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[PATCH] In virFDStreamRead(), fill buffer from this and next messages
by Erik Hulsmann 04 Feb '26

04 Feb '26

Before this change, buffers returned from virFDStreamRead() would alternate in size (262120 and 24), because it only consumed the bytes remaining from the current background thread message. As the background thread reads 262144 bytes (256kB) of data in each chunk, where the maximum size returned from virFDStreamRead() to be transferred over the remote protocol is only 262120, 24 bytes would be left in the buffer on each iteration. The next iteration leaves 24 bytes, which used to be returned without considering messages waiting in the queue. Signed-off-by: Erik Huelsmann <ehuels(a)gmail.com> --- src/util/virfdstream.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/src/util/virfdstream.c b/src/util/virfdstream.c index 26a1f00..4c974ba 100644 --- a/src/util/virfdstream.c +++ b/src/util/virfdstream.c @@ -905,7 +905,10 @@ static int virFDStreamRead(virStreamPtr st, char *bytes, size_t nbytes) if (fdst->thread) { virFDStreamMsg *msg = NULL; + size_t got = 0; + size_t bsz = 0; + more: while (!(msg = fdst->msg)) { if (fdst->threadQuit || fdst->threadErr) { if (nbytes) { @@ -917,7 +920,7 @@ static int virFDStreamRead(virStreamPtr st, char *bytes, size_t nbytes) virReportSystemError(EBADF, "%s", _("stream is not open")); } else { - ret = 0; + ret = got; } goto cleanup; } else { @@ -931,7 +934,7 @@ static int virFDStreamRead(virStreamPtr st, char *bytes, size_t nbytes) * return 0 immediately. */ if (msg->type == VIR_FDSTREAM_MSG_TYPE_HOLE && msg->stream.hole.len == 0) { - ret = 0; + ret = got; goto cleanup; } @@ -942,21 +945,26 @@ static int virFDStreamRead(virStreamPtr st, char *bytes, size_t nbytes) goto cleanup; } - if (nbytes > msg->stream.data.len - msg->stream.data.offset) - nbytes = msg->stream.data.len - msg->stream.data.offset; + bsz = msg->stream.data.len - msg->stream.data.offset; + if (nbytes < bsz) + bsz = nbytes; - memcpy(bytes, + memcpy(bytes + got, msg->stream.data.buf + msg->stream.data.offset, - nbytes); + bsz); + got += bsz; + nbytes -= bsz; - msg->stream.data.offset += nbytes; + msg->stream.data.offset += bsz; if (msg->stream.data.offset == msg->stream.data.len) { virFDStreamMsgQueuePop(fdst, fdst->fd, "pipe"); virFDStreamMsgFree(msg); } - ret = nbytes; - + ret = got; + if (nbytes > 0) { + goto more; + } } else { retry: ret = read(fdst->fd, bytes, nbytes); -- 2.43.0

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Download of volume: alternating frames of 262120 and 24 bytes
by Erik Huelsmann 04 Feb '26

04 Feb '26

Hi, While analysing traffic generated by "virsh vol-download", I noticed that the download stream exhibits the following pattern (over qemu+ssh://): <Start> Read 4 bytes (= frame length field) Read 262144 bytes (= header + payload ; VIR_NET_MESSAGE_HEADER_MAX (24) + VIR_NET_MESSAGE_LEGACY_PAYLOAD_MAX (262120)) Read 4 bytes (= frame length field) Read 48 bytes (= header + payload) <Go back to Start> While nothing seems to be actually wrong with this pattern, the average payload on large data transfers is only (262120+24)/2 == 131072 and the CPU makes double the iterations necessary. I'll be trying to figure out where this comes from, but I imagine that will be pretty hard to track down. Two questions: 1. Do you see the same thing? 2. Any ideas/hints where I could start looking? Regards, -- Bye, Erik. http://efficito.com -- Hosted accounting and ERP. Robust and Flexible. No vendor lock-in.

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[PATCH v3 0/1] bhyve: improve loader handling on arm64
by Roman Bogorodskiy 04 Feb '26

04 Feb '26

Changes from v2: - Incorporate changes from Michal - Update *.aug{.in} files - Drop patch 2/2 with DATADIR substitution in bhyve.conf Roman Bogorodskiy (1): bhyve: improve loader handling on arm64 src/bhyve/bhyve.conf | 5 ++++ src/bhyve/bhyve_conf.c | 8 +++++++ src/bhyve/bhyve_domain.c | 23 +++++++++++++++++++ src/bhyve/bhyve_utils.h | 2 ++ src/bhyve/libvirtd_bhyve.aug | 3 ++- src/bhyve/test_libvirtd_bhyve.aug.in | 1 + .../aarch64/bhyvexml2argv-base.args | 1 + .../aarch64/bhyvexml2argv-base.ldargs | 8 +------ .../aarch64/bhyvexml2argv-console.args | 1 + .../aarch64/bhyvexml2argv-console.ldargs | 8 +------ tests/bhyvexml2argvmock.c | 20 +++++++++++++++- tests/bhyvexml2argvtest.c | 2 ++ .../aarch64/bhyvexml2xmlout-base.xml | 1 + .../aarch64/bhyvexml2xmlout-console.xml | 1 + tests/bhyvexml2xmltest.c | 7 ++++++ 15 files changed, 75 insertions(+), 16 deletions(-) -- 2.52.0

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[PATCH v2 0/2] bhyve: improve loader handling on arm64
by Roman Bogorodskiy 04 Feb '26

04 Feb '26

Changes since v1: - Make the default loader uboot path configurable in bhyve.conf. It might be useful for users and also way simpler to mock in the test than the hardcoded value in the code. Roman Bogorodskiy (2): bhyve: improve loader handling on arm64 bhyve: conf: do not hardcode datadir in bhyve.conf src/bhyve/{bhyve.conf => bhyve.conf.in} | 7 +++++- src/bhyve/bhyve_conf.c | 8 +++++++ src/bhyve/bhyve_domain.c | 23 +++++++++++++++++++ src/bhyve/bhyve_utils.h | 2 ++ src/bhyve/meson.build | 13 +++++++++-- .../aarch64/bhyvexml2argv-base.args | 1 + .../aarch64/bhyvexml2argv-base.ldargs | 8 +------ .../aarch64/bhyvexml2argv-console.args | 1 + .../aarch64/bhyvexml2argv-console.ldargs | 8 +------ tests/bhyvexml2argvmock.c | 20 +++++++++++++++- tests/bhyvexml2argvtest.c | 2 ++ .../aarch64/bhyvexml2xmlout-base.xml | 1 + .../aarch64/bhyvexml2xmlout-console.xml | 1 + tests/bhyvexml2xmltest.c | 4 ++++ 14 files changed, 81 insertions(+), 18 deletions(-) rename src/bhyve/{bhyve.conf => bhyve.conf.in} (73%) -- 2.52.0

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[PATCH 0/9] bhyve: A couple of memleak fixes
by Michal Privoznik 04 Feb '26

04 Feb '26

*** BLURB HERE *** Michal Prívozník (9): bhyve: Avoid memleak in bhyveParsePassthru() bhyve: Avoid leaking @addrs in bhyveDomainAssignPCIAddresses() bhyve_command: Avoid leaking @buf in virBhyveProcessBuildBhyveCmd() bhyve_command: Avoid memleak in bhyveBuildNetArgStr() bhyvexml2argvmock: Provide virCPUProbeHost() bhyvexml2argvtest: Avoid leaking driver caps bhyvexml2argvtest: Don't leak parts of driver config bhyvexml2argvtest: Avoid leaking firmwareDir bhyvexml2xmltest: Avoid leaking driver caps src/bhyve/bhyve_command.c | 26 ++++++++++++-------------- src/bhyve/bhyve_device.c | 10 +++++++--- src/bhyve/bhyve_parse_command.c | 2 +- tests/bhyvexml2argvmock.c | 8 ++++++++ tests/bhyvexml2argvtest.c | 10 +++++++--- tests/bhyvexml2xmltest.c | 1 + 6 files changed, 36 insertions(+), 21 deletions(-) -- 2.52.0

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[PATCH] rpcgen: Pass XDRPROC_T_3ARGS to test_demo.c
by Michal Privoznik 04 Feb '26

04 Feb '26

From: Michal Privoznik <mprivozn(a)redhat.com> In previous commit of v12.0.0-85-g2c66b6d72c we've tried to solve a problem where xdrproc_t is a prototype of a function which takes only two arguments instead of three. See original commit for more info. The fix consists of a config time check and setting XDRPROC_T_3ARGS accordingly (in meson-config.h). This works for nearly all of our code, except rpcgen which is intentionally independent of the rest of the code. Therefore, the macro has to be set extra - by specifying it on the compiler cmd line. Fixes: 2c66b6d72cd48d3cf80f957f55cfb1548feb46c4 Signed-off-by: Michal Privoznik <mprivozn(a)redhat.com> --- scripts/rpcgen/tests/meson.build | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/rpcgen/tests/meson.build b/scripts/rpcgen/tests/meson.build index 057a61433d..4df7471a99 100644 --- a/scripts/rpcgen/tests/meson.build +++ b/scripts/rpcgen/tests/meson.build @@ -4,13 +4,17 @@ rpcgen_tests = files([ 'test_parser.py', ]) +xdrproc_flags = [] +if conf.has('XDRPROC_T_3ARGS') + xdrproc_flags += [ '-DXDRPROC_T_3ARGS' ] +endif test_demo = executable( 'test_demo', [ 'test_demo.c' ], c_args: [ '-Dabs_srcdir="@0@"'.format(meson.current_source_dir()), - ] + cc_flags_relaxed_frame_limit, + ] + cc_flags_relaxed_frame_limit + xdrproc_flags, dependencies: [ xdr_dep, glib_dep ], -- 2.52.0

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[PATCH] build: add detection of xdrproc_t arguments count
by Roman Bogorodskiy 04 Feb '26

04 Feb '26

According to 9fa3a8ab6fd82ad2f5a14b490696085061418718, macOS insists on passing 3 arguments for xdrproc_t. Passing 3 arguments was a good common ground, but since recently[1] FreeBSD only accepts 2 arguments. Add a meson.build check whether 3 arguments are accepted, and add macros which passes either 2 or 3 arguments to xdrproc_t based on the result of this check. 1: https://cgit.freebsd.org/src/commit/?id=ac5a19ec6989675c8ec6c3ca245dba243d1… Signed-off-by: Roman Bogorodskiy <bogorodskiy(a)gmail.com> --- meson.build | 19 +++++++++++++++++++ scripts/rpcgen/tests/test_demo.c | 12 +++++++++--- src/rpc/virnetmessage.c | 10 ++++++++-- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/meson.build b/meson.build index 964d1fa4e1..4a4f89c1cb 100644 --- a/meson.build +++ b/meson.build @@ -893,6 +893,25 @@ else xdr_dep = dependency('', required: false) endif +if xdr_dep.found() + xdrproc_3arg_code = ''' + #include <rpc/xdr.h> + + bool_t test_filter(XDR *xdr, void *data, unsigned int opaque_flags) { + return TRUE; + } + + int main() { + XDR xdr; + xdrproc_t filter = (xdrproc_t)&test_filter; + (*filter)(&xdr, NULL, 0); + return 0; + } + ''' + if cc.compiles(xdrproc_3arg_code, dependencies: xdr_dep) + conf.set('XDRPROC_T_3ARGS', 1) + endif +endif # generic build dependencies diff --git a/scripts/rpcgen/tests/test_demo.c b/scripts/rpcgen/tests/test_demo.c index e6ba7ddbc5..82eda89592 100644 --- a/scripts/rpcgen/tests/test_demo.c +++ b/scripts/rpcgen/tests/test_demo.c @@ -8,6 +8,12 @@ # define xdr_uint64_t xdr_u_int64_t #endif +#if defined(XDRPROC_T_3ARGS) +# define XDRPROC(proc, xdr, data) (proc(&xdr, data, 0)) +#else +# define XDRPROC(proc, xdr, data) (proc(&xdr, data)) +#endif + #include "demo.h" #include "demo.c" @@ -27,7 +33,7 @@ static void test_xdr(xdrproc_t proc, void *vorig, void *vnew, const char *testna /* Step 1: serialize the vorig and compare to the data in test .bin files */ xdrmem_create(&xdr, buf, buflen, XDR_ENCODE); - ret = !!proc(&xdr, vorig, 0); + ret = !!XDRPROC(proc, xdr, vorig); g_assert_cmpint(ret, ==, !fail); if (fail) @@ -54,7 +60,7 @@ static void test_xdr(xdrproc_t proc, void *vorig, void *vnew, const char *testna /* Step 2: de-serialize the state to create a new object */ xdrmem_create(&xdr, buf, buflen, XDR_DECODE); - ret = !!proc(&xdr, vnew, 0); + ret = !!XDRPROC(proc, xdr, vnew); g_assert_cmpint(ret, ==, true); actlen = xdr_getpos(&xdr); @@ -68,7 +74,7 @@ static void test_xdr(xdrproc_t proc, void *vorig, void *vnew, const char *testna xdrmem_create(&xdr, buf, buflen, XDR_ENCODE); - ret = !!proc(&xdr, vnew, 0); + ret = !!XDRPROC(proc, xdr, vnew); g_assert_cmpint(ret, ==, true); actlen = xdr_getpos(&xdr); diff --git a/src/rpc/virnetmessage.c b/src/rpc/virnetmessage.c index af0f9cb30b..e66df5c9e2 100644 --- a/src/rpc/virnetmessage.c +++ b/src/rpc/virnetmessage.c @@ -34,6 +34,12 @@ VIR_LOG_INIT("rpc.netmessage"); +#if defined(XDRPROC_T_3ARGS) +# define XDRPROC_FILTER(filter, xdr, data) ((*filter)(&xdr, data, 0)) +#else +# define XDRPROC_FILTER(filter, xdr, data) ((*filter)(&xdr, data)) +#endif + virNetMessage *virNetMessageNew(bool tracked) { virNetMessage *msg; @@ -367,7 +373,7 @@ int virNetMessageEncodePayload(virNetMessage *msg, msg->bufferLength - msg->bufferOffset, XDR_ENCODE); /* Try to encode the payload. If the buffer is too small increase it. */ - while (!(*filter)(&xdr, data, 0)) { + while (!XDRPROC_FILTER(*filter, xdr, data)) { unsigned int newlen = msg->bufferLength - VIR_NET_MESSAGE_LEN_MAX; newlen *= 2; @@ -424,7 +430,7 @@ int virNetMessageDecodePayload(virNetMessage *msg, xdrmem_create(&xdr, msg->buffer + msg->bufferOffset, msg->bufferLength - msg->bufferOffset, XDR_DECODE); - if (!(*filter)(&xdr, data, 0)) { + if (!XDRPROC_FILTER(*filter, xdr, data)) { virReportError(VIR_ERR_RPC, "%s", _("Unable to decode message payload")); goto error; } -- 2.52.0

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[RFC PATCH v5 0/7] riscv: add initial sdext support
by Chao Liu 03 Feb '26

03 Feb '26

Hi, Per Daniel's review feedback, this v5 series is based on Alistair's riscv-to-apply.next branch [3]. It depends on patches 1-5 of Max Chou's "Add Zvfbfa extension support" v2 series (not included; apply them first) [2]. It is based on RISC-V Debug Specification 1.0 [1]. It introduces the sdext/sdtrig config bits, DCSR/DPC/DSCRATCH state, Debug Mode enter/leave helpers, DRET, EBREAK entry, single-step, and trigger action=debug mode. To reduce review load, this series focuses on the Sdext features first. The Debug Module (DM) and related flows will follow in a later series. Changes in v5: - Patch 2: removed redundant `cpu->cfg.ext_sdext = false;` in riscv_cpu_init() since it's already set to false in MULTI_EXT_CFG_BOOL. (Daniel) - Patch 7: changed LOG_UNIMP to LOG_GUEST_ERROR for invalid trigger action=debug mode when Sdext is not enabled. LOG_UNIMP is reserved for unimplemented features, while LOG_GUEST_ERROR is for invalid guest actions. (Daniel) Changes in v4: - Fixed linux-user build errors: moved debug_mode/dcsr/dpc/dscratch fields inside #ifndef CONFIG_USER_ONLY block in cpu.h, and wrapped all code using these fields with proper guards. (Daniel) - Updated dependency from single patch (patch 5 only) to patches 1-5 of Max Chou's "Add Zvfbfa extension support" v2 series to avoid compilation errors. Changes in v3: - Rebase onto Alistair's riscv-to-apply.next branch. - Depend on Max Chou's patch "target/riscv: Use the tb->cs_bqse as the extend tb flags." (not included; apply it first) [2]. - Patch 2: default sdext to false in riscv_cpu_extensions[]. Changes in v2: - Drop the RHCT expected AML update from this series. - Replace the split sdext/sdtrig config bits patch with deprecating the 'debug' CPU property. - Rebase and update patch subjects to target/riscv prefix. Changes in v1: - Debug Mode entry/exit updates DCSR/DPC and restores execution via DRET. - EBREAK honors DCSR ebreak bits and enters Debug Mode when enabled. - Single-step uses DCSR.STEP with a TB flag and a helper at TB exit. It references Max Chou's patch "target/riscv: Use the tb->cs_bqse as the extend tb flags." [2]. - Sdtrig supports action=debug mode for mcontrol/mcontrol6 and reports inst-count triggers in tinfo. Differences vs Debug Spec (known gaps): - No Debug Module (no DMI, dmcontrol/dmstatus, haltreq/resumereq). - No debug ROM, program buffer, abstract commands, or SBA. - Resume is modeled by leaving Debug Mode at cpu_exec_enter. - Step/exception ordering is simplified: if the stepped instruction traps, the normal exception is taken and Debug Mode is not forced. - Several DCSR fields are not fully modeled (stopcount/stoptime, etc). Roadmap (next stage, DM focus): 1) Add a DM core with DMI access and hart state tracking. 2) Implement halt/resume handshake and move Debug Mode transitions under DM control. 3) Add debug ROM, program buffer, and abstract commands for GPR/CSR and memory access. 4) Add SBA if required by tooling. 5) Tighten ordering rules for step/exception/trigger priorities. References: [1] https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 [2] https://lore.kernel.org/qemu-devel/20260108132631.9429-1-max.chou@sifive.co… [3] https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks, Chao Chao Liu (6): target/riscv: add sdext debug CSRs state target/riscv: add sdext Debug Mode helpers target/riscv: add dret instruction target/riscv: add sdext enter Debug Mode on ebreak target/riscv: add sdext single-step support target/riscv: add sdtrig trigger action=debug mode Daniel Henrique Barboza (1): target/riscv: deprecate 'debug' CPU property docs/about/deprecated.rst | 7 + include/exec/translation-block.h | 4 +- target/riscv/cpu.c | 59 +++++++- target/riscv/cpu.h | 9 ++ target/riscv/cpu_bits.h | 33 +++++ target/riscv/cpu_cfg_fields.h.inc | 3 +- target/riscv/cpu_helper.c | 90 ++++++++++++ target/riscv/csr.c | 128 +++++++++++++++++- target/riscv/debug.c | 58 +++++++- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 24 ++++ target/riscv/machine.c | 44 ++++-- target/riscv/op_helper.c | 70 ++++++++++ target/riscv/tcg/tcg-cpu.c | 21 ++- target/riscv/translate.c | 16 ++- 16 files changed, 545 insertions(+), 25 deletions(-) -- 2.53.0

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[RFC PATCH] Prioritise and validate cgroup2 canonical mount on /sys/fs/cgroup
by Rogério Vinhal Nunes 03 Feb '26

03 Feb '26

Hey folks, we've gotten an issue with how libvirt is currently detecting the cgroup2 mounts. Basically we expose cgroup2 mounts in a container from the host-level and libvirt was selecting that instead of the container-level mount, which uses the canonical path. The current logic basically iterate on the mounts until it finds a cgroup2 mount and uses that. If there's multiple, it will override until the last one is read, which is not very safe. I've cut a quick patch that should: 1. Validate that the mount is actually an existing directory in the context 2. Prefer the canonical mount (/sys/fs/cgroup) if it's available 3. only override it once, so it will not go through lists of mounts overriding up to the end I'm happy to get some feedback here especially on step 3 as I'm not very sure how we should proceed on non-canonical situations or if we should at all. Maybe the best solution is to just use the canonical path? From 4a0bf5c5b1e1cd4e0393981a25e1407d29beb43e Mon Sep 17 00:00:00 2001 From: Rogerio Vinhal Nunes <rogervn(a)meta.com> Date: Mon, 2 Feb 2026 19:24:52 +0000 Subject: [PATCH] Preferred /sys/fs/cgroup as a canonical mount but also verifies if the mount is an existing directory in the namespace. The reason for this is preventing that mounts that are not visible in the container namespace or additional cgroupv2 mounts to share host context might be incorrectly taken as targets here. --- src/util/vircgroupv2.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/util/vircgroupv2.c b/src/util/vircgroupv2.c index eaf5ae98f6..aa8c950691 100644 --- a/src/util/vircgroupv2.c +++ b/src/util/vircgroupv2.c @@ -23,6 +23,7 @@ #ifdef __linux__ # include <mntent.h> # include <sys/mount.h> +# include <sys/stat.h> #endif /* __linux__ */ #include "internal.h" @@ -46,6 +47,8 @@ VIR_LOG_INIT("util.cgroup"); #define VIR_FROM_THIS VIR_FROM_CGROUP +#define VIR_CGROUP_SYSFS_MOUNT "/sys/fs/cgroup" + VIR_ENUM_DECL(virCgroupV2Controller); VIR_ENUM_IMPL(virCgroupV2Controller, VIR_CGROUP_CONTROLLER_LAST, @@ -173,12 +176,26 @@ virCgroupV2DetectMounts(virCgroup *group, const char *mntOpts G_GNUC_UNUSED, const char *mntDir) { + struct stat sb; + if (STRNEQ(mntType, "cgroup2")) return 0; - VIR_FREE(group->unified.mountPoint); + if (stat(mntDir, &sb) < 0 || !S_ISDIR(sb.st_mode)) { + VIR_DEBUG("Skipping non-directory cgroup2 mount: %s", mntDir); + return 0; + } + + /* Always prefer /sys/fs/cgroup as the canonical mount point. + * If we already have /sys/fs/cgroup, don't override it. + * Otherwise, use the first valid directory we find as fallback. */ + if (STREQ(mntDir, VIR_CGROUP_SYSFS_MOUNT)) { + VIR_FREE(group->unified.mountPoint); + group->unified.mountPoint = g_strdup(mntDir); + } else if (!group->unified.mountPoint) { + group->unified.mountPoint = g_strdup(mntDir); + } - group->unified.mountPoint = g_strdup(mntDir); return 0; } -- 2.52.0

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[RFC PATCH v4 0/7] riscv: add initial sdext support
by Chao Liu 03 Feb '26

03 Feb '26

Hi, Per Daniel's review feedback, this v4 series is based on Alistair's riscv-to-apply.next branch [3]. It depends on patches 1-5 of Max Chou's "Add Zvfbfa extension support" v2 series (not included; apply them first) [2]. It is based on RISC-V Debug Specification 1.0 [1]. It introduces the sdext/sdtrig config bits, DCSR/DPC/DSCRATCH state, Debug Mode enter/leave helpers, DRET, EBREAK entry, single-step, and trigger action=debug mode. To reduce review load, this series focuses on the Sdext features first. The Debug Module (DM) and related flows will follow in a later series. Changes in v4: - Fixed linux-user build errors: moved debug_mode/dcsr/dpc/dscratch fields inside #ifndef CONFIG_USER_ONLY block in cpu.h, and wrapped all code using these fields with proper guards. (Daniel) - Updated dependency from single patch (patch 5 only) to patches 1-5 of Max Chou's "Add Zvfbfa extension support" v2 series to avoid compilation errors. Changes in v3: - Rebase onto Alistair's riscv-to-apply.next branch. - Depend on Max Chou's patch "target/riscv: Use the tb->cs_bqse as the extend tb flags." (not included; apply it first) [2]. - Patch 2: default sdext to false in riscv_cpu_extensions[]. Changes in v2: - Drop the RHCT expected AML update from this series. - Replace the split sdext/sdtrig config bits patch with deprecating the 'debug' CPU property. - Rebase and update patch subjects to target/riscv prefix. Changes in v1: - Debug Mode entry/exit updates DCSR/DPC and restores execution via DRET. - EBREAK honors DCSR ebreak bits and enters Debug Mode when enabled. - Single-step uses DCSR.STEP with a TB flag and a helper at TB exit. It references Max Chou's patch "target/riscv: Use the tb->cs_bqse as the extend tb flags." [2]. - Sdtrig supports action=debug mode for mcontrol/mcontrol6 and reports inst-count triggers in tinfo. Differences vs Debug Spec (known gaps): - No Debug Module (no DMI, dmcontrol/dmstatus, haltreq/resumereq). - No debug ROM, program buffer, abstract commands, or SBA. - Resume is modeled by leaving Debug Mode at cpu_exec_enter. - Step/exception ordering is simplified: if the stepped instruction traps, the normal exception is taken and Debug Mode is not forced. - Several DCSR fields are not fully modeled (stopcount/stoptime, etc). Roadmap (next stage, DM focus): 1) Add a DM core with DMI access and hart state tracking. 2) Implement halt/resume handshake and move Debug Mode transitions under DM control. 3) Add debug ROM, program buffer, and abstract commands for GPR/CSR and memory access. 4) Add SBA if required by tooling. 5) Tighten ordering rules for step/exception/trigger priorities. References: [1] https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 [2] https://lore.kernel.org/qemu-devel/20260108132631.9429-1-max.chou@sifive.co… [3] https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks, Chao Chao Liu (6): target/riscv: add sdext debug CSRs state target/riscv: add sdext Debug Mode helpers target/riscv: add dret instruction target/riscv: add sdext enter Debug Mode on ebreak target/riscv: add sdext single-step support target/riscv: add sdtrig trigger action=debug mode Daniel Henrique Barboza (1): target/riscv: deprecate 'debug' CPU property docs/about/deprecated.rst | 7 + include/exec/translation-block.h | 4 +- target/riscv/cpu.c | 62 ++++++++- target/riscv/cpu.h | 9 ++ target/riscv/cpu_bits.h | 33 +++++ target/riscv/cpu_cfg_fields.h.inc | 3 +- target/riscv/cpu_helper.c | 90 ++++++++++++ target/riscv/csr.c | 128 +++++++++++++++++- target/riscv/debug.c | 58 +++++++- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 24 ++++ target/riscv/machine.c | 44 ++++-- target/riscv/op_helper.c | 70 ++++++++++ target/riscv/tcg/tcg-cpu.c | 21 ++- target/riscv/translate.c | 16 ++- 16 files changed, 548 insertions(+), 25 deletions(-) -- 2.52.0

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