Re: [libvirt] [Qemu-devel] Configuring pflash devices for OVMF firmware
> This is all greek to me. I take it there's something wrong
with these
> accelerators that makes (read-only?) flash memory not work, even
> though the read-only mapping we now create for traditional BIOS works.
> Weird, but I'm of course willing to take your word for it.
Yes, as I wrote in the other message even read-only flash memory
supports commands, and these accelerators do not support direct reads + MMIO writes on the
same memory slot.
At least I checked HAX code and it doesn't; I don't know about WHPX.
(CC'd Yu Ning @ Intel's HAXM team)
Not sure, if I'm understanding the issue correctly, but isn't
`HAX_VM_IOCTL_SET_RAM2` with the `HAX_RAM_INFO_ROM` flag precisely what you are looking
for?
More precisely, HAX_VM_IOCTL_SET_RAM2 maps an HVA range to a GPA range, the
HAX_RAM_INFO_ROM flag should allow only guest memory reads to that range [1]. When the
guest attempts to write, this should trigger a VM exit that will be handled by QEMU. Also,
this seems to be handled here:
https://github.com/qemu/qemu/blob/15bede554162dda822cd762c689edb6fa32b6e3...
Best,
Alexandro
[1] https://github.com/intel/haxm/blob/master/docs/api.md