On May 15, 2025, at 6:54 AM, Daniel P. Berrangé
<berrange(a)redhat.com> wrote:
On Wed, May 14, 2025 at 05:18:50PM -0700, Matthew R. Ochs wrote:
> Add support for generating QEMU command line with PCI high memory MMIO size:
> - Add highmem-mmio-size to machine command line generation using
> size conveyed through pcihole64
> - Add validation for aarch64/virt machine type requirement
> - Add capability check for QEMU support
>
> This enables configuring the PCI high memory MMIO window size
> for aarch64 virt machine types using the existing pcihole64
> element.
>
> Signed-off-by: Matthew R. Ochs <mochs(a)nvidia.com>
> ---
> src/qemu/qemu_command.c | 14 +++++++++++++-
> src/qemu/qemu_validate.c | 8 ++++++--
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/src/qemu/qemu_command.c b/src/qemu/qemu_command.c
> index e6d308534f87..1386b2772a55 100644
> --- a/src/qemu/qemu_command.c
> +++ b/src/qemu/qemu_command.c
> @@ -6195,7 +6195,8 @@ qemuBuildGlobalControllerCommandLine(virCommand *cmd,
> for (i = 0; i < def->ncontrollers; i++) {
> virDomainControllerDef *cont = def->controllers[i];
> if (cont->type == VIR_DOMAIN_CONTROLLER_TYPE_PCI &&
> - cont->opts.pciopts.pcihole64) {
> + cont->opts.pciopts.pcihole64 &&
> + !qemuDomainIsARMVirt(def)) {
This ought to be a positive check
..IsQ35(..) || ..IsI440FX(..)
Makes sense, will fix in v3.
>
> diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c
> index b2c3c9e2f631..f808aac1063a 100644
> --- a/src/qemu/qemu_validate.c
> +++ b/src/qemu/qemu_validate.c
> @@ -4074,7 +4074,9 @@ qemuValidateDomainDeviceDefControllerPCI(const
virDomainControllerDef *cont,
> switch ((virDomainControllerModelPCI) cont->model) {
> case VIR_DOMAIN_CONTROLLER_MODEL_PCI_ROOT:
> if (pciopts->pcihole64 || pciopts->pcihole64size != 0) {
> - if (!qemuDomainIsI440FX(def)) {
> + if (!qemuDomainIsI440FX(def) &&
> + !(qemuDomainIsARMVirt(def) && virQEMUCapsGet(qemuCaps,
> +
QEMU_CAPS_MACHINE_VIRT_HIGHMEM_MMIO_SIZE))) {
> virReportError(VIR_ERR_CONFIG_UNSUPPORTED,
> _("Setting the 64-bit PCI hole size is not
supported for machine '%1$s'"),
> def->os.machine);
IIUC arm virt machine is always PCI-E, so we shouldn't allow it
for arm here.
Yep, will remove this change in v3.