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[libvirt] [PATCH 3/4] cputest: Add CPUID data for Hygon Dhyana 7185 32-core Processor
by Yingle Hou 21 Nov '19
by Yingle Hou 21 Nov '19
21 Nov '19
Add Hygon Dhyana CPU data test case related files.
Signed-off-by: Yingle Hou <houyingle(a)hygon.cn>
---
tests/cputest.c | 1 +
...86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml | 7 +
...x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml | 9 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml | 16 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-host.xml | 17 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-json.xml | 12 +
.../x86_64-cpuid-Hygon-C86-7185-32-core.json | 1631 ++++++++++++++++++++
.../x86_64-cpuid-Hygon-C86-7185-32-core.sig | 4 +
.../x86_64-cpuid-Hygon-C86-7185-32-core.xml | 54 +
9 files changed, 1751 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.xml
diff --git a/tests/cputest.c b/tests/cputest.c
index b883ba7..0bd62ee 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -1243,6 +1243,7 @@ mymain(void)
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-8700", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-E6850", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-Q9500", JSON_NONE);
+ DO_TEST_CPUID(VIR_ARCH_X86_64, "Hygon-C86-7185-32-core", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "EPYC-7601-32-Core", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "EPYC-7601-32-Core-ibpb", JSON_MODELS_REQUIRED);
DO_TEST_CPUID(VIR_ARCH_X86_64, "FX-8150", JSON_NONE);
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml
new file mode 100644
index 0000000..747d725
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml
@@ -0,0 +1,7 @@
+<!-- Features disabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x08000008' edx='0x10000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000008' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x01c2300c' edx='0x00000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml
new file mode 100644
index 0000000..fcefcf7
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml
@@ -0,0 +1,9 @@
+<!-- Features enabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0xf5f83201' edx='0x078bfbff'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x009c01ab' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000007' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x000003f3' edx='0x2e500800'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x00000000' ebx='0x02001000' ecx='0x00000000' edx='0x00000000'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml
new file mode 100644
index 0000000..c2541b3
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml
@@ -0,0 +1,16 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Dhyana</model>
+ <vendor>Hygon</vendor>
+ <feature policy='require' name='ht'/>
+ <feature policy='require' name='osxsave'/>
+ <feature policy='require' name='xsaves'/>
+ <feature policy='require' name='cmp_legacy'/>
+ <feature policy='require' name='extapic'/>
+ <feature policy='require' name='skinit'/>
+ <feature policy='require' name='wdt'/>
+ <feature policy='require' name='tce'/>
+ <feature policy='require' name='topoext'/>
+ <feature policy='require' name='perfctr_core'/>
+ <feature policy='require' name='perfctr_nb'/>
+ <feature policy='require' name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-host.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-host.xml
new file mode 100644
index 0000000..5199708
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-host.xml
@@ -0,0 +1,17 @@
+<cpu>
+ <arch>x86_64</arch>
+ <model>Dhyana</model>
+ <vendor>Hygon</vendor>
+ <feature name='ht'/>
+ <feature name='osxsave'/>
+ <feature name='xsaves'/>
+ <feature name='cmp_legacy'/>
+ <feature name='extapic'/>
+ <feature name='skinit'/>
+ <feature name='wdt'/>
+ <feature name='tce'/>
+ <feature name='topoext'/>
+ <feature name='perfctr_core'/>
+ <feature name='perfctr_nb'/>
+ <feature name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-json.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-json.xml
new file mode 100644
index 0000000..d3003b6
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-json.xml
@@ -0,0 +1,12 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Dhyana</model>
+ <vendor>Hygon</vendor>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='tsc-deadline'/>
+ <feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='cmp_legacy'/>
+ <feature policy='require' name='virt-ssbd'/>
+ <feature policy='disable' name='monitor'/>
+ <feature policy='disable' name='svm'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.json b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.json
new file mode 100644
index 0000000..1d06d05
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.json
@@ -0,0 +1,1631 @@
+{
+ "return": {
+ "model": {
+ "name": "base",
+ "props": {
+ "phys-bits": 0,
+ "core-id": -1,
+ "xlevel": 2147483674,
+ "cmov": true,
+ "ia64": false,
+ "ssb-no": false,
+ "aes": false,
+ "mmx": true,
+ "rdpid": false,
+ "arat": true,
+ "gfni": false,
+ "ibrs-all": false,
+ "pause-filter": false,
+ "xsavec": true,
+ "intel-pt": false,
+ "hv-frequencies": false,
+ "tsc-frequency": 0,
+ "xd": true,
+ "x-intel-pt-auto-level": true,
+ "hv-vendor-id": "",
+ "kvm-asyncpf": true,
+ "kvm_asyncpf": true,
+ "perfctr_core": false,
+ "perfctr-core": false,
+ "mpx": false,
+ "pbe": false,
+ "decodeassists": false,
+ "avx512cd": false,
+ "sse4_1": true,
+ "sse4.1": true,
+ "sse4-1": true,
+ "family": 24,
+ "legacy-cache": true,
+ "host-phys-bits-limit": 0,
+ "vmware-cpuid-freq": true,
+ "wbnoinvd": false,
+ "avx512f": false,
+ "hv-stimer-direct": false,
+ "msr": true,
+ "mce": true,
+ "mca": true,
+ "hv-runtime": false,
+ "xcrypt": false,
+ "thread-id": -1,
+ "min-level": 13,
+ "xgetbv1": true,
+ "cid": false,
+ "hv-relaxed": false,
+ "hv-crash": false,
+ "ds": false,
+ "fxsr": true,
+ "xsaveopt": true,
+ "xtpr": false,
+ "hv-evmcs": false,
+ "avx512vl": false,
+ "avx512-vpopcntdq": false,
+ "phe": false,
+ "extapic": false,
+ "3dnowprefetch": true,
+ "avx512vbmi2": false,
+ "cr8legacy": true,
+ "stibp": false,
+ "cpuid-0xb": true,
+ "xcrypt-en": false,
+ "kvm_pv_eoi": true,
+ "apic-id": 4294967295,
+ "rsba": false,
+ "pn": false,
+ "dca": false,
+ "vendor": "HygonGenuine",
+ "hv-ipi": false,
+ "pku": false,
+ "smx": false,
+ "cmp_legacy": true,
+ "cmp-legacy": true,
+ "node-id": -1,
+ "avx512-4fmaps": false,
+ "vmcb_clean": false,
+ "vmcb-clean": false,
+ "3dnowext": false,
+ "amd-no-ssb": false,
+ "hle": false,
+ "npt": true,
+ "rdctl-no": false,
+ "memory": "/machine/unattached/system[0]",
+ "clwb": false,
+ "lbrv": false,
+ "adx": true,
+ "ss": false,
+ "pni": true,
+ "svm_lock": false,
+ "svm-lock": false,
+ "pfthreshold": false,
+ "smep": true,
+ "smap": true,
+ "x2apic": true,
+ "avx512vbmi": false,
+ "avx512vnni": false,
+ "hv-stimer": false,
+ "x-hv-synic-kvm-only": false,
+ "i64": true,
+ "flushbyasid": false,
+ "f16c": true,
+ "ace2-en": false,
+ "pat": true,
+ "pae": true,
+ "sse": true,
+ "die-id": -1,
+ "phe-en": false,
+ "kvm_nopiodelay": true,
+ "kvm-nopiodelay": true,
+ "tm": false,
+ "kvmclock-stable-bit": true,
+ "hypervisor": true,
+ "socket-id": -1,
+ "mds-no": false,
+ "pcommit": false,
+ "syscall": true,
+ "level": 13,
+ "avx512dq": false,
+ "x-migrate-smi-count": true,
+ "svm": false,
+ "full-cpuid-auto-level": true,
+ "hv-reset": false,
+ "invtsc": false,
+ "sse3": true,
+ "sse2": true,
+ "ssbd": false,
+ "est": false,
+ "avx512ifma": false,
+ "tm2": false,
+ "kvm-pv-ipi": false,
+ "kvm-pv-eoi": true,
+ "cx8": true,
+ "cldemote": false,
+ "hv-reenlightenment": false,
+ "kvm_mmu": false,
+ "kvm-mmu": false,
+ "sse4_2": true,
+ "sse4.2": true,
+ "sse4-2": true,
+ "pge": true,
+ "fill-mtrr-mask": true,
+ "avx512bitalg": false,
+ "nodeid_msr": false,
+ "pdcm": false,
+ "movbe": true,
+ "model": 0,
+ "nrip_save": true,
+ "nrip-save": true,
+ "kvm_pv_unhalt": true,
+ "ssse3": true,
+ "sse4a": true,
+ "invpcid": false,
+ "pdpe1gb": true,
+ "tsc-deadline": true,
+ "skip-l1dfl-vmentry": false,
+ "fma": true,
+ "cx16": true,
+ "de": true,
+ "enforce": false,
+ "stepping": 1,
+ "xsave": true,
+ "clflush": true,
+ "skinit": false,
+ "tsc": true,
+ "tce": false,
+ "fpu": true,
+ "ibs": false,
+ "ds_cpl": false,
+ "ds-cpl": false,
+ "host-phys-bits": false,
+ "fma4": false,
+ "la57": false,
+ "osvw": true,
+ "check": true,
+ "hv-spinlocks": 4294967295,
+ "pmu": false,
+ "pmm": false,
+ "apic": true,
+ "spec-ctrl": false,
+ "min-xlevel2": 0,
+ "tsc-adjust": true,
+ "tsc_adjust": true,
+ "kvm-steal-time": true,
+ "kvm_steal_time": true,
+ "kvmclock": true,
+ "l3-cache": true,
+ "lwp": false,
+ "hv-passthrough": false,
+ "amd-ssbd": false,
+ "ibpb": true,
+ "xop": false,
+ "avx": true,
+ "core-capability": false,
+ "movdiri": false,
+ "ace2": false,
+ "avx512bw": false,
+ "acpi": false,
+ "hv-vapic": false,
+ "fsgsbase": true,
+ "ht": false,
+ "nx": true,
+ "pclmulqdq": false,
+ "mmxext": true,
+ "vaes": false,
+ "popcnt": true,
+ "xsaves": false,
+ "movdir64b": false,
+ "tcg-cpuid": true,
+ "lm": true,
+ "umip": false,
+ "pse": true,
+ "avx2": true,
+ "sep": true,
+ "pclmuldq": false,
+ "virt-ssbd": true,
+ "x-hv-max-vps": -1,
+ "nodeid-msr": false,
+ "md-clear": false,
+ "split-lock-detect": false,
+ "kvm": true,
+ "misalignsse": true,
+ "min-xlevel": 2147483674,
+ "kvm-pv-unhalt": true,
+ "bmi2": true,
+ "bmi1": true,
+ "realized": false,
+ "tsc_scale": false,
+ "tsc-scale": false,
+ "topoext": false,
+ "hv-vpindex": false,
+ "xlevel2": 0,
+ "clflushopt": true,
+ "kvm-no-smi-migration": false,
+ "monitor": false,
+ "avx512er": false,
+ "pmm-en": false,
+ "pcid": false,
+ "arch-capabilities": false,
+ "3dnow": false,
+ "erms": false,
+ "x-force-features": false,
+ "lahf-lm": true,
+ "lahf_lm": true,
+ "vpclmulqdq": false,
+ "fxsr-opt": true,
+ "hv-synic": false,
+ "xstore": false,
+ "fxsr_opt": true,
+ "kvm-hint-dedicated": false,
+ "rtm": false,
+ "lmce": false,
+ "hv-time": false,
+ "perfctr-nb": false,
+ "perfctr_nb": false,
+ "ffxsr": true,
+ "hv-tlbflush": false,
+ "rdrand": true,
+ "rdseed": true,
+ "avx512-4vnniw": false,
+ "vmx": false,
+ "vme": true,
+ "dtes64": false,
+ "mtrr": true,
+ "rdtscp": true,
+ "pse36": true,
+ "kvm-pv-tlb-flush": false,
+ "tbm": false,
+ "wdt": false,
+ "pause_filter": false,
+ "sha-ni": false,
+ "model-id": "Hygon C86 7185 32-core Processor ",
+ "abm": true,
+ "avx512pf": false,
+ "xstore-en": false
+ }
+ }
+ },
+ "id": "model-expansion"
+}
+
+{
+ "return": [
+ {
+ "name": "max",
+ "typename": "max-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "host",
+ "typename": "host-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "base",
+ "typename": "base-x86_64-cpu",
+ "unavailable-features": [],
+ "static": true,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64-v1",
+ "typename": "qemu64-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64",
+ "typename": "qemu64-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "qemu64-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32-v1",
+ "typename": "qemu32-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32",
+ "typename": "qemu32-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "qemu32-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom-v1",
+ "typename": "phenom-v1-x86_64-cpu",
+ "unavailable-features": [
+ "3dnowext",
+ "3dnow"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom",
+ "typename": "phenom-x86_64-cpu",
+ "unavailable-features": [
+ "3dnowext",
+ "3dnow"
+ ],
+ "alias-of": "phenom-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3-v1",
+ "typename": "pentium3-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3",
+ "typename": "pentium3-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "pentium3-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2-v1",
+ "typename": "pentium2-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2",
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+ {
+ "name": "Haswell-noTSX",
+ "typename": "Haswell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "erms",
+ "invpcid"
+ ],
+ "alias-of": "Haswell-v2",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-IBRS",
+ "typename": "Haswell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "spec-ctrl"
+ ],
+ "alias-of": "Haswell-v3",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell",
+ "typename": "Haswell-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm"
+ ],
+ "alias-of": "Haswell-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-v2",
+ "typename": "EPYC-v2-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "sha-ni"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-v1",
+ "typename": "EPYC-v1-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "sha-ni"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-IBPB",
+ "typename": "EPYC-IBPB-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "sha-ni"
+ ],
+ "alias-of": "EPYC-v2",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC",
+ "typename": "EPYC-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "sha-ni"
+ ],
+ "alias-of": "EPYC-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Dhyana-v1",
+ "typename": "Dhyana-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Dhyana",
+ "typename": "Dhyana-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "Dhyana-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe-v1",
+ "typename": "Conroe-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe",
+ "typename": "Conroe-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "Conroe-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Cascadelake-Server-v2",
+ "typename": "Cascadelake-Server-v2-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "avx512vnni",
+ "spec-ctrl",
+ "arch-capabilities",
+ "ssbd",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku",
+ "rdctl-no",
+ "ibrs-all",
+ "skip-l1dfl-vmentry",
+ "mds-no"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Cascadelake-Server-v1",
+ "typename": "Cascadelake-Server-v1-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "avx512vnni",
+ "spec-ctrl",
+ "ssbd",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Cascadelake-Server",
+ "typename": "Cascadelake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "avx512vnni",
+ "spec-ctrl",
+ "ssbd",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "alias-of": "Cascadelake-Server-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-v4",
+ "typename": "Broadwell-v4-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "erms",
+ "invpcid",
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-v3",
+ "typename": "Broadwell-v3-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-v2",
+ "typename": "Broadwell-v2-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "erms",
+ "invpcid"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-v1",
+ "typename": "Broadwell-v1-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX-IBRS",
+ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "erms",
+ "invpcid",
+ "spec-ctrl"
+ ],
+ "alias-of": "Broadwell-v4",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX",
+ "typename": "Broadwell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "erms",
+ "invpcid"
+ ],
+ "alias-of": "Broadwell-v2",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-IBRS",
+ "typename": "Broadwell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm",
+ "spec-ctrl"
+ ],
+ "alias-of": "Broadwell-v3",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell",
+ "typename": "Broadwell-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "pcid",
+ "aes",
+ "hle",
+ "erms",
+ "invpcid",
+ "rtm"
+ ],
+ "alias-of": "Broadwell-v1",
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486-v1",
+ "typename": "486-v1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486",
+ "typename": "486-x86_64-cpu",
+ "unavailable-features": [],
+ "alias-of": "486-v1",
+ "static": false,
+ "migration-safe": true
+ }
+ ],
+ "id": "definitions"
+}
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.sig b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.sig
new file mode 100644
index 0000000..d511998
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.sig
@@ -0,0 +1,4 @@
+900f01
+family: 24 (0x18)
+model: 0 (0x00)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.xml b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.xml
new file mode 100644
index 0000000..7ea825b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.xml
@@ -0,0 +1,54 @@
+<!-- Hygon C86 7185 32-core Processor -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x0000000d' ebx='0x6f677948' ecx='0x656e6975' edx='0x6e65476e'/>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00900f01' ebx='0x3b400800' ecx='0x7cd83209' edx='0x178bfbff'/>
+ <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000005' ecx_in='0x00' eax='0x00000040' ebx='0x00000040' ecx='0x00000003' edx='0x00000011'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004' ebx='0x00000000' ecx='0x00000001' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x009c01a9' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000008' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000009' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000a' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000c' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x00' eax='0x00000007' ebx='0x00000340' ecx='0x00000340' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x0000000f' ebx='0x00000340' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x02' eax='0x00000100' ebx='0x00000240' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x8000001f' ebx='0x6f677948' ecx='0x656e6975' edx='0x6e65476e'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00900f01' ebx='0x40000000' ecx='0x35c233ff' edx='0x2fd3fbff'/>
+ <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x6f677948' ebx='0x3843206e' ecx='0x31372036' edx='0x33203538'/>
+ <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x6f632d32' ebx='0x50206572' ecx='0x65636f72' edx='0x726f7373'/>
+ <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x20202020' ebx='0x20202020' ecx='0x20202020' edx='0x00202020'/>
+ <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0xff40ff40' ebx='0xff40ff40' ecx='0x20080140' edx='0x40040140'/>
+ <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x36006400' ebx='0x56006400' ecx='0x02006140' edx='0x0200c140'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x0000001b' ecx='0x00000000' edx='0x00006599'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x00003030' ebx='0x00001007' ecx='0x0000603f' edx='0x00000000'/>
+ <cpuid eax_in='0x80000009' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000000a' ecx_in='0x00' eax='0x00000001' ebx='0x00008000' ecx='0x00000000' edx='0x0001bcff'/>
+ <cpuid eax_in='0x8000000b' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000000c' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000000d' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000000e' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000000f' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000010' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000011' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000012' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000013' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000014' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000015' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000016' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000017' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000018' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000019' ecx_in='0x00' eax='0xf040f040' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001a' ecx_in='0x00' eax='0x00000003' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001b' ecx_in='0x00' eax='0x000003ff' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001c' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001d' ecx_in='0x00' eax='0x00004121' ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001d' ecx_in='0x01' eax='0x00004122' ebx='0x00c0003f' ecx='0x000000ff' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001d' ecx_in='0x02' eax='0x00004143' ebx='0x01c0003f' ecx='0x000003ff' edx='0x00000002'/>
+ <cpuid eax_in='0x8000001d' ecx_in='0x03' eax='0x0001c163' ebx='0x03c0003f' ecx='0x00001fff' edx='0x00000001'/>
+ <cpuid eax_in='0x8000001e' ecx_in='0x00' eax='0x0000003b' ebx='0x0000011d' ecx='0x00000303' edx='0x00000000'/>
+ <cpuid eax_in='0x8000001f' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+</cpudata>
--
1.8.3.1
1
0
Add Hygon Dhyana CPU model to the processor model.
Signed-off-by: Yingle Hou <houyingle(a)hygon.cn>
---
src/cpu_map/Makefile.inc.am | 1 +
src/cpu_map/index.xml | 3 ++
src/cpu_map/x86_Dhyana.xml | 70 +++++++++++++++++++++++++++++++++++++++++++++
src/cpu_map/x86_vendors.xml | 1 +
4 files changed, 75 insertions(+)
create mode 100644 src/cpu_map/x86_Dhyana.xml
diff --git a/src/cpu_map/Makefile.inc.am b/src/cpu_map/Makefile.inc.am
index 7eb86c8..e935178 100644
--- a/src/cpu_map/Makefile.inc.am
+++ b/src/cpu_map/Makefile.inc.am
@@ -25,6 +25,7 @@ cpumap_DATA = \
cpu_map/x86_coreduo.xml \
cpu_map/x86_cpu64-rhel5.xml \
cpu_map/x86_cpu64-rhel6.xml \
+ cpu_map/x86_Dhyana.xml \
cpu_map/x86_EPYC.xml \
cpu_map/x86_EPYC-IBPB.xml \
cpu_map/x86_Haswell.xml \
diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml
index ed45083..ffb2f6f 100644
--- a/src/cpu_map/index.xml
+++ b/src/cpu_map/index.xml
@@ -60,6 +60,9 @@
<include filename="x86_Opteron_G5.xml"/>
<include filename="x86_EPYC.xml"/>
<include filename="x86_EPYC-IBPB.xml"/>
+
+ <!-- Hygon CPU models -->
+ <include filename="x86_Dhyana.xml"/>
</arch>
<arch name='ppc64'>
diff --git a/src/cpu_map/x86_Dhyana.xml b/src/cpu_map/x86_Dhyana.xml
new file mode 100644
index 0000000..cbc8020
--- /dev/null
+++ b/src/cpu_map/x86_Dhyana.xml
@@ -0,0 +1,70 @@
+<cpus>
+ <model name='Dhyana'>
+ <signature family='24' model='0'/> <!-- 900f00 -->
+ <vendor name='Hygon'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='clflushopt'/>
+ <feature name='cmov'/>
+ <feature name='cr8legacy'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='fxsr_opt'/>
+ <feature name='ibpb'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='misalignsse'/>
+ <feature name='mmx'/>
+ <feature name='mmxext'/>
+ <feature name='monitor'/>
+ <feature name='movbe'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='osvw'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pdpe1gb'/>
+ <feature name='pge'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='sse4a'/>
+ <feature name='ssse3'/>
+ <feature name='svm'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='vme'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/src/cpu_map/x86_vendors.xml b/src/cpu_map/x86_vendors.xml
index 418712a..840179d 100644
--- a/src/cpu_map/x86_vendors.xml
+++ b/src/cpu_map/x86_vendors.xml
@@ -1,4 +1,5 @@
<cpus>
<vendor name='Intel' string='GenuineIntel'/>
<vendor name='AMD' string='AuthenticAMD'/>
+ <vendor name='Hygon' string='HygonGenuine'/>
</cpus>
--
1.8.3.1
1
0
[libvirt] [PATCH 1/4] cpu: Remove the verification conditions of the model in the x86 signatures
by Yingle Hou 21 Nov '19
by Yingle Hou 21 Nov '19
21 Nov '19
The x86ModelParseSignatures function makes an assumption that CPU signature
model equals 0 as an invalid case. While in Hygon processor definition, A1
version (model 0, stepping 1) is mass production version, to support Hygon
Dhyana A1 version, we have removed CPU signature model zero checking condition.
Signed-off-by: Yingle Hou <houyingle(a)hygon.cn>
---
src/cpu/cpu_x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index c83cab0..dcd8429 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1419,7 +1419,7 @@ x86ModelParseSignatures(virCPUx86ModelPtr model,
}
rc = virXPathUInt("string(@model)", ctxt, &sigModel);
- if (rc < 0 || sigModel == 0) {
+ if (rc < 0) {
virReportError(VIR_ERR_INTERNAL_ERROR,
_("Invalid CPU signature model in model %s"),
model->name);
--
1.8.3.1
1
0
As a Joint Venture between AMD and Haiguang Information Technology Co., Ltd.,
Hygon aims to provide x86 server processor in China market. The first
generation processor Dhyana (family 18h) shares similar architecture with
AMD family 17h.
As Dhyana support in QEMU already have been merged in qemu-4.1.0 [1], to add
Dhyana support in libvirt, we have added a new Dhyana CPU model file
x86_Dhyana.xml in cpu_map directory, and also we have added a series of
Dhyana test files.
We have tested the patches on Hygon Dhyana machine with the result that it
has successfully worked as expected.
Reference:
[1] https://patchwork.kernel.org/patch/10902889/
Yingle Hou (4):
cpu: Remove the verification conditions of the model in the x86
signatures
cpu: Add new Dhyana CPU model
cputest: Add CPUID data for Hygon Dhyana 7185 32-core Processor
domaincapstest: Add CPU model Dhyana to QEMU
src/cpu/cpu_x86.c | 2 +-
src/cpu_map/Makefile.inc.am | 1 +
src/cpu_map/index.xml | 3 +
src/cpu_map/x86_Dhyana.xml | 70 +
src/cpu_map/x86_vendors.xml | 1 +
tests/cputest.c | 1 +
...86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml | 7 +
...x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml | 9 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml | 16 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-host.xml | 17 +
.../x86_64-cpuid-Hygon-C86-7185-32-core-json.xml | 12 +
.../x86_64-cpuid-Hygon-C86-7185-32-core.json | 1631 ++++++++++++++++++++
.../x86_64-cpuid-Hygon-C86-7185-32-core.sig | 4 +
.../x86_64-cpuid-Hygon-C86-7185-32-core.xml | 54 +
tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 +
20 files changed, 1833 insertions(+), 1 deletion(-)
create mode 100644 src/cpu_map/x86_Dhyana.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Hygon-C86-7185-32-core.xml
--
1.8.3.1
1
0
[libvirt] [PATCH v2 0/4] Fix remote dispatch code trying to allocate 0-sized return buffers
by Erik Skultety 21 Nov '19
by Erik Skultety 21 Nov '19
21 Nov '19
This happens because of the switch to glib whose method g_malloc0 actually
correctly returns NULL on size 0 which doesn't make sense to do. The outcome of
that is that because virAllocN always returns 0, the dispatch code never fails
allocation and passes the NULL pointer to the server-side public API which
actually checks that and fails.
https://bugzilla.redhat.com/show_bug.cgi?id=1772842
Since v1:
- reworked the original patch 3/3 (now 4/4) by introducing a
virCheckNonNull-style macro which checks whether the caller-provided array
isn't by any chance NULL while the declared size of this array is a
positive int (Dan's suggestion)
-> apart from the single scenario check (NULL && n > 0), the other
combinations are allowed for the legacy APIs letting the server-side
handle this
- added patch 3/4 when I realized one of the legacy APIs which didn't have
the dispatch code autogenerated needed adjustment too
- I deliberately didn't touch the APIs using typed params, as half of them
are setters and the other half is supposed to be called twice, so we
already have various NULL checks in place
- there were a few legacy APIs that already had some protection in the
remote dispatch code, so I didn't touch the client side for those, IMO we
can always treat those on case-by-case basis if a similar issue arises
than risk breaking one third of libvirt now :P
Erik Skultety (4):
rpc: gendispatch: Fix a couple of places adding trailing spaces
rpc: gendispatch: Add a check for zero size client-side buffers
remote: Add a check for zero sized client-side buffers
libvirt-<module>: Check caller-provided buffers to be NULL with size >
0
src/internal.h | 13 +++++++++++++
src/libvirt-domain-snapshot.c | 4 ++--
src/libvirt-domain.c | 21 ++++++---------------
src/libvirt-host.c | 2 +-
src/libvirt-interface.c | 4 ++--
src/libvirt-network.c | 4 ++--
src/libvirt-nodedev.c | 4 ++--
src/libvirt-nwfilter.c | 2 +-
src/libvirt-secret.c | 2 +-
src/libvirt-storage.c | 6 +++---
src/remote/remote_daemon_dispatch.c | 6 ++++++
src/rpc/gendispatch.pl | 12 ++++++++++--
12 files changed, 49 insertions(+), 31 deletions(-)
--
2.23.0
2
8
[libvirt] [PATCH 0/8] domaincaps: Simplify adding of new domain capability features
by Peter Krempa 21 Nov '19
by Peter Krempa 21 Nov '19
21 Nov '19
As you might guess I plan to add a new one later on.
Peter Krempa (8):
conf: domaincaps: Replace FORMAT_SINGLE macro by a function
conf: domaincaps: Extract formatting of the <features> subelement
conf: domaincaps: Use virXMLFormatElement in
virDomainCapsFormatFeatures
conf: domaincaps: Add 'iothreads' to the features section
domcaps: Add function for initializing domain caps as unsupported
qemu: domcaps: Initialize all features
domaincaps: Store domain capability features in an array
qemu: domcaps: Simplify adding new domaincaps based on qemu caps
docs/schemas/domaincaps.rng | 3 +
src/bhyve/bhyve_capabilities.c | 4 +-
src/conf/domain_capabilities.c | 80 ++++++++++++++-----
src/conf/domain_capabilities.h | 15 +++-
src/libvirt_private.syms | 1 +
src/libxl/libxl_capabilities.c | 5 +-
src/qemu/qemu_capabilities.c | 41 +++++++---
tests/domaincapsdata/libxl-xenfv.xml | 1 +
tests/domaincapsdata/libxl-xenpv.xml | 1 +
.../domaincapsdata/qemu_1.5.3-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_1.5.3-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_1.5.3.x86_64.xml | 1 +
.../domaincapsdata/qemu_1.6.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_1.6.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_1.6.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_1.7.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_1.7.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_1.7.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.1.1-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.1.1-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.1.1.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.10.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.10.0-tcg.x86_64.xml | 1 +
.../qemu_2.10.0-virt.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.10.0.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.10.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_2.10.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.10.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.11.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.11.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.11.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.11.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.12.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.12.0-tcg.x86_64.xml | 1 +
.../qemu_2.12.0-virt.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.12.0.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.12.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_2.12.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.12.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.4.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.4.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.4.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.5.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.5.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.5.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.6.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.6.0-tcg.x86_64.xml | 1 +
.../qemu_2.6.0-virt.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.6.0.aarch64.xml | 1 +
tests/domaincapsdata/qemu_2.6.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_2.6.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.7.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.7.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.7.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.7.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.8.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.8.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.8.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.8.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.9.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_2.9.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_2.9.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_2.9.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_2.9.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_3.0.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_3.0.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_3.0.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_3.0.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_3.0.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_3.1.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_3.1.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_3.1.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_3.1.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.0.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.0.0-tcg.x86_64.xml | 1 +
.../qemu_4.0.0-virt.aarch64.xml | 1 +
tests/domaincapsdata/qemu_4.0.0.aarch64.xml | 1 +
tests/domaincapsdata/qemu_4.0.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_4.0.0.s390x.xml | 1 +
tests/domaincapsdata/qemu_4.0.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 +
tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 +
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 +
.../qemu_4.2.0-virt.aarch64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0.aarch64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0.ppc64.xml | 1 +
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 +
89 files changed, 192 insertions(+), 39 deletions(-)
--
2.23.0
4
23
[libvirt] [PATCH v2 0/4] qemu: block: implement optional removal of committed snapshot images
by Pavel Mores 20 Nov '19
by Pavel Mores 20 Nov '19
20 Nov '19
v2 fixes a mess-up in handling of strerror_r() return value.
Pavel Mores (4):
qemu: block: propagate the delete flag to where it can actually be
used
qemu: block: use the delete flag to delete snapshot images if
requested
qemu: block: store the delete flag in libvirtd's status XML
qemu: block: add unit test of storing the delete flag in status XML
src/qemu/qemu_blockjob.c | 35 ++++++++++++++++++-
src/qemu/qemu_blockjob.h | 4 ++-
src/qemu/qemu_domain.c | 4 +++
src/qemu/qemu_driver.c | 5 +--
.../blockjob-blockdev-in.xml | 1 +
5 files changed, 45 insertions(+), 4 deletions(-)
--
2.21.0
2
14
20 Nov '19
When starting a domain without a CPU model specified in the domain XML,
QEMU will choose a default one. Which is fine unless the domain gets
migrated to another host because libvirt doesn't perform any CPU ABI
checks and the virtual CPU provided by QEMU on the destination host can
differ from the one on the source host.
With QEMU 4.2.0 we can probe for the default CPU model used by QEMU for
a particular machine type and store it in the domain XML. This way the
chosen CPU model is more visible to users and libvirt will make sure
the guest will see the exact same CPU after migration.
https://bugzilla.redhat.com/show_bug.cgi?id=1598151
https://bugzilla.redhat.com/show_bug.cgi?id=1598162
Version 2:
- more tests
- TCG-only support for non x86_64 architectures
Version 3:
- as a result of talking with QEMU developers dealing with s390 and
ppc64 I have to enhance the series so that libvirt is able to fetch
different default CPU models on TCG vs. KVM
---
Some patches were too large so I decided to shorten them before sending
to the list. You can check the full version of this series with
git fetch https://gitlab.com/jirkade/libvirt cpu-default-type
Jiri Denemark (52):
tests: Add capabilities for QEMU 4.2.0 on s390x
tests: Update 4.2.0 capabilities data on ppc64
conf: Use VIR_AUTO* in virDomainCapsCPUModelsAdd
conf: Drop nameLen parameter from virDomainCapsCPUModelsAdd
qemu: Copy CPU models in virQEMUCapsGetCPUDefinitions
qemu: Filter models in virQEMUCapsGetCPUDefinitions
qemu: Use virQEMUCapsGetCPUDefinitions more
qemu: Use g_autoptr in qemuMonitorJSONGetCPUDefinitions
qemu: Change return type of virQEMUCapsFetchCPUDefinitions
qemu: Introduce qemuMonitorCPUDefs struct
qemu: Flatten qemuMonitorCPUDefs.cpus
qemu: Add qemuMonitorCPUDefsCopy
qemu: Use g_autofree in virQEMUCapsLoadCPUModels
qemu: Use virDomainCapsCPUUsable in qemuMonitorCPUDefInfo
qemu: Introduce virQEMUCapsCPUDefsToModels
qemu: Rename virQEMUCaps{Get,Fetch}CPUDefinitions
qemu: Split virQEMUCapsFetchCPUModels
qemu: Switch qemuCaps to use qemuMonitorCPUDefs
conf: Drop unused virDomainCapsCPUModelsFilter
conf: Drop virDomainCapsCPUModelsAddSteal
qemu: Store typename from query-cpu-definitions in qemuCaps
qemu: Drop unused virQEMUCapsGetDefaultMachine
qemu: Add virQEMUCaps{Load,Format}Accel
qemu: Introduce virQEMUCapsAccel structure
qemu: Introduce virQEMUCapsAccelCopy
qemu: Introduce virQEMUCapsAccelClear
qemu: Introduce and use virQEMUCapsGetAccel
qemu: Drop virQEMUCapsGetHostCPUData
qemu: Refactor virQEMUCapsLoadAccel
qemu: Refactor virQEMUCapsFormatAccel
qemu: Introduce virQEMUCapsProbeCPUDefinitionsTest
qemu: Refactor probing of accelerator dependent data
qemu: Make virQEMUCapsGetMachineTypesCaps static
qemu: Make virQEMUCapsIsMachineSupported static
qemu: Refactor virQEMUCapsLoadCache a bit
qemu: Refactor virQEMUCapsFormatCache a bit
qemu: Pass virDomainVirtType to APIs dealing with machine types
qemu: Move machine type data in capabilities cache
qemu: Use typedef for virQEMUCapsMachineType
qemu: Introduce virQEMUCapsCopyMachineTypes
qemu: Make probed machine types depend on accelerator
qemu: Probe machine types for both KVM and TCG
qemu: Probe for default CPU types
qemu: Introduce virQEMUCapsGetMachineDefaultCPU
qemu: Use g_autoptr in qemuDomainDefPostParse
conf: Define g_autoptr cleanup function for virCPUDef
qemuxml2argvtest: Update host arch for DO_TEST*ARCH* tests
qemuxml2*test: Add test cases for default CPU models on aarch64
qemuxml2*test: Add test cases for default CPU models on ppc64
qemuxml2*test: Add test cases for default CPU models on s390x
qemuxml2*test: Add test cases for default CPU models on x86_64
qemu: Store default CPU in domain XML
src/conf/cpu_conf.h | 1 +
src/conf/domain_capabilities.c | 86 +-
src/conf/domain_capabilities.h | 10 +-
src/libvirt_private.syms | 2 -
src/qemu/qemu_capabilities.c | 1064 +-
src/qemu/qemu_capabilities.h | 29 +-
src/qemu/qemu_capspriv.h | 5 +-
src/qemu/qemu_domain.c | 97 +-
src/qemu/qemu_driver.c | 4 +-
src/qemu/qemu_monitor.c | 61 +-
src/qemu/qemu_monitor.h | 19 +-
src/qemu/qemu_monitor_json.c | 82 +-
src/qemu/qemu_monitor_json.h | 2 +-
src/qemu/qemu_process.c | 24 +-
tests/cputest.c | 12 +-
tests/domaincapsdata/qemu_4.2.0.s390x.xml | 202 +
tests/domaincapstest.c | 10 +-
.../caps_1.5.3.x86_64.replies | 78 +
.../caps_1.5.3.x86_64.xml | 45 +-
.../caps_1.6.0.x86_64.replies | 86 +
.../caps_1.6.0.x86_64.xml | 51 +-
.../caps_1.7.0.x86_64.replies | 94 +
.../caps_1.7.0.x86_64.xml | 57 +-
.../caps_2.1.1.x86_64.replies | 110 +
.../caps_2.1.1.x86_64.xml | 69 +-
.../caps_2.10.0.aarch64.replies | 272 +
.../caps_2.10.0.aarch64.xml | 279 +-
.../caps_2.10.0.ppc64.replies | 123 +
.../caps_2.10.0.ppc64.xml | 575 +-
.../caps_2.10.0.s390x.replies | 53 +
.../caps_2.10.0.s390x.xml | 285 +-
.../caps_2.10.0.x86_64.replies | 194 +
.../caps_2.10.0.x86_64.xml | 387 +-
.../caps_2.11.0.s390x.replies | 58 +
.../caps_2.11.0.s390x.xml | 288 +-
.../caps_2.11.0.x86_64.replies | 194 +
.../caps_2.11.0.x86_64.xml | 327 +-
.../caps_2.12.0.aarch64.replies | 302 +
.../caps_2.12.0.aarch64.xml | 307 +-
.../caps_2.12.0.ppc64.replies | 143 +
.../caps_2.12.0.ppc64.xml | 591 +-
.../caps_2.12.0.s390x.replies | 63 +
.../caps_2.12.0.s390x.xml | 291 +-
.../caps_2.12.0.x86_64.replies | 204 +
.../caps_2.12.0.x86_64.xml | 631 +-
.../caps_2.4.0.x86_64.replies | 134 +
.../caps_2.4.0.x86_64.xml | 87 +-
.../caps_2.5.0.x86_64.replies | 142 +
.../caps_2.5.0.x86_64.xml | 93 +-
.../caps_2.6.0.aarch64.replies | 180 +
.../caps_2.6.0.aarch64.xml | 123 +-
.../caps_2.6.0.ppc64.replies | 77 +
.../qemucapabilitiesdata/caps_2.6.0.ppc64.xml | 45 +-
.../caps_2.6.0.x86_64.replies | 118 +
.../caps_2.6.0.x86_64.xml | 75 +-
.../caps_2.7.0.s390x.replies | 38 +
.../qemucapabilitiesdata/caps_2.7.0.s390x.xml | 12 +-
.../caps_2.7.0.x86_64.replies | 154 +
.../caps_2.7.0.x86_64.xml | 81 +-
.../caps_2.8.0.s390x.replies | 43 +
.../qemucapabilitiesdata/caps_2.8.0.s390x.xml | 15 +-
.../caps_2.8.0.x86_64.replies | 174 +
.../caps_2.8.0.x86_64.xml | 93 +-
.../caps_2.9.0.ppc64.replies | 118 +
.../qemucapabilitiesdata/caps_2.9.0.ppc64.xml | 572 +-
.../caps_2.9.0.s390x.replies | 48 +
.../qemucapabilitiesdata/caps_2.9.0.s390x.xml | 274 +-
.../caps_2.9.0.x86_64.replies | 184 +
.../caps_2.9.0.x86_64.xml | 277 +-
.../caps_3.0.0.ppc64.replies | 148 +
.../qemucapabilitiesdata/caps_3.0.0.ppc64.xml | 594 +-
.../caps_3.0.0.riscv32.replies | 42 +
.../caps_3.0.0.riscv32.xml | 10 +-
.../caps_3.0.0.riscv64.replies | 42 +
.../caps_3.0.0.riscv64.xml | 10 +-
.../caps_3.0.0.s390x.replies | 68 +
.../qemucapabilitiesdata/caps_3.0.0.s390x.xml | 302 +-
.../caps_3.0.0.x86_64.replies | 214 +
.../caps_3.0.0.x86_64.xml | 447 +-
.../caps_3.1.0.ppc64.replies | 153 +
.../qemucapabilitiesdata/caps_3.1.0.ppc64.xml | 597 +-
.../caps_3.1.0.x86_64.replies | 224 +
.../caps_3.1.0.x86_64.xml | 587 +-
.../caps_4.0.0.aarch64.replies | 347 +
.../caps_4.0.0.aarch64.xml | 346 +-
.../caps_4.0.0.ppc64.replies | 158 +
.../qemucapabilitiesdata/caps_4.0.0.ppc64.xml | 600 +-
.../caps_4.0.0.riscv32.replies | 42 +
.../caps_4.0.0.riscv32.xml | 10 +-
.../caps_4.0.0.riscv64.replies | 42 +
.../caps_4.0.0.riscv64.xml | 10 +-
.../caps_4.0.0.s390x.replies | 78 +
.../qemucapabilitiesdata/caps_4.0.0.s390x.xml | 324 +-
.../caps_4.0.0.x86_64.replies | 224 +
.../caps_4.0.0.x86_64.xml | 583 +-
.../caps_4.1.0.x86_64.replies | 329 +
.../caps_4.1.0.x86_64.xml | 930 +-
.../caps_4.2.0.aarch64.replies | 556 +
.../caps_4.2.0.aarch64.xml | 358 +-
.../caps_4.2.0.ppc64.replies | 305 +-
.../qemucapabilitiesdata/caps_4.2.0.ppc64.xml | 611 +-
.../caps_4.2.0.s390x.replies | 22548 ++++++++++++++++
.../qemucapabilitiesdata/caps_4.2.0.s390x.xml | 3359 +++
.../caps_4.2.0.x86_64.replies | 389 +
.../caps_4.2.0.x86_64.xml | 942 +-
tests/qemumonitorjsontest.c | 42 +-
...fault-cpu-kvm-virt-4.2.aarch64-latest.args | 38 +
.../aarch64-default-cpu-kvm-virt-4.2.xml | 20 +
...fault-cpu-tcg-virt-4.2.aarch64-latest.args | 39 +
.../aarch64-default-cpu-tcg-virt-4.2.xml | 20 +
.../disk-cache.x86_64-latest.args | 1 +
.../disk-cdrom-network.x86_64-latest.args | 1 +
.../disk-cdrom-tray.x86_64-latest.args | 1 +
.../disk-copy_on_read.x86_64-latest.args | 1 +
.../disk-detect-zeroes.x86_64-latest.args | 1 +
.../disk-floppy-q35-2_11.x86_64-latest.args | 1 +
.../disk-floppy-q35-2_9.x86_64-latest.args | 1 +
.../os-firmware-bios.x86_64-latest.args | 1 +
...os-firmware-efi-secboot.x86_64-latest.args | 1 +
.../os-firmware-efi.x86_64-latest.args | 1 +
...ault-cpu-kvm-pseries-2.7.ppc64-latest.args | 39 +
.../ppc64-default-cpu-kvm-pseries-2.7.xml | 22 +
...ault-cpu-kvm-pseries-3.1.ppc64-latest.args | 39 +
.../ppc64-default-cpu-kvm-pseries-3.1.xml | 22 +
...ault-cpu-kvm-pseries-4.2.ppc64-latest.args | 39 +
.../ppc64-default-cpu-kvm-pseries-4.2.xml | 22 +
...ault-cpu-tcg-pseries-2.7.ppc64-latest.args | 39 +
.../ppc64-default-cpu-tcg-pseries-2.7.xml | 22 +
...ault-cpu-tcg-pseries-3.1.ppc64-latest.args | 39 +
.../ppc64-default-cpu-tcg-pseries-3.1.xml | 22 +
...ault-cpu-tcg-pseries-4.2.ppc64-latest.args | 39 +
.../ppc64-default-cpu-tcg-pseries-4.2.xml | 22 +
...t-cpu-kvm-ccw-virtio-4.2.s390x-latest.args | 32 +
.../s390-default-cpu-kvm-ccw-virtio-4.2.xml | 16 +
...t-cpu-tcg-ccw-virtio-4.2.s390x-latest.args | 32 +
.../s390-default-cpu-tcg-ccw-virtio-4.2.xml | 16 +
.../tpm-emulator-tpm2-enc.x86_64-latest.args | 1 +
.../tpm-emulator-tpm2.x86_64-latest.args | 1 +
.../tpm-emulator.x86_64-latest.args | 1 +
.../tseg-explicit-size.x86_64-latest.args | 1 +
.../vhost-vsock-auto.x86_64-latest.args | 1 +
.../vhost-vsock.x86_64-latest.args | 1 +
...-default-cpu-kvm-pc-4.2.x86_64-latest.args | 37 +
.../x86_64-default-cpu-kvm-pc-4.2.xml | 24 +
...default-cpu-kvm-q35-4.2.x86_64-latest.args | 42 +
.../x86_64-default-cpu-kvm-q35-4.2.xml | 24 +
...-default-cpu-tcg-pc-4.2.x86_64-latest.args | 37 +
.../x86_64-default-cpu-tcg-pc-4.2.xml | 24 +
...default-cpu-tcg-q35-4.2.x86_64-latest.args | 42 +
.../x86_64-default-cpu-tcg-q35-4.2.xml | 24 +
tests/qemuxml2argvtest.c | 19 +
...efault-cpu-kvm-virt-4.2.aarch64-latest.xml | 38 +
...efault-cpu-tcg-virt-4.2.aarch64-latest.xml | 41 +
.../os-firmware-bios.x86_64-latest.xml | 3 +
.../os-firmware-efi-secboot.x86_64-latest.xml | 3 +
.../os-firmware-efi.x86_64-latest.xml | 3 +
...fault-cpu-kvm-pseries-2.7.ppc64-latest.xml | 48 +
...fault-cpu-kvm-pseries-3.1.ppc64-latest.xml | 48 +
...fault-cpu-kvm-pseries-4.2.ppc64-latest.xml | 48 +
...fault-cpu-tcg-pseries-2.7.ppc64-latest.xml | 48 +
...fault-cpu-tcg-pseries-3.1.ppc64-latest.xml | 48 +
...fault-cpu-tcg-pseries-4.2.ppc64-latest.xml | 48 +
...lt-cpu-kvm-ccw-virtio-4.2.s390x-latest.xml | 24 +
...lt-cpu-tcg-ccw-virtio-4.2.s390x-latest.xml | 26 +
.../tpm-emulator-tpm2-enc.x86_64-latest.xml | 3 +
.../tpm-emulator-tpm2.x86_64-latest.xml | 3 +
.../tpm-emulator.x86_64-latest.xml | 3 +
.../tpm-passthrough-crb.x86_64-latest.xml | 3 +
.../tpm-passthrough.x86_64-latest.xml | 3 +
...4-default-cpu-kvm-pc-4.2.x86_64-latest.xml | 40 +
...-default-cpu-kvm-q35-4.2.x86_64-latest.xml | 63 +
...4-default-cpu-tcg-pc-4.2.x86_64-latest.xml | 40 +
...-default-cpu-tcg-q35-4.2.x86_64-latest.xml | 63 +
tests/qemuxml2xmltest.c | 15 +
tests/testutilsqemu.c | 6 +-
tests/testutilsqemu.h | 1 +
176 files changed, 42397 insertions(+), 6735 deletions(-)
create mode 100644 tests/domaincapsdata/qemu_4.2.0.s390x.xml
create mode 100644 tests/qemucapabilitiesdata/caps_4.2.0.s390x.replies
create mode 100644 tests/qemucapabilitiesdata/caps_4.2.0.s390x.xml
create mode 100644 tests/qemuxml2argvdata/aarch64-default-cpu-kvm-virt-4.2.aarch64-latest.args
create mode 100644 tests/qemuxml2argvdata/aarch64-default-cpu-kvm-virt-4.2.xml
create mode 100644 tests/qemuxml2argvdata/aarch64-default-cpu-tcg-virt-4.2.aarch64-latest.args
create mode 100644 tests/qemuxml2argvdata/aarch64-default-cpu-tcg-virt-4.2.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-2.7.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-2.7.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-3.1.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-3.1.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-4.2.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-kvm-pseries-4.2.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-2.7.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-2.7.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-3.1.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-3.1.xml
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-4.2.ppc64-latest.args
create mode 100644 tests/qemuxml2argvdata/ppc64-default-cpu-tcg-pseries-4.2.xml
create mode 100644 tests/qemuxml2argvdata/s390-default-cpu-kvm-ccw-virtio-4.2.s390x-latest.args
create mode 100644 tests/qemuxml2argvdata/s390-default-cpu-kvm-ccw-virtio-4.2.xml
create mode 100644 tests/qemuxml2argvdata/s390-default-cpu-tcg-ccw-virtio-4.2.s390x-latest.args
create mode 100644 tests/qemuxml2argvdata/s390-default-cpu-tcg-ccw-virtio-4.2.xml
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-kvm-pc-4.2.x86_64-latest.args
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-kvm-pc-4.2.xml
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-kvm-q35-4.2.x86_64-latest.args
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-kvm-q35-4.2.xml
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-tcg-pc-4.2.x86_64-latest.args
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-tcg-pc-4.2.xml
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-tcg-q35-4.2.x86_64-latest.args
create mode 100644 tests/qemuxml2argvdata/x86_64-default-cpu-tcg-q35-4.2.xml
create mode 100644 tests/qemuxml2xmloutdata/aarch64-default-cpu-kvm-virt-4.2.aarch64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/aarch64-default-cpu-tcg-virt-4.2.aarch64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-kvm-pseries-2.7.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-kvm-pseries-3.1.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-kvm-pseries-4.2.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-tcg-pseries-2.7.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-tcg-pseries-3.1.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/ppc64-default-cpu-tcg-pseries-4.2.ppc64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/s390-default-cpu-kvm-ccw-virtio-4.2.s390x-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/s390-default-cpu-tcg-ccw-virtio-4.2.s390x-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/x86_64-default-cpu-kvm-pc-4.2.x86_64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/x86_64-default-cpu-kvm-q35-4.2.x86_64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/x86_64-default-cpu-tcg-pc-4.2.x86_64-latest.xml
create mode 100644 tests/qemuxml2xmloutdata/x86_64-default-cpu-tcg-q35-4.2.x86_64-latest.xml
--
2.23.0
3
82
[libvirt] [PATCH 0/4] apparmor fixes triggered by multi disk snapshots
by Christian Ehrhardt 20 Nov '19
by Christian Ehrhardt 20 Nov '19
20 Nov '19
Hi,
the bugs [1][2] that made me debug into this actually only need the
last patch (one line), but while coming along I found several
opportunities for minor improvements of the apparmor code in libvirt.
But that way it became a 4 patch series around apparmor.
[1]: https://bugzilla.redhat.com/show_bug.cgi?id=1746684
[2]: https://bugs.launchpad.net/libvirt/+bug/1845506
Christian Ehrhardt (4):
virt-aa-helper: clarify command line options
apparmor: drop useless call to get_profile_name
apparmor: refactor AppArmorSetSecurityImageLabel
apparmor: let AppArmorSetSecurityImageLabel append rules
src/security/security_apparmor.c | 52 +++++++-------------------------
src/security/virt-aa-helper.c | 14 +++++----
2 files changed, 19 insertions(+), 47 deletions(-)
--
2.23.0
3
15
Cole was recently adding a few of the usual apparmor suspects to BZ 1761645
and I was taking a look at the low hanging fruits of it today. It isn't
perfect, but would resolve the reported issue - so I'd appreciate a
review.
Limitations:
- One could break the path creating elements in qemuBuildShmemBackendMemProps
and qemuDomainPrepareShmemChardev into extra functions and then use those
from virt-aa-helper. But I haven't done so yet and unless it is strictly
required consider it too much for what we want/need to achieve here.
- I haven't covered hotplug of shmem devices yet, it seems there is no
infrastructure for their labels yet and I wasn't sure how important
shmem-hotplug would even be to anyone.
Christian Ehrhardt (2):
virt-aa-helper: add rules for shmem devices
virt-aa-helper: testcase for shmem devices
src/security/virt-aa-helper.c | 35 +++++++++++++++++++++++++++++++++++
tests/virt-aa-helper-test | 15 +++++++++++++++
2 files changed, 50 insertions(+)
--
2.23.0
3
18