[PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com&gt; Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org&gt; Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org&gt; Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com&gt; Message-Id: <20201208003702.4088927-10-f4bug(a)amsat.org&gt; --- target/mips/translate.c | 71 ++++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 22 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 18cebe26bde..0e7b2abe8bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28615,49 +28615,76 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) tcg_temp_free_i64(t1); } +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + t0 = tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |= MIPS_HFLAG_BC; + ctx->hflags |= MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |= MIPS_HFLAG_BC; + ctx->hflags |= MIPS_HFLAG_BDS32; + + return true; +} + static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df = (ctx->opcode >> 21) & 0x3; uint8_t wt = (ctx->opcode >> 16) & 0x1f; int64_t s16 = (int16_t)ctx->opcode; - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return; - } switch (op1) { case OPC_BZ_V: case OPC_BNZ_V: - { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - } + gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); break; case OPC_BZ_B: case OPC_BZ_H: case OPC_BZ_W: case OPC_BZ_D: - gen_check_zero_element(bcond, df, wt); + gen_msa_BxZ(ctx, df, wt, s16, false); break; case OPC_BNZ_B: case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - gen_check_zero_element(bcond, df, wt); - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + gen_msa_BxZ(ctx, df, wt, s16, true); break; } - - ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |= MIPS_HFLAG_BC; - ctx->hflags |= MIPS_HFLAG_BDS32; } static void gen_msa_i8(DisasContext *ctx) -- 2.26.2