[PULL 6/6] target/mips: Add unaligned access support for MIPS64R6 and Loongson-3

From: Huacai Chen <zltjiangshi(a)gmail.com&gt; MIPSR6 (not only MIPS32R6) processors support unaligned access in hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new Loongson-3 (such as Loongson-3A4000) also support unaligned access, since both old and new Loongson-3 use the same binaries, we can simply set MO_UNALN for all Loongson-3 processors. Signed-off-by: Huacai Chen <chenhc(a)lemote.com&gt; Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org&gt; Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org&gt; Message-Id: <1604053541-27822-3-git-send-email-chenhc(a)lemote.com&gt; Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org&gt; --- target/mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3197a692c45..c64a1bc42e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31442,8 +31442,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ? - MO_UNALN : MO_ALIGN; + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | + INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, ctx->hflags); -- 2.26.2