[PATCH RFC v3 11/14] target/riscv: Support riscv cpu vmstate

Describe gpr, fpr and csr in vmstate_riscv_cpu. Signed-off-by: Yifei Jiang <jiangyifei(a)huawei.com&gt; Signed-off-by: Yipeng Yin <yinyipeng1(a)huawei.com&gt; --- target/riscv/cpu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8c32a8f84..b698f4adbb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" -#include "migration/vmstate.h" +#include "migration/cpu.h" #include "fpu/softfloat-helpers.h" #include "kvm_riscv.h" @@ -499,7 +499,23 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .unmigratable = 1, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), + VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), + VMSTATE_UINTTL(env.pc, RISCVCPU), + VMSTATE_UINTTL(env.mstatus, RISCVCPU), + VMSTATE_UINTTL(env.mie, RISCVCPU), + VMSTATE_UINTTL(env.stvec, RISCVCPU), + VMSTATE_UINTTL(env.sscratch, RISCVCPU), + VMSTATE_UINTTL(env.sepc, RISCVCPU), + VMSTATE_UINTTL(env.scause, RISCVCPU), + VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.mip, RISCVCPU), + VMSTATE_UINTTL(env.satp, RISCVCPU), + VMSTATE_END_OF_LIST() + } }; #endif -- 2.19.1