[PATCH 6/8] qemuxml2xmltest: Convert all test cases asserting QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY

Turn them into DO_TEST_CAPS_LATEST tests so that we are closer to real world. Signed-off-by: Peter Krempa <pkrempa(a)redhat.com&gt; --- ...h64-virtio-pci-default.aarch64-latest.xml} | 12 +- ...ev-scsi-vhost-scsi-pcie.x86_64-latest.xml} | 3 + ...35-default-devices-only.x86_64-latest.xml} | 11 +- ...ml => q35-multifunction.x86_64-latest.xml} | 41 +++--- ...xml => q35-pcie-autoadd.x86_64-latest.xml} | 31 ++--- ...35-pcie.xml => q35-pcie.x86_64-latest.xml} | 29 +++-- ... q35-virt-manager-basic.x86_64-latest.xml} | 15 ++- tests/qemuxml2xmltest.c | 119 ++---------------- 8 files changed, 87 insertions(+), 174 deletions(-) rename tests/qemuxml2xmloutdata/{aarch64-virtio-pci-default.xml => aarch64-virtio-pci-default.aarch64-latest.xml} (93%) rename tests/qemuxml2xmloutdata/{hostdev-scsi-vhost-scsi-pcie.xml => hostdev-scsi-vhost-scsi-pcie.x86_64-latest.xml} (94%) rename tests/qemuxml2xmloutdata/{q35-default-devices-only.xml => q35-default-devices-only.x86_64-latest.xml} (86%) rename tests/qemuxml2xmloutdata/{q35-multifunction.xml => q35-multifunction.x86_64-latest.xml} (85%) rename tests/qemuxml2xmloutdata/{q35-pcie-autoadd.xml => q35-pcie-autoadd.x86_64-latest.xml} (90%) rename tests/qemuxml2xmloutdata/{q35-pcie.xml => q35-pcie.x86_64-latest.xml} (91%) rename tests/qemuxml2xmloutdata/{q35-virt-manager-basic.xml => q35-virt-manager-basic.x86_64-latest.xml} (93%) diff --git a/tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.xml b/tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.aarch64-latest.xml similarity index 93% rename from tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.xml rename to tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.aarch64-latest.xml index e49ecc4e15..1ea25a01f5 100644 --- a/tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.xml +++ b/tests/qemuxml2xmloutdata/aarch64-virtio-pci-default.aarch64-latest.xml @@ -37,32 +37,32 @@ <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/> </controller> <controller type='pci' index='1' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='1' port='0x8'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='2' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='2' port='0x9'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x1'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0xa'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x2'/> </controller> <controller type='pci' index='4' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='4' port='0xb'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x3'/> </controller> <controller type='pci' index='5' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='5' port='0xc'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x4'/> </controller> <controller type='pci' index='6' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='6' port='0xd'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x5'/> </controller> diff --git a/tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.xml b/tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.x86_64-latest.xml similarity index 94% rename from tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.xml rename to tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.x86_64-latest.xml index dd8db2158c..032b4ce030 100644 --- a/tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.xml +++ b/tests/qemuxml2xmloutdata/hostdev-scsi-vhost-scsi-pcie.x86_64-latest.xml @@ -8,6 +8,9 @@ <type arch='x86_64' machine='q35'>hvm</type> <boot dev='hd'/> </os> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'/> <on_poweroff>destroy</on_poweroff> <on_reboot>restart</on_reboot> diff --git a/tests/qemuxml2xmloutdata/q35-default-devices-only.xml b/tests/qemuxml2xmloutdata/q35-default-devices-only.x86_64-latest.xml similarity index 86% rename from tests/qemuxml2xmloutdata/q35-default-devices-only.xml rename to tests/qemuxml2xmloutdata/q35-default-devices-only.x86_64-latest.xml index cf8646e833..5540ad1147 100644 --- a/tests/qemuxml2xmloutdata/q35-default-devices-only.xml +++ b/tests/qemuxml2xmloutdata/q35-default-devices-only.x86_64-latest.xml @@ -8,13 +8,16 @@ <type arch='x86_64' machine='q35'>hvm</type> <boot dev='hd'/> </os> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'/> <on_poweroff>destroy</on_poweroff> <on_reboot>restart</on_reboot> <on_crash>destroy</on_crash> <devices> <emulator>/usr/bin/qemu-system-x86_64</emulator> - <controller type='usb' index='0' model='nec-xhci'> + <controller type='usb' index='0' model='qemu-xhci'> <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> </controller> <controller type='sata' index='0'> @@ -22,17 +25,17 @@ </controller> <controller type='pci' index='0' model='pcie-root'/> <controller type='pci' index='1' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='1' port='0x8'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='2' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='2' port='0x9'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x1'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0xa'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x2'/> </controller> diff --git a/tests/qemuxml2xmloutdata/q35-multifunction.xml b/tests/qemuxml2xmloutdata/q35-multifunction.x86_64-latest.xml similarity index 85% rename from tests/qemuxml2xmloutdata/q35-multifunction.xml rename to tests/qemuxml2xmloutdata/q35-multifunction.x86_64-latest.xml index b98405b257..e8ea62321a 100644 --- a/tests/qemuxml2xmloutdata/q35-multifunction.xml +++ b/tests/qemuxml2xmloutdata/q35-multifunction.x86_64-latest.xml @@ -8,6 +8,9 @@ <type arch='x86_64' machine='q35'>hvm</type> <boot dev='hd'/> </os> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'/> <on_poweroff>destroy</on_poweroff> <on_reboot>restart</on_reboot> @@ -16,96 +19,96 @@ <emulator>/usr/bin/qemu-system-x86_64</emulator> <controller type='pci' index='0' model='pcie-root'/> <controller type='pci' index='1' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='1' port='0x10'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='2' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='2' port='0x11'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x1'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0x12'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x2'/> </controller> <controller type='pci' index='4' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='4' port='0x18'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='5' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='5' port='0x19'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x1' multifunction='on'/> </controller> <controller type='pci' index='6' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='6' port='0x20'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x04' function='0x0' multifunction='off'/> </controller> <controller type='pci' index='7' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='7' port='0x21'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x04' function='0x1'/> </controller> <controller type='pci' index='8' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='8' port='0x8'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='9' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='9' port='0x9'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x1'/> </controller> <controller type='pci' index='10' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='10' port='0xa'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x2'/> </controller> <controller type='pci' index='11' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='11' port='0xb'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x3'/> </controller> <controller type='pci' index='12' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='12' port='0xc'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x4'/> </controller> <controller type='pci' index='13' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='13' port='0xd'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x5'/> </controller> <controller type='pci' index='14' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='14' port='0xe'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x6'/> </controller> <controller type='pci' index='15' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='15' port='0xf'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x7'/> </controller> <controller type='pci' index='16' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='16' port='0x13'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x3'/> </controller> <controller type='pci' index='17' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='17' port='0x14'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x4'/> </controller> <controller type='pci' index='18' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='18' port='0x15'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x5'/> </controller> - <controller type='usb' index='0' model='nec-xhci'> + <controller type='usb' index='0' model='qemu-xhci'> <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> </controller> <controller type='sata' index='0'> diff --git a/tests/qemuxml2xmloutdata/q35-pcie-autoadd.xml b/tests/qemuxml2xmloutdata/q35-pcie-autoadd.x86_64-latest.xml similarity index 90% rename from tests/qemuxml2xmloutdata/q35-pcie-autoadd.xml rename to tests/qemuxml2xmloutdata/q35-pcie-autoadd.x86_64-latest.xml index f9131d3e4f..3037902354 100644 --- a/tests/qemuxml2xmloutdata/q35-pcie-autoadd.xml +++ b/tests/qemuxml2xmloutdata/q35-pcie-autoadd.x86_64-latest.xml @@ -8,6 +8,9 @@ <type arch='x86_64' machine='q35'>hvm</type> <boot dev='hd'/> </os> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'/> <on_poweroff>destroy</on_poweroff> <on_reboot>restart</on_reboot> @@ -34,72 +37,72 @@ </controller> <controller type='pci' index='0' model='pcie-root'/> <controller type='pci' index='1' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='1' port='0x10'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='2' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='2' port='0x11'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x1'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0x12'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x2'/> </controller> <controller type='pci' index='4' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='4' port='0x13'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x3'/> </controller> <controller type='pci' index='5' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='5' port='0x14'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x4'/> </controller> <controller type='pci' index='6' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='6' port='0x15'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x5'/> </controller> <controller type='pci' index='7' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='7' port='0x16'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x6'/> </controller> <controller type='pci' index='8' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='8' port='0x17'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x7'/> </controller> <controller type='pci' index='9' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='9' port='0x18'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='10' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='10' port='0x19'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x1'/> </controller> <controller type='pci' index='11' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='11' port='0x1a'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x2'/> </controller> <controller type='pci' index='12' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='12' port='0x1b'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x3'/> </controller> <controller type='pci' index='13' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='13' port='0x1c'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x4'/> </controller> <controller type='pci' index='14' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='14' port='0x1d'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x5'/> </controller> diff --git a/tests/qemuxml2xmloutdata/q35-pcie.xml b/tests/qemuxml2xmloutdata/q35-pcie.x86_64-latest.xml similarity index 91% rename from tests/qemuxml2xmloutdata/q35-pcie.xml rename to tests/qemuxml2xmloutdata/q35-pcie.x86_64-latest.xml index 76dbfd5c8c..72535446f6 100644 --- a/tests/qemuxml2xmloutdata/q35-pcie.xml +++ b/tests/qemuxml2xmloutdata/q35-pcie.x86_64-latest.xml @@ -8,6 +8,9 @@ <type arch='x86_64' machine='q35'>hvm</type> <boot dev='hd'/> </os> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'/> <on_poweroff>destroy</on_poweroff> <on_reboot>restart</on_reboot> @@ -31,67 +34,67 @@ <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0x10'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='4' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='4' port='0x11'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x1'/> </controller> <controller type='pci' index='5' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='5' port='0x12'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x2'/> </controller> <controller type='pci' index='6' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='6' port='0x13'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x3'/> </controller> <controller type='pci' index='7' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='7' port='0x14'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x4'/> </controller> <controller type='pci' index='8' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='8' port='0x15'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x5'/> </controller> <controller type='pci' index='9' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='9' port='0x16'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x6'/> </controller> <controller type='pci' index='10' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='10' port='0x17'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x7'/> </controller> <controller type='pci' index='11' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='11' port='0x18'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='12' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='12' port='0x19'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x1'/> </controller> <controller type='pci' index='13' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='13' port='0x1a'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x2'/> </controller> <controller type='pci' index='14' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='14' port='0x1b'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x3'/> </controller> <controller type='pci' index='15' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='15' port='0x1c'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x4'/> </controller> diff --git a/tests/qemuxml2xmloutdata/q35-virt-manager-basic.xml b/tests/qemuxml2xmloutdata/q35-virt-manager-basic.x86_64-latest.xml similarity index 93% rename from tests/qemuxml2xmloutdata/q35-virt-manager-basic.xml rename to tests/qemuxml2xmloutdata/q35-virt-manager-basic.x86_64-latest.xml index 44770b5fdc..62289d4800 100644 --- a/tests/qemuxml2xmloutdata/q35-virt-manager-basic.xml +++ b/tests/qemuxml2xmloutdata/q35-virt-manager-basic.x86_64-latest.xml @@ -13,6 +13,9 @@ <apic/> <vmport state='off'/> </features> + <cpu mode='custom' match='exact' check='none'> + <model fallback='forbid'>qemu64</model> + </cpu> <clock offset='utc'> <timer name='rtc' tickpolicy='catchup'/> <timer name='pit' tickpolicy='delay'/> @@ -44,32 +47,32 @@ </controller> <controller type='pci' index='0' model='pcie-root'/> <controller type='pci' index='1' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='1' port='0x10'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0' multifunction='on'/> </controller> <controller type='pci' index='2' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='2' port='0x11'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x1'/> </controller> <controller type='pci' index='3' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='3' port='0x12'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x2'/> </controller> <controller type='pci' index='4' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='4' port='0x13'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x3'/> </controller> <controller type='pci' index='5' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='5' port='0x14'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x4'/> </controller> <controller type='pci' index='6' model='pcie-root-port'> - <model name='ioh3420'/> + <model name='pcie-root-port'/> <target chassis='6' port='0x15'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x5'/> </controller> diff --git a/tests/qemuxml2xmltest.c b/tests/qemuxml2xmltest.c index 6806e5e742..0507b70825 100644 --- a/tests/qemuxml2xmltest.c +++ b/tests/qemuxml2xmltest.c @@ -804,106 +804,12 @@ mymain(void) QEMU_CAPS_ICH9_AHCI, QEMU_CAPS_ICH9_USB_EHCI1, QEMU_CAPS_DEVICE_QXL); - DO_TEST("q35-pcie", - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_RNG, - QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_DEVICE_VIRTIO_NET, - QEMU_CAPS_DEVICE_VIRTIO_GPU, - QEMU_CAPS_VIRTIO_GPU_VIRGL, - QEMU_CAPS_VIRTIO_KEYBOARD, - QEMU_CAPS_VIRTIO_MOUSE, - QEMU_CAPS_VIRTIO_TABLET, - QEMU_CAPS_VIRTIO_INPUT_HOST, - QEMU_CAPS_VIRTIO_SCSI, - QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_ICH9_AHCI, - QEMU_CAPS_ICH9_USB_EHCI1, - QEMU_CAPS_NEC_USB_XHCI); + DO_TEST_CAPS_LATEST("q35-pcie"); /* same as q35-pcie, but all PCI controllers are added automatically */ - DO_TEST("q35-pcie-autoadd", - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_RNG, - QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_DEVICE_VIRTIO_NET, - QEMU_CAPS_DEVICE_VIRTIO_GPU, - QEMU_CAPS_VIRTIO_GPU_VIRGL, - QEMU_CAPS_VIRTIO_KEYBOARD, - QEMU_CAPS_VIRTIO_MOUSE, - QEMU_CAPS_VIRTIO_TABLET, - QEMU_CAPS_VIRTIO_INPUT_HOST, - QEMU_CAPS_VIRTIO_SCSI, - QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_ICH9_AHCI, - QEMU_CAPS_ICH9_USB_EHCI1, - QEMU_CAPS_NEC_USB_XHCI); - DO_TEST("q35-default-devices-only", - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_RNG, - QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_DEVICE_VIRTIO_NET, - QEMU_CAPS_DEVICE_VIRTIO_GPU, - QEMU_CAPS_VIRTIO_GPU_VIRGL, - QEMU_CAPS_VIRTIO_KEYBOARD, - QEMU_CAPS_VIRTIO_MOUSE, - QEMU_CAPS_VIRTIO_TABLET, - QEMU_CAPS_VIRTIO_INPUT_HOST, - QEMU_CAPS_VIRTIO_SCSI, - QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_ICH9_AHCI, - QEMU_CAPS_ICH9_USB_EHCI1, - QEMU_CAPS_NEC_USB_XHCI); - DO_TEST("q35-multifunction", - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_RNG, - QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_DEVICE_VIRTIO_NET, - QEMU_CAPS_DEVICE_VIRTIO_GPU, - QEMU_CAPS_VIRTIO_GPU_VIRGL, - QEMU_CAPS_VIRTIO_KEYBOARD, - QEMU_CAPS_VIRTIO_MOUSE, - QEMU_CAPS_VIRTIO_TABLET, - QEMU_CAPS_VIRTIO_INPUT_HOST, - QEMU_CAPS_VIRTIO_SCSI, - QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_ICH9_AHCI, - QEMU_CAPS_ICH9_USB_EHCI1, - QEMU_CAPS_NEC_USB_XHCI); - DO_TEST("q35-virt-manager-basic", - QEMU_CAPS_KVM, - QEMU_CAPS_ICH9_DISABLE_S3, - QEMU_CAPS_ICH9_DISABLE_S4, - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_RNG, - QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_DEVICE_VIRTIO_NET, - QEMU_CAPS_DEVICE_VIRTIO_GPU, - QEMU_CAPS_VIRTIO_GPU_VIRGL, - QEMU_CAPS_VIRTIO_KEYBOARD, - QEMU_CAPS_VIRTIO_MOUSE, - QEMU_CAPS_VIRTIO_TABLET, - QEMU_CAPS_VIRTIO_INPUT_HOST, - QEMU_CAPS_VIRTIO_SCSI, - QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_ICH9_AHCI, - QEMU_CAPS_ICH9_USB_EHCI1, - QEMU_CAPS_NEC_USB_XHCI, - QEMU_CAPS_DEVICE_ICH9_INTEL_HDA, - QEMU_CAPS_SPICE, - QEMU_CAPS_DEVICE_QXL, - QEMU_CAPS_HDA_DUPLEX, - QEMU_CAPS_USB_REDIR, - QEMU_CAPS_MACHINE_VMPORT_OPT); + DO_TEST_CAPS_LATEST("q35-pcie-autoadd"); + DO_TEST_CAPS_LATEST("q35-default-devices-only"); + DO_TEST_CAPS_LATEST("q35-multifunction"); + DO_TEST_CAPS_LATEST("q35-virt-manager-basic"); DO_TEST("pcie-root", QEMU_CAPS_DEVICE_IOH3420, QEMU_CAPS_ICH9_AHCI, @@ -966,11 +872,7 @@ mymain(void) DO_TEST("hostdev-scsi-vhost-scsi-pci", QEMU_CAPS_VIRTIO_SCSI, QEMU_CAPS_DEVICE_VHOST_SCSI); - DO_TEST("hostdev-scsi-vhost-scsi-pcie", - QEMU_CAPS_KVM, - QEMU_CAPS_VIRTIO_SCSI, QEMU_CAPS_DEVICE_VHOST_SCSI, - QEMU_CAPS_DEVICE_PCIE_ROOT_PORT, - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY); + DO_TEST_CAPS_LATEST("hostdev-scsi-vhost-scsi-pcie"); DO_TEST("hostdev-scsi-lsi", QEMU_CAPS_VIRTIO_SCSI, QEMU_CAPS_SCSI_LSI); @@ -1075,14 +977,7 @@ mymain(void) DO_TEST("aarch64-aavmf-virtio-mmio", QEMU_CAPS_DEVICE_VIRTIO_MMIO, QEMU_CAPS_DEVICE_VIRTIO_RNG, QEMU_CAPS_OBJECT_RNG_RANDOM); - DO_TEST("aarch64-virtio-pci-default", - QEMU_CAPS_VIRTIO_PCI_DISABLE_LEGACY, - QEMU_CAPS_DEVICE_VIRTIO_MMIO, - QEMU_CAPS_DEVICE_VIRTIO_RNG, QEMU_CAPS_OBJECT_RNG_RANDOM, - QEMU_CAPS_OBJECT_GPEX, QEMU_CAPS_DEVICE_PCI_BRIDGE, - QEMU_CAPS_DEVICE_DMI_TO_PCI_BRIDGE, - QEMU_CAPS_DEVICE_IOH3420, - QEMU_CAPS_VIRTIO_SCSI); + DO_TEST_CAPS_ARCH_LATEST("aarch64-virtio-pci-default", "aarch64"); DO_TEST("aarch64-virtio-pci-manual-addresses", QEMU_CAPS_DEVICE_VIRTIO_MMIO, QEMU_CAPS_DEVICE_VIRTIO_RNG, QEMU_CAPS_OBJECT_RNG_RANDOM, -- 2.37.1