Re: [libvirt] [V4 RESEND PATCH] Expose resource control capabilites on cache bank

> > This could be wrong on new platform in Intel’s SKX CPU after check with platform guys. > > The cbm_mask is “7ff” (11 bits) on SKX. I will refine this by counting the bits. > > We can virFileReadValueString() then convert it to unsigned int, then count the bits of ‘1’. > > thought ? or a new utils function in virfile is required? I missed this patch, sorry. I was thinking about changing it to bit counting, but I thought it will always be divisible by 4. I will send a trivial update to this, but it would be nice to have test cases for it. Could you get some of that data from such a machine n the meantime? If not, I can just coy what we have and change the mask.

> I am not sure min_cbm_bits should be used. > > Besides, on old platform (haswell), the min_cbm_bits is 2, but we still can specify a cbm like > “0x7” ) 3bit while do the cache allocation. > Yes, you can. min_cbm_bits is not a granularity. it is the minimum number of consecutive bits that you need to have when allocating. We should also add the granularity there. I'll fix that as well then.

> Later we need this on doing cache allocation(instead of read these value from the host again), we will > need > 1. total cache size > 2. what the cache size of 1 (CBM) bit stand for, so that we can calculate how many bits we want. > > Maybe we need to add another filed like ’step’ (to indicate 1 bits stand for) ? > > > > control->scope = scope; > > > > > > @@ -1732,10 +1743,10 @@ virCapabilitiesInitCaches(virCapsPtr caps) > > > VIR_CACHE_TYPE_BOTH) < 0) > > > goto cleanup; > > > } else if (typeret == 1) { > > > - if ((virCapabilitiesGetCacheControl(bank, > > > - VIR_CACHE_TYPE_CODE) < 0) || > > > - (virCapabilitiesGetCacheControl(bank, > > > - VIR_CACHE_TYPE_DATA) < 0)) > > > + if (virCapabilitiesGetCacheControl(bank, > > > + VIR_CACHE_TYPE_CODE) < 0 || > > > + virCapabilitiesGetCacheControl(bank, > > > + VIR_CACHE_TYPE_DATA) < 0) > > > goto cleanup; > > > } > > > > > > diff --git i/tests/vircaps2xmldata/vircaps-x86_64-resctrl-cdp.xml w/tests/vircaps2xmldata/vircaps-x86_64-resctrl-cdp.xml > > > index c9f460d8a227..49aa0b98ca88 100644 > > > --- i/tests/vircaps2xmldata/vircaps-x86_64-resctrl-cdp.xml > > > +++ w/tests/vircaps2xmldata/vircaps-x86_64-resctrl-cdp.xml > > > @@ -42,12 +42,12 @@ > > > </topology> > > > <cache> > > > <bank id='0' level='3' type='both' size='15360' unit='KiB' cpus='0-5'> > > > - <control min='768' unit='KiB' scope='code' max_allocation='8'/> > > > - <control min='768' unit='KiB' scope='data' max_allocation='8'/> > > > + <control min='768' unit='KiB' type='code' maxAllocs='8'/> > > > + <control min='768' unit='KiB' type='data' maxAllocs='8'/> > > > </bank> > > > <bank id='1' level='3' type='both' size='15360' unit='KiB' cpus='6-11'> > > > - <control min='768' unit='KiB' scope='code' max_allocation='8'/> > > > - <control min='768' unit='KiB' scope='data' max_allocation='8'/> > > > + <control min='768' unit='KiB' type='code' maxAllocs='8'/> > > > + <control min='768' unit='KiB' type='data' maxAllocs='8'/> > > > </bank> > > > </cache> > > > </host> > > > diff --git i/tests/vircaps2xmldata/vircaps-x86_64-resctrl.xml w/tests/vircaps2xmldata/vircaps-x86_64-resctrl.xml > > > index 04a5eb895727..cb78b4ab788d 100644 > > > --- i/tests/vircaps2xmldata/vircaps-x86_64-resctrl.xml > > > +++ w/tests/vircaps2xmldata/vircaps-x86_64-resctrl.xml > > > @@ -42,10 +42,10 @@ > > > </topology> > > > <cache> > > > <bank id='0' level='3' type='both' size='15360' unit='KiB' cpus='0-5'> > > > - <control min='768' unit='KiB' scope='both' max_allocation='4'/> > > > + <control min='1536' unit='KiB' type='both' maxAllocs='4'/> > > > </bank> > > > <bank id='1' level='3' type='both' size='15360' unit='KiB' cpus='6-11'> > > > - <control min='768' unit='KiB' scope='both' max_allocation='4'/> > > > + <control min='1536' unit='KiB' type='both' maxAllocs='4'/> > > > > > > > > > > > </bank> > > > </cache> > > > </host> > > > -- > > > Martin > > > > > > >