Power8E and Power8NVL were deprecated since QEMU 10.1, with commit 264a604e7163 ("target/ppc: Deprecate Power8E and Power8NVL") Accordingly, remove usage of 8E and 8NVL chips from powernv, as it's old and unmaintained now. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Tested-by: Misbah Anjum N <misanjum@linux.ibm.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> --- docs/system/ppc/powernv.rst | 2 +- hw/ppc/pnv.c | 62 ------------------------------------- hw/ppc/pnv_core.c | 2 -- include/hw/ppc/pnv.h | 8 ----- tests/qtest/pnv-xscom.h | 9 ------ 5 files changed, 1 insertion(+), 82 deletions(-) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index 5154794cc8cd..1de696b588a8 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -15,7 +15,7 @@ beyond the scope of what QEMU addresses today. Supported devices ----------------- - * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11. + * Multi processor support for POWER8, POWER9, Power10 and Power11. * XSCOM, serial communication sideband bus to configure chiplets. * Simple LPC Controller. * Processor Service Interface (PSI) Controller. diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index afb6019b1098..c0cb45dbfbc4 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -869,16 +869,6 @@ static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) return pnv_lpc_isa_create(&chip8->lpc, true, errp); } -static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) -{ - Pnv8Chip *chip8 = PNV8_CHIP(chip); - qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); - - qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); - - return pnv_lpc_isa_create(&chip8->lpc, false, errp); -} - static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); @@ -1646,7 +1636,6 @@ static void *pnv_chip_power11_intc_get(PnvChip *chip) * EX14 * <EX15 reserved> */ -#define POWER8E_CORE_MASK (0x7070ull) #define POWER8_CORE_MASK (0x7e7eull) /* @@ -1827,30 +1816,6 @@ static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); } -static void pnv_chip_power8e_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PnvChipClass *k = PNV_CHIP_CLASS(klass); - - k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ - k->cores_mask = POWER8E_CORE_MASK; - k->num_phbs = 3; - k->get_pir_tir = pnv_get_pir_tir_p8; - k->intc_create = pnv_chip_power8_intc_create; - k->intc_reset = pnv_chip_power8_intc_reset; - k->intc_destroy = pnv_chip_power8_intc_destroy; - k->intc_print_info = pnv_chip_power8_intc_print_info; - k->isa_create = pnv_chip_power8_isa_create; - k->dt_populate = pnv_chip_power8_dt_populate; - k->pic_print_info = pnv_chip_power8_pic_print_info; - k->xscom_core_base = pnv_chip_power8_xscom_core_base; - k->xscom_pcba = pnv_chip_power8_xscom_pcba; - dc->desc = "PowerNV Chip POWER8E"; - - device_class_set_parent_realize(dc, pnv_chip_power8_realize, - &k->parent_realize); -} - static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1875,30 +1840,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data) &k->parent_realize); } -static void pnv_chip_power8nvl_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PnvChipClass *k = PNV_CHIP_CLASS(klass); - - k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ - k->cores_mask = POWER8_CORE_MASK; - k->num_phbs = 4; - k->get_pir_tir = pnv_get_pir_tir_p8; - k->intc_create = pnv_chip_power8_intc_create; - k->intc_reset = pnv_chip_power8_intc_reset; - k->intc_destroy = pnv_chip_power8_intc_destroy; - k->intc_print_info = pnv_chip_power8_intc_print_info; - k->isa_create = pnv_chip_power8nvl_isa_create; - k->dt_populate = pnv_chip_power8_dt_populate; - k->pic_print_info = pnv_chip_power8_pic_print_info; - k->xscom_core_base = pnv_chip_power8_xscom_core_base; - k->xscom_pcba = pnv_chip_power8_xscom_pcba; - dc->desc = "PowerNV Chip POWER8NVL"; - - device_class_set_parent_realize(dc, pnv_chip_power8_realize, - &k->parent_realize); -} - static void pnv_chip_power9_instance_init(Object *obj) { PnvChip *chip = PNV_CHIP(obj); @@ -3785,9 +3726,6 @@ static const TypeInfo types[] = { .instance_size = sizeof(Pnv8Chip), }, DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), - DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), - DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, - pnv_chip_power8nvl_class_init), }; DEFINE_TYPES(types) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8939515c2c34..61dc8211e32f 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -515,9 +515,7 @@ static const TypeInfo pnv_core_infos[] = { .class_init = pnv_core_class_init, .abstract = true, }, - DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), - DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"), diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f8234fb3cd31..60e902d9c5bb 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -39,18 +39,10 @@ typedef struct Pnv10Chip Pnv11Chip; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX -#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") -DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, - TYPE_PNV_CHIP_POWER8E) - #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, TYPE_PNV_CHIP_POWER8) -#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") -DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, - TYPE_PNV_CHIP_POWER8NVL) - #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, TYPE_PNV_CHIP_POWER9) diff --git a/tests/qtest/pnv-xscom.h b/tests/qtest/pnv-xscom.h index 8e882dac9d36..c4c42c694644 100644 --- a/tests/qtest/pnv-xscom.h +++ b/tests/qtest/pnv-xscom.h @@ -12,9 +12,7 @@ #define SMT 4 /* some tests will break if less than 4 */ typedef enum PnvChipType { - PNV_CHIP_POWER8E, /* AKA Murano (default) */ PNV_CHIP_POWER8, /* AKA Venice */ - PNV_CHIP_POWER8NVL, /* AKA Naples */ PNV_CHIP_POWER9, /* AKA Nimbus */ PNV_CHIP_POWER10, PNV_CHIP_POWER11, @@ -37,13 +35,6 @@ static const PnvChip pnv_chips[] = { .cfam_id = 0x220ea04980000000ull, .first_core = 0x1, .num_i2c = 0, - }, { - .chip_type = PNV_CHIP_POWER8NVL, - .cpu_model = "POWER8NVL", - .xscom_base = 0x0003fc0000000000ull, - .cfam_id = 0x120d304980000000ull, - .first_core = 0x1, - .num_i2c = 0, }, { .chip_type = PNV_CHIP_POWER9, -- 2.55.0