Describe the usage of the vlen attribute for RISC-V CPUs. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> --- docs/formatdomain.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index a861f9f177..3856bc8921 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -1810,7 +1810,20 @@ In case no restrictions need to be put on CPU model and its features, a simpler address bits for ``passthrough`` mode, i.e. in case the host CPU reports more bits than that, ``limit`` is used. :since:`Since 9.3.0` +``vlen`` + :since:`Since 12.6.0` the ``vlen`` element describes the length, in bits, + of the vector registers exposed to the guest CPU. This is currently only + supported for RISC-V guests with the ``V`` vector extension enabled, and + corresponds to the QEMU ``vlen`` CPU property, e.g. + ``-cpu rva23s64,vlen=256``. The element is omitted if the vector register + length is not configured, in which case the hypervisor default is used. + + ``value`` + This mandatory attribute specifies the vector register length in bits. + The value must be a power of two in the range [8, 65536]. + Guest NUMA topology can be specified using the ``numa`` element. + :since:`Since 0.9.8` :: -- 2.53.0