[libvirt PATCH v3 00/10] Add missing feature detection to sync tool in cpu_map
sync_qemu_i386.py in src/cpu_map is a tool to sync CPU models from qemu with libvirt. It currently has no provisions for detecting new features that are not implemented in libvirt yet. This series changes that. Currently missing x86 CPU models: * "Denverton" * "KnightsMill" * "Snowridge" Currently missing x86 CPU features: * "core-capability" * "fsrm" * "split-lock-detect" This series adds "core-capability", "fsrm", "split-lock-detect" and the CPU model for "Snowridge". V1: https://www.redhat.com/archives/libvir-list/2020-November/msg01002.html V2: https://www.redhat.com/archives/libvir-list/2020-November/msg01023.html Tim Wiederhake (10): cpu_map: sync_qemu_cpu_i386: Factor out translation of vendors cpu_map: sync_qemu_cpu_i386: Factor out translation of features cpu_map: sync_qemu_cpu_i386: Translate features in model versions cpu_map: sync_qemu_cpu_i386: Simplify ignore features cpu_map: sync_qemu_cpu_i386: Add missing features to translation table cpu_map: sync_qemu_cpu_i386: Detect features missing in libvirt cpu_map: Add support for fsrm CPU feature cpu_map: Add support for core-capability CPU feature cpu_map: Add support for split-lock-detect CPU feature cpu_map: Define and enable Snowridge model src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/sync_qemu_i386.py | 340 ++++++++++-------- src/cpu_map/x86_Snowridge.xml | 71 ++++ src/cpu_map/x86_features.xml | 11 + .../x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + .../x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 22 files changed, 294 insertions(+), 147 deletions(-) create mode 100644 src/cpu_map/x86_Snowridge.xml -- 2.26.2
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index 8deda869df..f86cdf969f 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -8,11 +8,6 @@ import re T = { - # translating qemu -> libvirt cpu vendor names - "CPUID_VENDOR_AMD": "AMD", - "CPUID_VENDOR_INTEL": "Intel", - "CPUID_VENDOR_HYGON": "Hygon", - # translating qemu -> libvirt cpu feature names "CPUID_6_EAX_ARAT": "arat", "CPUID_7_0_EBX_ADX": "adx", @@ -152,6 +147,20 @@ T = { } +def translate_vendor(name): + T = { + "CPUID_VENDOR_AMD": "AMD", + "CPUID_VENDOR_INTEL": "Intel", + "CPUID_VENDOR_HYGON": "Hygon", + } + + if name in T: + return T[name] + + print("warning: Unknown vendor '{}'".format(name)) + return name + + def readline_cont(f): """Read one logical line from a file `f` i.e. continues lines that end in a backslash.""" @@ -264,7 +273,7 @@ def expand_model(model): result = { "name": model.pop(".name"), - "vendor": T[model.pop(".vendor")], + "vendor": translate_vendor(model.pop(".vendor")), "features": set(), "extra": dict()} -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:24 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 289 +++++++++++++++++----------------- 1 file changed, 148 insertions(+), 141 deletions(-) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index f86cdf969f..53b27773e4 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -7,146 +7,6 @@ import os import re -T = { - # translating qemu -> libvirt cpu feature names - "CPUID_6_EAX_ARAT": "arat", - "CPUID_7_0_EBX_ADX": "adx", - "CPUID_7_0_EBX_AVX2": "avx2", - "CPUID_7_0_EBX_AVX512BW": "avx512bw", - "CPUID_7_0_EBX_AVX512CD": "avx512cd", - "CPUID_7_0_EBX_AVX512DQ": "avx512dq", - "CPUID_7_0_EBX_AVX512ER": "avx512er", - "CPUID_7_0_EBX_AVX512F": "avx512f", - "CPUID_7_0_EBX_AVX512PF": "avx512pf", - "CPUID_7_0_EBX_AVX512VL": "avx512vl", - "CPUID_7_0_EBX_BMI1": "bmi1", - "CPUID_7_0_EBX_BMI2": "bmi2", - "CPUID_7_0_EBX_CLFLUSHOPT": "clflushopt", - "CPUID_7_0_EBX_CLWB": "clwb", - "CPUID_7_0_EBX_ERMS": "erms", - "CPUID_7_0_EBX_FSGSBASE": "fsgsbase", - "CPUID_7_0_EBX_HLE": "hle", - "CPUID_7_0_EBX_INVPCID": "invpcid", - "CPUID_7_0_EBX_MPX": "mpx", - "CPUID_7_0_EBX_RDSEED": "rdseed", - "CPUID_7_0_EBX_RTM": "rtm", - "CPUID_7_0_EBX_SHA_NI": "sha-ni", - "CPUID_7_0_EBX_SMAP": "smap", - "CPUID_7_0_EBX_SMEP": "smep", - "CPUID_7_0_ECX_AVX512BITALG": "avx512bitalg", - "CPUID_7_0_ECX_AVX512_VBMI2": "avx512vbmi2", - "CPUID_7_0_ECX_AVX512_VBMI": "avx512vbmi", - "CPUID_7_0_ECX_AVX512VNNI": "avx512vnni", - "CPUID_7_0_ECX_AVX512_VPOPCNTDQ": "avx512-vpopcntdq", - "CPUID_7_0_ECX_CLDEMOTE": "cldemote", - "CPUID_7_0_ECX_GFNI": "gfni", - "CPUID_7_0_ECX_LA57": "la57", - "CPUID_7_0_ECX_MOVDIR64B": "movdir64b", - "CPUID_7_0_ECX_MOVDIRI": "movdiri", - "CPUID_7_0_ECX_PKU": "pku", - "CPUID_7_0_ECX_RDPID": "rdpid", - "CPUID_7_0_ECX_UMIP": "umip", - "CPUID_7_0_ECX_VAES": "vaes", - "CPUID_7_0_ECX_VPCLMULQDQ": "vpclmulqdq", - "CPUID_7_0_EDX_ARCH_CAPABILITIES": "arch-capabilities", - "CPUID_7_0_EDX_AVX512_4FMAPS": "avx512-4fmaps", - "CPUID_7_0_EDX_AVX512_4VNNIW": "avx512-4vnniw", - "CPUID_7_0_EDX_CORE_CAPABILITY": "core-capability", - "CPUID_7_0_EDX_SPEC_CTRL": "spec-ctrl", - "CPUID_7_0_EDX_SPEC_CTRL_SSBD": "ssbd", - "CPUID_7_0_EDX_STIBP": "stibp", - "CPUID_7_1_EAX_AVX512_BF16": "avx512-bf16", - "CPUID_8000_0008_EBX_CLZERO": "clzero", - "CPUID_8000_0008_EBX_IBPB": "ibpb", - "CPUID_8000_0008_EBX_STIBP": "amd-stibp", - "CPUID_8000_0008_EBX_WBNOINVD": "wbnoinvd", - "CPUID_8000_0008_EBX_XSAVEERPTR": "xsaveerptr", - "CPUID_ACPI": "acpi", - "CPUID_APIC": "apic", - "CPUID_CLFLUSH": "clflush", - "CPUID_CMOV": "cmov", - "CPUID_CX8": "cx8", - "CPUID_DE": "de", - "CPUID_EXT2_3DNOW": "3dnow", - "CPUID_EXT2_3DNOWEXT": "3dnowext", - "CPUID_EXT2_FFXSR": "fxsr_opt", - "CPUID_EXT2_LM": "lm", - "CPUID_EXT2_MMXEXT": "mmxext", - "CPUID_EXT2_NX": "nx", - "CPUID_EXT2_PDPE1GB": "pdpe1gb", - "CPUID_EXT2_RDTSCP": "rdtscp", - "CPUID_EXT2_SYSCALL": "syscall", - "CPUID_EXT3_3DNOWPREFETCH": "3dnowprefetch", - "CPUID_EXT3_ABM": "abm", - "CPUID_EXT3_CR8LEG": "cr8legacy", - "CPUID_EXT3_FMA4": "fma4", - "CPUID_EXT3_LAHF_LM": "lahf_lm", - "CPUID_EXT3_MISALIGNSSE": "misalignsse", - "CPUID_EXT3_OSVW": "osvw", - "CPUID_EXT3_PERFCORE": "perfctr_core", - "CPUID_EXT3_SSE4A": "sse4a", - "CPUID_EXT3_SVM": "svm", - "CPUID_EXT3_TBM": "tbm", - "CPUID_EXT3_XOP": "xop", - "CPUID_EXT_AES": "aes", - "CPUID_EXT_AVX": "avx", - "CPUID_EXT_CX16": "cx16", - "CPUID_EXT_F16C": "f16c", - "CPUID_EXT_FMA": "fma", - "CPUID_EXT_MOVBE": "movbe", - "CPUID_EXT_PCID": "pcid", - "CPUID_EXT_PCLMULQDQ": "pclmuldq", - "CPUID_EXT_POPCNT": "popcnt", - "CPUID_EXT_RDRAND": "rdrand", - "CPUID_EXT_SSE3": "pni", - "CPUID_EXT_SSE41": "sse4.1", - "CPUID_EXT_SSE42": "sse4.2", - "CPUID_EXT_SSSE3": "ssse3", - "CPUID_EXT_TSC_DEADLINE_TIMER": "tsc-deadline", - "CPUID_EXT_X2APIC": "x2apic", - "CPUID_EXT_XSAVE": "xsave", - "CPUID_FP87": "fpu", - "CPUID_FXSR": "fxsr", - "CPUID_MCA": "mca", - "CPUID_MCE": "mce", - "CPUID_MMX": "mmx", - "CPUID_MSR": "msr", - "CPUID_MTRR": "mtrr", - "CPUID_PAE": "pae", - "CPUID_PAT": "pat", - "CPUID_PGE": "pge", - "CPUID_PSE36": "pse36", - "CPUID_PSE": "pse", - "CPUID_SEP": "sep", - "CPUID_SSE2": "sse2", - "CPUID_SSE": "sse", - "CPUID_SS": "ss", - "CPUID_SVM_NPT": "npt", - "CPUID_SVM_NRIPSAVE": "nrip-save", - "CPUID_TSC": "tsc", - "CPUID_VME": "vme", - "CPUID_XSAVE_XGETBV1": "xgetbv1", - "CPUID_XSAVE_XSAVEC": "xsavec", - "CPUID_XSAVE_XSAVEOPT": "xsaveopt", - "CPUID_XSAVE_XSAVES": "xsaves", - "MSR_ARCH_CAP_IBRS_ALL": "ibrs-all", - "MSR_ARCH_CAP_MDS_NO": "mds-no", - "MSR_ARCH_CAP_PSCHANGE_MC_NO": "pschange-mc-no", - "MSR_ARCH_CAP_RDCL_NO": "rdctl-no", - "MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY": "skip-l1dfl-vmentry", - "MSR_ARCH_CAP_TAA_NO": "taa-no", - "MSR_CORE_CAP_SPLIT_LOCK_DETECT": "split-lock-detect", - - # always disabled features - "CPUID_EXT_MONITOR": None, - "0": None, - - # set to "no auto enable" by qemu - "CPUID_EXT3_TOPOEXT": None, - "MSR_VMX_BASIC_DUAL_MONITOR": None, -} - - def translate_vendor(name): T = { "CPUID_VENDOR_AMD": "AMD", @@ -161,6 +21,153 @@ def translate_vendor(name): return name +def translate_feature(name): + T = { + # translating qemu -> libvirt cpu feature names + "CPUID_6_EAX_ARAT": "arat", + "CPUID_7_0_EBX_ADX": "adx", + "CPUID_7_0_EBX_AVX2": "avx2", + "CPUID_7_0_EBX_AVX512BW": "avx512bw", + "CPUID_7_0_EBX_AVX512CD": "avx512cd", + "CPUID_7_0_EBX_AVX512DQ": "avx512dq", + "CPUID_7_0_EBX_AVX512ER": "avx512er", + "CPUID_7_0_EBX_AVX512F": "avx512f", + "CPUID_7_0_EBX_AVX512PF": "avx512pf", + "CPUID_7_0_EBX_AVX512VL": "avx512vl", + "CPUID_7_0_EBX_BMI1": "bmi1", + "CPUID_7_0_EBX_BMI2": "bmi2", + "CPUID_7_0_EBX_CLFLUSHOPT": "clflushopt", + "CPUID_7_0_EBX_CLWB": "clwb", + "CPUID_7_0_EBX_ERMS": "erms", + "CPUID_7_0_EBX_FSGSBASE": "fsgsbase", + "CPUID_7_0_EBX_HLE": "hle", + "CPUID_7_0_EBX_INVPCID": "invpcid", + "CPUID_7_0_EBX_MPX": "mpx", + "CPUID_7_0_EBX_RDSEED": "rdseed", + "CPUID_7_0_EBX_RTM": "rtm", + "CPUID_7_0_EBX_SHA_NI": "sha-ni", + "CPUID_7_0_EBX_SMAP": "smap", + "CPUID_7_0_EBX_SMEP": "smep", + "CPUID_7_0_ECX_AVX512BITALG": "avx512bitalg", + "CPUID_7_0_ECX_AVX512_VBMI2": "avx512vbmi2", + "CPUID_7_0_ECX_AVX512_VBMI": "avx512vbmi", + "CPUID_7_0_ECX_AVX512VNNI": "avx512vnni", + "CPUID_7_0_ECX_AVX512_VPOPCNTDQ": "avx512-vpopcntdq", + "CPUID_7_0_ECX_CLDEMOTE": "cldemote", + "CPUID_7_0_ECX_GFNI": "gfni", + "CPUID_7_0_ECX_LA57": "la57", + "CPUID_7_0_ECX_MOVDIR64B": "movdir64b", + "CPUID_7_0_ECX_MOVDIRI": "movdiri", + "CPUID_7_0_ECX_PKU": "pku", + "CPUID_7_0_ECX_RDPID": "rdpid", + "CPUID_7_0_ECX_UMIP": "umip", + "CPUID_7_0_ECX_VAES": "vaes", + "CPUID_7_0_ECX_VPCLMULQDQ": "vpclmulqdq", + "CPUID_7_0_EDX_ARCH_CAPABILITIES": "arch-capabilities", + "CPUID_7_0_EDX_AVX512_4FMAPS": "avx512-4fmaps", + "CPUID_7_0_EDX_AVX512_4VNNIW": "avx512-4vnniw", + "CPUID_7_0_EDX_CORE_CAPABILITY": "core-capability", + "CPUID_7_0_EDX_SPEC_CTRL": "spec-ctrl", + "CPUID_7_0_EDX_SPEC_CTRL_SSBD": "ssbd", + "CPUID_7_0_EDX_STIBP": "stibp", + "CPUID_7_1_EAX_AVX512_BF16": "avx512-bf16", + "CPUID_8000_0008_EBX_CLZERO": "clzero", + "CPUID_8000_0008_EBX_IBPB": "ibpb", + "CPUID_8000_0008_EBX_STIBP": "amd-stibp", + "CPUID_8000_0008_EBX_WBNOINVD": "wbnoinvd", + "CPUID_8000_0008_EBX_XSAVEERPTR": "xsaveerptr", + "CPUID_ACPI": "acpi", + "CPUID_APIC": "apic", + "CPUID_CLFLUSH": "clflush", + "CPUID_CMOV": "cmov", + "CPUID_CX8": "cx8", + "CPUID_DE": "de", + "CPUID_EXT2_3DNOW": "3dnow", + "CPUID_EXT2_3DNOWEXT": "3dnowext", + "CPUID_EXT2_FFXSR": "fxsr_opt", + "CPUID_EXT2_LM": "lm", + "CPUID_EXT2_MMXEXT": "mmxext", + "CPUID_EXT2_NX": "nx", + "CPUID_EXT2_PDPE1GB": "pdpe1gb", + "CPUID_EXT2_RDTSCP": "rdtscp", + "CPUID_EXT2_SYSCALL": "syscall", + "CPUID_EXT3_3DNOWPREFETCH": "3dnowprefetch", + "CPUID_EXT3_ABM": "abm", + "CPUID_EXT3_CR8LEG": "cr8legacy", + "CPUID_EXT3_FMA4": "fma4", + "CPUID_EXT3_LAHF_LM": "lahf_lm", + "CPUID_EXT3_MISALIGNSSE": "misalignsse", + "CPUID_EXT3_OSVW": "osvw", + "CPUID_EXT3_PERFCORE": "perfctr_core", + "CPUID_EXT3_SSE4A": "sse4a", + "CPUID_EXT3_SVM": "svm", + "CPUID_EXT3_TBM": "tbm", + "CPUID_EXT3_XOP": "xop", + "CPUID_EXT_AES": "aes", + "CPUID_EXT_AVX": "avx", + "CPUID_EXT_CX16": "cx16", + "CPUID_EXT_F16C": "f16c", + "CPUID_EXT_FMA": "fma", + "CPUID_EXT_MOVBE": "movbe", + "CPUID_EXT_PCID": "pcid", + "CPUID_EXT_PCLMULQDQ": "pclmuldq", + "CPUID_EXT_POPCNT": "popcnt", + "CPUID_EXT_RDRAND": "rdrand", + "CPUID_EXT_SSE3": "pni", + "CPUID_EXT_SSE41": "sse4.1", + "CPUID_EXT_SSE42": "sse4.2", + "CPUID_EXT_SSSE3": "ssse3", + "CPUID_EXT_TSC_DEADLINE_TIMER": "tsc-deadline", + "CPUID_EXT_X2APIC": "x2apic", + "CPUID_EXT_XSAVE": "xsave", + "CPUID_FP87": "fpu", + "CPUID_FXSR": "fxsr", + "CPUID_MCA": "mca", + "CPUID_MCE": "mce", + "CPUID_MMX": "mmx", + "CPUID_MSR": "msr", + "CPUID_MTRR": "mtrr", + "CPUID_PAE": "pae", + "CPUID_PAT": "pat", + "CPUID_PGE": "pge", + "CPUID_PSE36": "pse36", + "CPUID_PSE": "pse", + "CPUID_SEP": "sep", + "CPUID_SSE2": "sse2", + "CPUID_SSE": "sse", + "CPUID_SS": "ss", + "CPUID_SVM_NPT": "npt", + "CPUID_SVM_NRIPSAVE": "nrip-save", + "CPUID_TSC": "tsc", + "CPUID_VME": "vme", + "CPUID_XSAVE_XGETBV1": "xgetbv1", + "CPUID_XSAVE_XSAVEC": "xsavec", + "CPUID_XSAVE_XSAVEOPT": "xsaveopt", + "CPUID_XSAVE_XSAVES": "xsaves", + "MSR_ARCH_CAP_IBRS_ALL": "ibrs-all", + "MSR_ARCH_CAP_MDS_NO": "mds-no", + "MSR_ARCH_CAP_PSCHANGE_MC_NO": "pschange-mc-no", + "MSR_ARCH_CAP_RDCL_NO": "rdctl-no", + "MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY": "skip-l1dfl-vmentry", + "MSR_ARCH_CAP_TAA_NO": "taa-no", + "MSR_CORE_CAP_SPLIT_LOCK_DETECT": "split-lock-detect", + + # always disabled features + "CPUID_EXT_MONITOR": None, + "0": None, + + # set to "no auto enable" by qemu + "CPUID_EXT3_TOPOEXT": None, + "MSR_VMX_BASIC_DUAL_MONITOR": None, + } + + if name in T: + return T[name] + + print("warning: Unknown feature '{}'".format(name)) + return name + + def readline_cont(f): """Read one logical line from a file `f` i.e. continues lines that end in a backslash.""" @@ -286,7 +293,7 @@ def expand_model(model): for feature in v.split(): if feature.startswith("VMX_") or feature.startswith("MSR_VMX_"): continue - translated = T.get(feature, feature) + translated = translate_feature(feature) if translated: result["features"].add(translated) -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:25 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 289 +++++++++++++++++----------------- 1 file changed, 148 insertions(+), 141 deletions(-)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
If a feature is added (or removed) in a QEMU CPU model version, we get to see the QEMU pretty name for the feature, not the name of the macro. Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index 53b27773e4..93630f1a55 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -164,6 +164,10 @@ def translate_feature(name): if name in T: return T[name] + for v in T.values(): + if name.replace("-", "_") == v.replace("-", "_"): + return v + print("warning: Unknown feature '{}'".format(name)) return name @@ -308,6 +312,11 @@ def expand_model(model): props = version.pop(".props", dict()) for k, v in props: + if k not in ("model-id", "stepping", "model"): + k = translate_feature(k) + if k is None: + continue + if v == "on": result["features"].add(k) elif v == "off" and k in result["features"]: -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:26 +0100, Tim Wiederhake wrote:
If a feature is added (or removed) in a QEMU CPU model version, we get to see the QEMU pretty name for the feature, not the name of the macro.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 9 +++++++++ 1 file changed, 9 insertions(+)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index 93630f1a55..acf27d2bec 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -23,7 +23,6 @@ def translate_vendor(name): def translate_feature(name): T = { - # translating qemu -> libvirt cpu feature names "CPUID_6_EAX_ARAT": "arat", "CPUID_7_0_EBX_ADX": "adx", "CPUID_7_0_EBX_AVX2": "avx2", @@ -151,16 +150,21 @@ def translate_feature(name): "MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY": "skip-l1dfl-vmentry", "MSR_ARCH_CAP_TAA_NO": "taa-no", "MSR_CORE_CAP_SPLIT_LOCK_DETECT": "split-lock-detect", - - # always disabled features - "CPUID_EXT_MONITOR": None, - "0": None, - - # set to "no auto enable" by qemu - "CPUID_EXT3_TOPOEXT": None, - "MSR_VMX_BASIC_DUAL_MONITOR": None, } + ignore = any([ + name.startswith("VMX_"), + name.startswith("vmx-"), + name.startswith("MSR_VMX_"), + name in ("0", "model", "model-id", "stepping"), + name in ("CPUID_EXT_MONITOR", "monitor"), + name in ("MSR_VMX_BASIC_DUAL_MONITOR", "dual-monitor"), + name in ("CPUID_EXT3_TOPOEXT", "topoext"), + ]) + + if ignore: + return None + if name in T: return T[name] @@ -295,8 +299,6 @@ def expand_model(model): for k in [k for k in model if k.startswith(".features")]: v = model.pop(k) for feature in v.split(): - if feature.startswith("VMX_") or feature.startswith("MSR_VMX_"): - continue translated = translate_feature(feature) if translated: result["features"].add(translated) -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:27 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index acf27d2bec..83b21a93e5 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -31,6 +31,7 @@ def translate_feature(name): "CPUID_7_0_EBX_AVX512DQ": "avx512dq", "CPUID_7_0_EBX_AVX512ER": "avx512er", "CPUID_7_0_EBX_AVX512F": "avx512f", + "CPUID_7_0_EBX_AVX512IFMA": "avx512ifma", "CPUID_7_0_EBX_AVX512PF": "avx512pf", "CPUID_7_0_EBX_AVX512VL": "avx512vl", "CPUID_7_0_EBX_BMI1": "bmi1", @@ -66,6 +67,7 @@ def translate_feature(name): "CPUID_7_0_EDX_AVX512_4FMAPS": "avx512-4fmaps", "CPUID_7_0_EDX_AVX512_4VNNIW": "avx512-4vnniw", "CPUID_7_0_EDX_CORE_CAPABILITY": "core-capability", + "CPUID_7_0_EDX_FSRM": "fsrm", "CPUID_7_0_EDX_SPEC_CTRL": "spec-ctrl", "CPUID_7_0_EDX_SPEC_CTRL_SSBD": "ssbd", "CPUID_7_0_EDX_STIBP": "stibp", -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:28 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/cpu_map/sync_qemu_i386.py b/src/cpu_map/sync_qemu_i386.py index 83b21a93e5..d2a05db77c 100755 --- a/src/cpu_map/sync_qemu_i386.py +++ b/src/cpu_map/sync_qemu_i386.py @@ -5,6 +5,7 @@ import copy import lark import os import re +import xml.etree.ElementTree def translate_vendor(name): @@ -393,6 +394,22 @@ def main(): with open(name, "wt") as f: output_model(f, model) + features = set() + for model in models: + features.update(model["features"]) + + try: + filename = os.path.join(args.outdir, "x86_features.xml") + dom = xml.etree.ElementTree.parse(filename) + known = [x.attrib["name"] for x in dom.getroot().iter("feature")] + unknown = [x for x in features if x not in known and x is not None] + except Exception as e: + unknown = [] + print("warning: Unable to read libvirt x86_features.xml: {}".format(e)) + + for x in unknown: + print("warning: Feature unknown to libvirt: {}".format(x)) + if __name__ == "__main__": main() -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:29 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/sync_qemu_i386.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com> I pushed the first 6 patches of this series.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + 3 files changed, 5 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a55f52b16c..b0bf22d916 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -339,6 +339,9 @@ <feature name='avx512-4fmaps'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000008'/> </feature> + <feature name='fsrm'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000010'/> + </feature> <feature name='md-clear'> <!-- md_clear --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000400'/> </feature> diff --git a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml index 9b75ace710..3a71b28cfb 100644 --- a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml +++ b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml @@ -24,6 +24,7 @@ <feature policy='require' name='sha-ni'/> <feature policy='require' name='ospke'/> <feature policy='require' name='rdpid'/> + <feature policy='require' name='fsrm'/> <feature policy='require' name='stibp'/> <feature policy='require' name='arch-capabilities'/> <feature policy='require' name='xsaves'/> diff --git a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml index efbf9d363b..1582de0422 100644 --- a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml +++ b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml @@ -25,6 +25,7 @@ <feature name='sha-ni'/> <feature name='ospke'/> <feature name='rdpid'/> + <feature name='fsrm'/> <feature name='stibp'/> <feature name='arch-capabilities'/> <feature name='xsaves'/> -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:30 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + 3 files changed, 5 insertions(+)
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index b0bf22d916..a5a987deba 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -357,6 +357,9 @@ <feature name='arch-capabilities'> <!-- arch_capabilities, arch-facilities --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x20000000'/> </feature> + <feature name='core-capability'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x40000000'/> + </feature> <feature name='ssbd'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x80000000'/> </feature> -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:31 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index b0bf22d916..a5a987deba 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -357,6 +357,9 @@ <feature name='arch-capabilities'> <!-- arch_capabilities, arch-facilities --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x20000000'/> </feature> + <feature name='core-capability'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x40000000'/> + </feature> <feature name='ssbd'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x80000000'/> </feature>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus> -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:32 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus>
This patch is fine, but cpu-gather.sh script (in tests/cputestdata) needs to be updated to cover this new MSR to make sure our future (including the one which should be part of this series) test data sets are complete. Jirka
On Wed, 2020-12-09 at 14:43 +0100, Jiri Denemark wrote:
On Mon, Nov 23, 2020 at 15:14:32 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus>
This patch is fine, but cpu-gather.sh script (in tests/cputestdata) needs to be updated to cover this new MSR to make sure our future (including the one which should be part of this series) test data sets are complete.
Jirka
I am working on that change right now. The series will also include some cleanup of the scripts involved. Cheers, Tim
On Wed, Dec 09, 2020 at 14:51:27 +0100, Tim Wiederhake wrote:
On Wed, 2020-12-09 at 14:43 +0100, Jiri Denemark wrote:
On Mon, Nov 23, 2020 at 15:14:32 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus>
This patch is fine, but cpu-gather.sh script (in tests/cputestdata) needs to be updated to cover this new MSR to make sure our future (including the one which should be part of this series) test data sets are complete.
Jirka
I am working on that change right now. The series will also include some cleanup of the scripts involved.
Nice, they certainly deserve it :-) Jirka
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/x86_Snowridge.xml | 71 +++++++++++++++++++ .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 18 files changed, 88 insertions(+) create mode 100644 src/cpu_map/x86_Snowridge.xml diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml index 065d9aede0..2e0685df68 100644 --- a/src/cpu_map/index.xml +++ b/src/cpu_map/index.xml @@ -55,6 +55,7 @@ <include filename='x86_Icelake-Server.xml'/> <include filename='x86_Icelake-Server-noTSX.xml'/> <include filename='x86_Cooperlake.xml'/> + <include filename='x86_Snowridge.xml'/> <!-- AMD CPUs --> <include filename='x86_athlon.xml'/> diff --git a/src/cpu_map/meson.build b/src/cpu_map/meson.build index 8efa9207a2..48f69f623c 100644 --- a/src/cpu_map/meson.build +++ b/src/cpu_map/meson.build @@ -72,6 +72,7 @@ cpumap_data = [ 'x86_Skylake-Server-IBRS.xml', 'x86_Skylake-Server-noTSX-IBRS.xml', 'x86_Skylake-Server.xml', + 'x86_Snowridge.xml', 'x86_vendors.xml', 'x86_Westmere-IBRS.xml', 'x86_Westmere.xml', diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml new file mode 100644 index 0000000000..c0b94834ce --- /dev/null +++ b/src/cpu_map/x86_Snowridge.xml @@ -0,0 +1,71 @@ +<cpus> + <model name='Snowridge'> + <decode host='on' guest='on'/> + <signature family='6' model='134'/> + <vendor name='Intel'/> + <feature name='3dnowprefetch'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='arat'/> + <feature name='arch-capabilities'/> + <feature name='cldemote'/> + <feature name='clflush'/> + <feature name='clflushopt'/> + <feature name='clwb'/> + <feature name='cmov'/> + <feature name='core-capability'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='erms'/> + <feature name='fpu'/> + <feature name='fsgsbase'/> + <feature name='fxsr'/> + <feature name='gfni'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='movbe'/> + <feature name='movdir64b'/> + <feature name='movdiri'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pclmuldq'/> + <feature name='pdpe1gb'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='rdrand'/> + <feature name='rdseed'/> + <feature name='rdtscp'/> + <feature name='sep'/> + <feature name='sha-ni'/> + <feature name='smap'/> + <feature name='smep'/> + <feature name='spec-ctrl'/> + <feature name='split-lock-detect'/> + <feature name='ssbd'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='umip'/> + <feature name='vme'/> + <feature name='x2apic'/> + <feature name='xgetbv1'/> + <feature name='xsave'/> + <feature name='xsavec'/> + <feature name='xsaveopt'/> + </model> +</cpus> diff --git a/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml index 3a7e01c809..39050a2b7d 100644 --- a/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='yes'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml index bb1dacc14c..9246220964 100644 --- a/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml @@ -75,6 +75,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='no'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='no'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.1.0.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0.x86_64.xml index 577b7f439d..1fc14a7dd6 100644 --- a/tests/domaincapsdata/qemu_4.1.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0.x86_64.xml @@ -67,6 +67,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='yes'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml index 1a65f6e727..a57529ee03 100644 --- a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml index 622acc47a1..3721676e0d 100644 --- a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml @@ -75,6 +75,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='no'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml index da9cf56ba5..6013d01e54 100644 --- a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml index a42bec4d87..4a30b558c0 100644 --- a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml index 40d691a62d..54308b9c38 100644 --- a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml @@ -74,6 +74,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml index 57638696f8..abaa54d493 100644 --- a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml index 9fba7f33ab..39452be343 100644 --- a/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml @@ -70,6 +70,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml index 21db6a084a..022367239f 100644 --- a/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml @@ -74,6 +74,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0.x86_64.xml index 1984ed2e07..d7477951b6 100644 --- a/tests/domaincapsdata/qemu_5.1.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml index 5a3777f6f8..7111bdf2c5 100644 --- a/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml @@ -70,6 +70,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml index ad10e7b8fd..f8df73ba07 100644 --- a/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml @@ -74,6 +74,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0.x86_64.xml index ab6455c3fc..d8113c4e92 100644 --- a/tests/domaincapsdata/qemu_5.2.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> -- 2.26.2
On Mon, Nov 23, 2020 at 15:14:33 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/x86_Snowridge.xml | 71 +++++++++++++++++++ .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 18 files changed, 88 insertions(+) create mode 100644 src/cpu_map/x86_Snowridge.xml
...
diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml new file mode 100644 index 0000000000..c0b94834ce --- /dev/null +++ b/src/cpu_map/x86_Snowridge.xml @@ -0,0 +1,71 @@ +<cpus> + <model name='Snowridge'> + <decode host='on' guest='on'/> + <signature family='6' model='134'/>
Sigh. This is the same signature we use for Icelake-Server, which is most likely wrong. The question is which one should be changed and to what value? But most likely the Icelake-Server signature is wrong. We copied it from QEMU, but I haven't seen a mention of any real Icelake-Server CPU with such signature (or perhaps at all). Anyway, it would be nice if we could add a test data (prior to this patch) from host with Snowridge CPU to prove its signature is correct. Jirka
On Mon, Nov 23, 2020 at 15:14:23 +0100, Tim Wiederhake wrote:
sync_qemu_i386.py in src/cpu_map is a tool to sync CPU models from qemu with libvirt. It currently has no provisions for detecting new features that are not implemented in libvirt yet. This series changes that.
Currently missing x86 CPU models: * "Denverton" * "KnightsMill" * "Snowridge"
Currently missing x86 CPU features: * "core-capability" * "fsrm" * "split-lock-detect"
This series adds "core-capability", "fsrm", "split-lock-detect" and the CPU model for "Snowridge".
Although I acked patches 7 and 8 now, I think it makes sense to push them with the rest of the Snowridge CPU model (included tests). Feel free to include the Reviewed-by tags to does patches when resending them accompanied with the new patches. Jirka
participants (2)
-
Jiri Denemark -
Tim Wiederhake