[PATCH v5 00/28] hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines
Hi, A brief introduction from Philippe's v4: The versioned 'pc' and 'q35' machines up to 2.12 been marked as deprecated three releases ago, and are older than 6 years, so according to our support policy we can remove them. This series only includes the 2.6 and 2.7 machines removal, as it is a big enough number of LoC removed. Rest will follow. This v5 is based on the master branch at the commit 66ec38b6fa59 ("Merge tag 'pull-target-arm-20251201' of https://gitlab.com/pm215/qemu into staging"). (Main) changes since v4: * Completely remove the legacy CPU hotplug approach. - New patch 2-8. - Test CPU hot-plug & hot-unplug via qmp. * Keep "dma_enabled" property in fw_cfg_io_properties[] since Sun4u & Sun4v are still using it. - About more details, please see commit message of patch 15. * Temporarily keep these properties: "cpuid-0xb" (of X86CPU), "fill-mtrr-mask" (of X86CPU), "version" (of IOAPICCommonState). - These properties will be deprecated first before removal, in another series. * Keep "l3-cache" (of X86CPU) and "page-per-vq" (of VirtIOPCIProxy), since they are still in use (e.g., libvirt). Thank you everyone for the reviews and patience, and also thank you Philippe for the guidance and Igor for the patch. Best Regards, Zhao --- Igor Mammedov (3): tests/acpi: Allow DSDT table change for x86 machines pc: Start with modern CPU hotplug interface by default acpi: Remove legacy cpu hotplug utilities Philippe Mathieu-Daudé (22): hw/i386/pc: Remove deprecated pc-q35-2.6 and pc-i440fx-2.6 machines hw/i386/pc: Remove PCMachineClass::legacy_cpu_hotplug field hw/nvram/fw_cfg: Rename fw_cfg_init_mem() with '_nodma' suffix hw/mips/loongson3_virt: Prefer using fw_cfg_init_mem_nodma() hw/nvram/fw_cfg: Factor fw_cfg_init_mem_internal() out hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() -> fw_cfg_init_mem_dma() hw/i386/x86: Remove X86MachineClass::fwcfg_dma_enabled field hw/i386/pc: Remove multiboot.bin hw/i386: Assume fw_cfg DMA is always enabled hw/i386: Remove linuxboot.bin hw/i386/pc: Remove pc_compat_2_6[] array hw/intc/apic: Remove APICCommonState::legacy_instance_id field hw/core/machine: Remove hw_compat_2_6[] array hw/virtio/virtio-mmio: Remove VirtIOMMIOProxy::format_transport_address field hw/i386/pc: Remove deprecated pc-q35-2.7 and pc-i440fx-2.7 machines hw/i386/pc: Remove pc_compat_2_7[] array target/i386/cpu: Remove CPUX86State::full_cpuid_auto_level field hw/audio/pcspk: Remove PCSpkState::migrate field hw/core/machine: Remove hw_compat_2_7[] array hw/i386/intel_iommu: Remove IntelIOMMUState::buggy_eim field hw/virtio/virtio-pci: Remove VirtIOPCIProxy::ignore_backend_features field hw/char/virtio-serial: Do not expose the 'emergency-write' property Zhao Liu (3): docs/specs/acpi_cpu_hotplug: Remove legacy cpu hotplug descriptions tests/acpi: Update DSDT tables for pc machine tests/acpi: Update DSDT tables for q35 machine docs/specs/acpi_cpu_hotplug.rst | 28 +- hw/acpi/acpi-cpu-hotplug-stub.c | 19 +- hw/acpi/cpu.c | 10 - hw/acpi/cpu_hotplug.c | 348 ------------------ hw/acpi/generic_event_device.c | 1 + hw/acpi/ich9.c | 61 +-- hw/acpi/meson.build | 2 +- hw/acpi/piix4.c | 61 +-- hw/arm/virt.c | 2 +- hw/audio/pcspk.c | 10 - hw/char/virtio-serial-bus.c | 9 +- hw/core/machine.c | 17 - hw/hppa/machine.c | 2 +- hw/i386/acpi-build.c | 7 +- hw/i386/fw_cfg.c | 16 +- hw/i386/intel_iommu.c | 5 +- hw/i386/microvm.c | 3 - hw/i386/multiboot.c | 7 +- hw/i386/pc.c | 25 +- hw/i386/pc_piix.c | 23 -- hw/i386/pc_q35.c | 24 -- hw/i386/x86-common.c | 8 +- hw/i386/x86.c | 2 - hw/intc/apic_common.c | 5 - hw/loongarch/fw_cfg.c | 4 +- hw/loongarch/virt-acpi-build.c | 1 - hw/mips/loongson3_virt.c | 2 +- hw/nvram/fw_cfg.c | 22 +- hw/riscv/virt.c | 4 +- hw/virtio/virtio-mmio.c | 15 - hw/virtio/virtio-pci.c | 5 +- include/hw/acpi/cpu.h | 1 - include/hw/acpi/cpu_hotplug.h | 40 -- include/hw/acpi/ich9.h | 4 +- include/hw/acpi/piix4.h | 4 +- include/hw/boards.h | 6 - include/hw/i386/apic_internal.h | 1 - include/hw/i386/intel_iommu.h | 1 - include/hw/i386/pc.h | 9 - include/hw/i386/x86.h | 2 - include/hw/nvram/fw_cfg.h | 9 +- include/hw/virtio/virtio-mmio.h | 1 - include/hw/virtio/virtio-pci.h | 1 - include/hw/virtio/virtio-serial.h | 2 - pc-bios/meson.build | 2 - pc-bios/multiboot.bin | Bin 1024 -> 0 bytes pc-bios/optionrom/Makefile | 2 +- pc-bios/optionrom/linuxboot.S | 195 ---------- pc-bios/optionrom/multiboot.S | 232 ------------ pc-bios/optionrom/multiboot_dma.S | 234 +++++++++++- pc-bios/optionrom/optionrom.h | 4 - target/i386/cpu.c | 111 +++--- target/i386/cpu.h | 3 - tests/data/acpi/x86/pc/DSDT | Bin 8611 -> 8598 bytes tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8522 -> 8509 bytes tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9936 -> 9923 bytes tests/data/acpi/x86/pc/DSDT.bridge | Bin 15482 -> 15469 bytes tests/data/acpi/x86/pc/DSDT.cphp | Bin 9075 -> 9062 bytes tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10265 -> 10252 bytes tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8562 -> 8549 bytes tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5100 -> 5087 bytes tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8683 -> 8670 bytes tests/data/acpi/x86/pc/DSDT.memhp | Bin 9970 -> 9957 bytes tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8469 -> 8456 bytes tests/data/acpi/x86/pc/DSDT.numamem | Bin 8617 -> 8604 bytes tests/data/acpi/x86/pc/DSDT.roothp | Bin 12404 -> 12391 bytes tests/data/acpi/x86/q35/DSDT | Bin 8440 -> 8427 bytes tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9765 -> 9752 bytes .../data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12650 -> 12637 bytes .../acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8719 -> 8706 bytes tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8486 -> 8473 bytes tests/data/acpi/x86/q35/DSDT.bridge | Bin 12053 -> 12040 bytes tests/data/acpi/x86/q35/DSDT.core-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.cphp | Bin 8904 -> 8891 bytes tests/data/acpi/x86/q35/DSDT.cxl | Bin 13231 -> 13218 bytes tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10094 -> 10081 bytes tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8515 -> 8502 bytes tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8528 -> 8515 bytes tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.memhp | Bin 9799 -> 9786 bytes tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9570 -> 9557 bytes tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13293 -> 13280 bytes tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8302 -> 8289 bytes tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8298 -> 8285 bytes tests/data/acpi/x86/q35/DSDT.numamem | Bin 8446 -> 8433 bytes tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8541 -> 8528 bytes tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 9046 -> 9033 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 9072 -> 9059 bytes tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18674 -> 18661 bytes tests/data/acpi/x86/q35/DSDT.viot | Bin 14697 -> 14684 bytes tests/data/acpi/x86/q35/DSDT.xapic | Bin 35803 -> 35790 bytes tests/qtest/test-x86-cpuid-compat.c | 11 - 96 files changed, 359 insertions(+), 1264 deletions(-) delete mode 100644 hw/acpi/cpu_hotplug.c delete mode 100644 include/hw/acpi/cpu_hotplug.h delete mode 100644 pc-bios/multiboot.bin delete mode 100644 pc-bios/optionrom/linuxboot.S delete mode 100644 pc-bios/optionrom/multiboot.S -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/pc_piix.c | 14 -------------- hw/i386/pc_q35.c | 14 -------------- 2 files changed, 28 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7b3611e973cd..4628d491d5b5 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -733,20 +733,6 @@ static void pc_i440fx_machine_2_7_options(MachineClass *m) DEFINE_I440FX_MACHINE(2, 7); -static void pc_i440fx_machine_2_6_options(MachineClass *m) -{ - X86MachineClass *x86mc = X86_MACHINE_CLASS(m); - PCMachineClass *pcmc = PC_MACHINE_CLASS(m); - - pc_i440fx_machine_2_7_options(m); - pcmc->legacy_cpu_hotplug = true; - x86mc->fwcfg_dma_enabled = false; - compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); - compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); -} - -DEFINE_I440FX_MACHINE(2, 6); - #ifdef CONFIG_XEN static void xenfv_machine_4_2_options(MachineClass *m) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 6015e639d7bc..0ae19eb9f1e4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -681,17 +681,3 @@ static void pc_q35_machine_2_7_options(MachineClass *m) } DEFINE_Q35_MACHINE(2, 7); - -static void pc_q35_machine_2_6_options(MachineClass *m) -{ - X86MachineClass *x86mc = X86_MACHINE_CLASS(m); - PCMachineClass *pcmc = PC_MACHINE_CLASS(m); - - pc_q35_machine_2_7_options(m); - pcmc->legacy_cpu_hotplug = true; - x86mc->fwcfg_dma_enabled = false; - compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); - compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); -} - -DEFINE_Q35_MACHINE(2, 6); -- 2.34.1
On Wed, 3 Dec 2025 00:28:08 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/i386/pc_piix.c | 14 -------------- hw/i386/pc_q35.c | 14 -------------- 2 files changed, 28 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7b3611e973cd..4628d491d5b5 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -733,20 +733,6 @@ static void pc_i440fx_machine_2_7_options(MachineClass *m)
DEFINE_I440FX_MACHINE(2, 7);
-static void pc_i440fx_machine_2_6_options(MachineClass *m) -{ - X86MachineClass *x86mc = X86_MACHINE_CLASS(m); - PCMachineClass *pcmc = PC_MACHINE_CLASS(m); - - pc_i440fx_machine_2_7_options(m); - pcmc->legacy_cpu_hotplug = true; - x86mc->fwcfg_dma_enabled = false; - compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); - compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); -} - -DEFINE_I440FX_MACHINE(2, 6); - #ifdef CONFIG_XEN static void xenfv_machine_4_2_options(MachineClass *m) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 6015e639d7bc..0ae19eb9f1e4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -681,17 +681,3 @@ static void pc_q35_machine_2_7_options(MachineClass *m) }
DEFINE_Q35_MACHINE(2, 7); - -static void pc_q35_machine_2_6_options(MachineClass *m) -{ - X86MachineClass *x86mc = X86_MACHINE_CLASS(m); - PCMachineClass *pcmc = PC_MACHINE_CLASS(m); - - pc_q35_machine_2_7_options(m); - pcmc->legacy_cpu_hotplug = true; - x86mc->fwcfg_dma_enabled = false; - compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); - compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); -} - -DEFINE_Q35_MACHINE(2, 6);
From: Igor Mammedov <imammedo@redhat.com> Before dropping legacy CPU hotplug code, mark and allow the affected ACPI tables, to avoid breaking ACPI table testing. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch split off from Igor's v5 [*]. [*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- tests/qtest/bios-tables-test-allowed-diff.h | 42 +++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf4..eed8ded69335 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,43 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/x86/pc/DSDT", +"tests/data/acpi/x86/pc/DSDT.bridge", +"tests/data/acpi/x86/pc/DSDT.ipmikcs", +"tests/data/acpi/x86/pc/DSDT.cphp", +"tests/data/acpi/x86/pc/DSDT.numamem", +"tests/data/acpi/x86/pc/DSDT.nohpet", +"tests/data/acpi/x86/pc/DSDT.memhp", +"tests/data/acpi/x86/pc/DSDT.dimmpxm", +"tests/data/acpi/x86/pc/DSDT.acpihmat", +"tests/data/acpi/x86/pc/DSDT.acpierst", +"tests/data/acpi/x86/pc/DSDT.roothp", +"tests/data/acpi/x86/pc/DSDT.hpbridge", +"tests/data/acpi/x86/pc/DSDT.hpbrroot", +"tests/data/acpi/x86/q35/DSDT", +"tests/data/acpi/x86/q35/DSDT.tis.tpm2", +"tests/data/acpi/x86/q35/DSDT.tis.tpm12", +"tests/data/acpi/x86/q35/DSDT.bridge", +"tests/data/acpi/x86/q35/DSDT.noacpihp", +"tests/data/acpi/x86/q35/DSDT.multi-bridge", +"tests/data/acpi/x86/q35/DSDT.ipmibt", +"tests/data/acpi/x86/q35/DSDT.cphp", +"tests/data/acpi/x86/q35/DSDT.numamem", +"tests/data/acpi/x86/q35/DSDT.nohpet", +"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator", +"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x", +"tests/data/acpi/x86/q35/DSDT.memhp", +"tests/data/acpi/x86/q35/DSDT.dimmpxm", +"tests/data/acpi/x86/q35/DSDT.acpihmat", +"tests/data/acpi/x86/q35/DSDT.mmio64", +"tests/data/acpi/x86/q35/DSDT.acpierst", +"tests/data/acpi/x86/q35/DSDT.applesmc", +"tests/data/acpi/x86/q35/DSDT.pvpanic-isa", +"tests/data/acpi/x86/q35/DSDT.ivrs", +"tests/data/acpi/x86/q35/DSDT.type4-count", +"tests/data/acpi/x86/q35/DSDT.core-count", +"tests/data/acpi/x86/q35/DSDT.core-count2", +"tests/data/acpi/x86/q35/DSDT.thread-count", +"tests/data/acpi/x86/q35/DSDT.thread-count2", +"tests/data/acpi/x86/q35/DSDT.viot", +"tests/data/acpi/x86/q35/DSDT.cxl", +"tests/data/acpi/x86/q35/DSDT.ipmismbus", +"tests/data/acpi/x86/q35/DSDT.xapic", -- 2.34.1
From: Igor Mammedov <imammedo@redhat.com> For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type (in commit 679dd1a957df ("pc: use new CPU hotplug interface since 2.7 machine type")). In that way, legacy firmware that doesn't use QEMU generated ACPI tables was able to continue using legacy CPU hotplug interface. While later machine types, with firmware supporting QEMU provided ACPI tables, generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading. Since 2.6 machine type is now gone, and consider that the legacy BIOS (based on QEMU ACPI prior to v2.7) should be no longer in use, previous compatibility requirements are no longer necessary. So initialize 'modern' hotplug directly from the very beginning for PC/Q35 machines with cpu_hotplug_hw_init(), and drop _INIT method. Additionally, remove the checks and settings around cpu_hotplug_legacy in cpuhp VMState (for piix4 & ich9), to eliminate the risk of segmentation faults, as gpe_cpu no longer has the opportunity to be initialized. This is safe because all hotplug now start with the modern way, and it's impossible to switch to legacy way at runtime (even the "cpu-hotplug-legacy" properties does not allow it either). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch split off from Igor's v5 [*]. [*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/cpu.c | 10 ---------- hw/acpi/ich9.c | 22 +++------------------- hw/acpi/piix4.c | 21 +++------------------ hw/i386/acpi-build.c | 2 +- hw/loongarch/virt-acpi-build.c | 1 - include/hw/acpi/cpu.h | 1 - 6 files changed, 7 insertions(+), 50 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 6f1ae79edbf3..d63ca83c1bcd 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -408,16 +408,6 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(field, aml_reserved_field(4 * 8)); aml_append(field, aml_named_field(CPU_DATA, 32)); aml_append(cpu_ctrl_dev, field); - - if (opts.has_legacy_cphp) { - method = aml_method("_INI", 0, AML_SERIALIZED); - /* switch off legacy CPU hotplug HW and use new one, - * on reboot system is in new mode and writing 0 - * in CPU_SELECTOR selects BSP, which is NOP at - * the time _INI is called */ - aml_append(method, aml_store(zero, aml_name(CPU_SELECTOR))); - aml_append(cpu_ctrl_dev, method); - } } aml_append(sb_scope, cpu_ctrl_dev); diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 2b3b493c014b..54590129c695 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -183,26 +183,10 @@ static const VMStateDescription vmstate_tco_io_state = { } }; -static bool vmstate_test_use_cpuhp(void *opaque) -{ - ICH9LPCPMRegs *s = opaque; - return !s->cpu_hotplug_legacy; -} - -static int vmstate_cpuhp_pre_load(void *opaque) -{ - ICH9LPCPMRegs *s = opaque; - Object *obj = OBJECT(s->gpe_cpu.device); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); - return 0; -} - static const VMStateDescription vmstate_cpuhp_state = { .name = "ich9_pm/cpuhp", .version_id = 1, .minimum_version_id = 1, - .needed = vmstate_test_use_cpuhp, - .pre_load = vmstate_cpuhp_pre_load, .fields = (const VMStateField[]) { VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs), VMSTATE_END_OF_LIST() @@ -338,8 +322,8 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq) pm->powerdown_notifier.notify = pm_powerdown_req; qemu_register_powerdown_notifier(&pm->powerdown_notifier); - legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), - OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); + cpu_hotplug_hw_init(pci_address_space_io(lpc_pci), + OBJECT(lpc_pci), &pm->cpuhp_state, ICH9_CPU_HOTPLUG_IO_BASE); acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), &pm->acpi_memory_hotplug, @@ -419,7 +403,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) { static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; pm->acpi_memory_hotplug.is_enabled = true; - pm->cpu_hotplug_legacy = true; + pm->cpu_hotplug_legacy = false; pm->disable_s3 = 0; pm->disable_s4 = 0; pm->s4_val = 2; diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 7a18f18dda21..a7a29b0d09a9 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -195,25 +195,10 @@ static const VMStateDescription vmstate_memhp_state = { } }; -static bool vmstate_test_use_cpuhp(void *opaque) -{ - PIIX4PMState *s = opaque; - return !s->cpu_hotplug_legacy; -} - -static int vmstate_cpuhp_pre_load(void *opaque) -{ - Object *obj = OBJECT(opaque); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); - return 0; -} - static const VMStateDescription vmstate_cpuhp_state = { .name = "piix4_pm/cpuhp", .version_id = 1, .minimum_version_id = 1, - .needed = vmstate_test_use_cpuhp, - .pre_load = vmstate_cpuhp_pre_load, .fields = (const VMStateField[]) { VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), VMSTATE_END_OF_LIST() @@ -573,12 +558,12 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); } - s->cpu_hotplug_legacy = true; + s->cpu_hotplug_legacy = false; object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", piix4_get_cpu_hotplug_legacy, piix4_set_cpu_hotplug_legacy); - legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, - PIIX4_CPU_HOTPLUG_IO_BASE); + cpu_hotplug_hw_init(parent, OBJECT(s), &s->cpuhp_state, + PIIX4_CPU_HOTPLUG_IO_BASE); if (s->acpi_memory_hotplug.is_enabled) { acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9446a9f862ca..23147ddc25e7 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -964,7 +964,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); } else { CPUHotplugFeatures opts = { - .acpi_1_compatible = true, .has_legacy_cphp = true, + .acpi_1_compatible = true, .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, .fw_unplugs_cpu = pm->smi_on_cpu_unplug, }; diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index 3694c9827f04..8d01c8e3de87 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -369,7 +369,6 @@ build_la_ged_aml(Aml *dsdt, MachineState *machine) if (event & ACPI_GED_CPU_HOTPLUG_EVT) { opts.acpi_1_compatible = false; - opts.has_legacy_cphp = false; opts.fw_unplugs_cpu = false; opts.smi_path = NULL; diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 32654dc274fd..2cb0ca4f3dce 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -54,7 +54,6 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, typedef struct CPUHotplugFeatures { bool acpi_1_compatible; - bool has_legacy_cphp; bool fw_unplugs_cpu; const char *smi_path; } CPUHotplugFeatures; -- 2.34.1
On Wed, 3 Dec 2025 00:28:10 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Igor Mammedov <imammedo@redhat.com> ^^^ given you resplit original patch, it's better to replace this with you, keeping my SoB is sufficient
For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type (in commit 679dd1a957df ("pc: use new CPU hotplug interface since 2.7 machine type")). In that way, legacy firmware that doesn't use QEMU generated ACPI tables was able to continue using legacy CPU hotplug interface.
While later machine types, with firmware supporting QEMU provided ACPI tables, generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading.
Since 2.6 machine type is now gone, and consider that the legacy BIOS (based on QEMU ACPI prior to v2.7) should be no longer in use, previous compatibility requirements are no longer necessary. So initialize 'modern' hotplug directly from the very beginning for PC/Q35 machines with cpu_hotplug_hw_init(), and drop _INIT method.
Additionally, remove the checks and settings around cpu_hotplug_legacy in cpuhp VMState (for piix4 & ich9), to eliminate the risk of segmentation faults, as gpe_cpu no longer has the opportunity to be initialized. This is safe because all hotplug now start with the modern way, and it's impossible to switch to legacy way at runtime (even the "cpu-hotplug-legacy" properties does not allow it either).
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
tested ping pong cross version (master vs master+this patch) migration with 10.1 machine type, nothing is broken, hence Acked-by: Igor Mammedov <imammedo@redhat.com>
--- Changes since v4: * New patch split off from Igor's v5 [*].
[*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/cpu.c | 10 ---------- hw/acpi/ich9.c | 22 +++------------------- hw/acpi/piix4.c | 21 +++------------------ hw/i386/acpi-build.c | 2 +- hw/loongarch/virt-acpi-build.c | 1 - include/hw/acpi/cpu.h | 1 - 6 files changed, 7 insertions(+), 50 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 6f1ae79edbf3..d63ca83c1bcd 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -408,16 +408,6 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(field, aml_reserved_field(4 * 8)); aml_append(field, aml_named_field(CPU_DATA, 32)); aml_append(cpu_ctrl_dev, field); - - if (opts.has_legacy_cphp) { - method = aml_method("_INI", 0, AML_SERIALIZED); - /* switch off legacy CPU hotplug HW and use new one, - * on reboot system is in new mode and writing 0 - * in CPU_SELECTOR selects BSP, which is NOP at - * the time _INI is called */ - aml_append(method, aml_store(zero, aml_name(CPU_SELECTOR))); - aml_append(cpu_ctrl_dev, method); - } } aml_append(sb_scope, cpu_ctrl_dev);
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 2b3b493c014b..54590129c695 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -183,26 +183,10 @@ static const VMStateDescription vmstate_tco_io_state = { } };
-static bool vmstate_test_use_cpuhp(void *opaque) -{ - ICH9LPCPMRegs *s = opaque; - return !s->cpu_hotplug_legacy; -} - -static int vmstate_cpuhp_pre_load(void *opaque) -{ - ICH9LPCPMRegs *s = opaque; - Object *obj = OBJECT(s->gpe_cpu.device); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); - return 0; -} - static const VMStateDescription vmstate_cpuhp_state = { .name = "ich9_pm/cpuhp", .version_id = 1, .minimum_version_id = 1, - .needed = vmstate_test_use_cpuhp, - .pre_load = vmstate_cpuhp_pre_load, .fields = (const VMStateField[]) { VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs), VMSTATE_END_OF_LIST() @@ -338,8 +322,8 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq) pm->powerdown_notifier.notify = pm_powerdown_req; qemu_register_powerdown_notifier(&pm->powerdown_notifier);
- legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), - OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); + cpu_hotplug_hw_init(pci_address_space_io(lpc_pci), + OBJECT(lpc_pci), &pm->cpuhp_state, ICH9_CPU_HOTPLUG_IO_BASE);
acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), &pm->acpi_memory_hotplug, @@ -419,7 +403,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) { static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; pm->acpi_memory_hotplug.is_enabled = true; - pm->cpu_hotplug_legacy = true; + pm->cpu_hotplug_legacy = false; pm->disable_s3 = 0; pm->disable_s4 = 0; pm->s4_val = 2; diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 7a18f18dda21..a7a29b0d09a9 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -195,25 +195,10 @@ static const VMStateDescription vmstate_memhp_state = { } };
-static bool vmstate_test_use_cpuhp(void *opaque) -{ - PIIX4PMState *s = opaque; - return !s->cpu_hotplug_legacy; -} - -static int vmstate_cpuhp_pre_load(void *opaque) -{ - Object *obj = OBJECT(opaque); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); - return 0; -} - static const VMStateDescription vmstate_cpuhp_state = { .name = "piix4_pm/cpuhp", .version_id = 1, .minimum_version_id = 1, - .needed = vmstate_test_use_cpuhp, - .pre_load = vmstate_cpuhp_pre_load, .fields = (const VMStateField[]) { VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), VMSTATE_END_OF_LIST() @@ -573,12 +558,12 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); }
- s->cpu_hotplug_legacy = true; + s->cpu_hotplug_legacy = false; object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", piix4_get_cpu_hotplug_legacy, piix4_set_cpu_hotplug_legacy); - legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, - PIIX4_CPU_HOTPLUG_IO_BASE); + cpu_hotplug_hw_init(parent, OBJECT(s), &s->cpuhp_state, + PIIX4_CPU_HOTPLUG_IO_BASE);
if (s->acpi_memory_hotplug.is_enabled) { acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9446a9f862ca..23147ddc25e7 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -964,7 +964,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); } else { CPUHotplugFeatures opts = { - .acpi_1_compatible = true, .has_legacy_cphp = true, + .acpi_1_compatible = true, .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, .fw_unplugs_cpu = pm->smi_on_cpu_unplug, }; diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index 3694c9827f04..8d01c8e3de87 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -369,7 +369,6 @@ build_la_ged_aml(Aml *dsdt, MachineState *machine)
if (event & ACPI_GED_CPU_HOTPLUG_EVT) { opts.acpi_1_compatible = false; - opts.has_legacy_cphp = false; opts.fw_unplugs_cpu = false; opts.smi_path = NULL;
diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 32654dc274fd..2cb0ca4f3dce 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -54,7 +54,6 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
typedef struct CPUHotplugFeatures { bool acpi_1_compatible; - bool has_legacy_cphp; bool fw_unplugs_cpu; const char *smi_path; } CPUHotplugFeatures;
On Wed, Dec 17, 2025 at 02:32:37PM +0100, Igor Mammedov wrote:
Date: Wed, 17 Dec 2025 14:32:37 +0100 From: Igor Mammedov <imammedo@redhat.com> Subject: Re: [PATCH v5 03/28] pc: Start with modern CPU hotplug interface by default X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu)
On Wed, 3 Dec 2025 00:28:10 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Igor Mammedov <imammedo@redhat.com> ^^^ given you resplit original patch, it's better to replace this with you, keeping my SoB is sufficient
Thank you! Will re-organize these signatures
For compatibility reasons PC/Q35 will start with legacy CPU hotplug interface by default but with new CPU hotplug AML code since 2.7 machine type (in commit 679dd1a957df ("pc: use new CPU hotplug interface since 2.7 machine type")). In that way, legacy firmware that doesn't use QEMU generated ACPI tables was able to continue using legacy CPU hotplug interface.
While later machine types, with firmware supporting QEMU provided ACPI tables, generate new CPU hotplug AML, which will switch to new CPU hotplug interface when guest OS executes its _INI method on ACPI tables loading.
Since 2.6 machine type is now gone, and consider that the legacy BIOS (based on QEMU ACPI prior to v2.7) should be no longer in use, previous compatibility requirements are no longer necessary. So initialize 'modern' hotplug directly from the very beginning for PC/Q35 machines with cpu_hotplug_hw_init(), and drop _INIT method.
Additionally, remove the checks and settings around cpu_hotplug_legacy in cpuhp VMState (for piix4 & ich9), to eliminate the risk of segmentation faults, as gpe_cpu no longer has the opportunity to be initialized. This is safe because all hotplug now start with the modern way, and it's impossible to switch to legacy way at runtime (even the "cpu-hotplug-legacy" properties does not allow it either).
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
tested ping pong cross version (master vs master+this patch) migration with 10.1 machine type, nothing is broken, hence
Acked-by: Igor Mammedov <imammedo@redhat.com>
Thanks for your test and review! Regards, Zhao
From: Philippe Mathieu-Daudé <philmd@linaro.org> Now all PC & Q35 machiens are using modern hotplug from the beginning, and all legacy_cpu_hotplug flags keep false during runtime. So it's safe to remove legacy_cpu_hotplug flags and related properties, with unused gpe_cpu field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Referring Igor's v5 [*], drop gpe_cpu field and does not only remove build_legacy_cpu_hotplug_aml(), but instead remove the entire cpu_hotplug.c file in a separate patch. [*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/ich9.c | 40 ++++------------------------------------ hw/acpi/piix4.c | 40 ++++------------------------------------ hw/i386/acpi-build.c | 4 +--- include/hw/acpi/ich9.h | 2 -- include/hw/acpi/piix4.h | 2 -- include/hw/i386/pc.h | 3 --- 6 files changed, 9 insertions(+), 82 deletions(-) diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 54590129c695..f254f3879716 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -339,26 +339,6 @@ static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name, visit_type_uint32(v, name, &value, errp); } -static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp) -{ - ICH9LPCState *s = ICH9_LPC_DEVICE(obj); - - return s->pm.cpu_hotplug_legacy; -} - -static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value, - Error **errp) -{ - ICH9LPCState *s = ICH9_LPC_DEVICE(obj); - - assert(!value); - if (s->pm.cpu_hotplug_legacy && value == false) { - acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state, - ICH9_CPU_HOTPLUG_IO_BASE); - } - s->pm.cpu_hotplug_legacy = value; -} - static bool ich9_pm_get_enable_tco(Object *obj, Error **errp) { ICH9LPCState *s = ICH9_LPC_DEVICE(obj); @@ -403,7 +383,6 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) { static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; pm->acpi_memory_hotplug.is_enabled = true; - pm->cpu_hotplug_legacy = false; pm->disable_s3 = 0; pm->disable_s4 = 0; pm->s4_val = 2; @@ -422,9 +401,6 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) NULL, NULL, pm); object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, &gpe0_len, OBJ_PROP_FLAG_READ); - object_property_add_bool(obj, "cpu-hotplug-legacy", - ich9_pm_get_cpu_hotplug_legacy, - ich9_pm_set_cpu_hotplug_legacy); object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED, &pm->disable_s3, OBJ_PROP_FLAG_READWRITE); object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED, @@ -477,11 +453,7 @@ void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, dev, errp); } } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { - if (lpc->pm.cpu_hotplug_legacy) { - legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp); - } else { - acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); - } + acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, dev, errp); @@ -500,8 +472,7 @@ void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev, acpi_memory_unplug_request_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !lpc->pm.cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { uint64_t negotiated = lpc->smi_negotiated_features; if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && @@ -533,8 +504,7 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !lpc->pm.cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, @@ -556,7 +526,5 @@ void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) ICH9LPCState *s = ICH9_LPC_DEVICE(adev); acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list); - if (!s->pm.cpu_hotplug_legacy) { - acpi_cpu_ospm_status(&s->pm.cpuhp_state, list); - } + acpi_cpu_ospm_status(&s->pm.cpuhp_state, list); } diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index a7a29b0d09a9..6ad5f1d1c19d 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -336,11 +336,7 @@ static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { - if (s->cpu_hotplug_legacy) { - legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); - } else { - acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); - } + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); } else { g_assert_not_reached(); } @@ -358,8 +354,7 @@ static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !s->cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); } else { error_setg(errp, "acpi: device unplug request for not supported device" @@ -378,8 +373,7 @@ static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !s->cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); } else { error_setg(errp, "acpi: device unplug for not supported device" @@ -523,26 +517,6 @@ static const MemoryRegionOps piix4_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; - -static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) -{ - PIIX4PMState *s = PIIX4_PM(obj); - - return s->cpu_hotplug_legacy; -} - -static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) -{ - PIIX4PMState *s = PIIX4_PM(obj); - - assert(!value); - if (s->cpu_hotplug_legacy && value == false) { - acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, - PIIX4_CPU_HOTPLUG_IO_BASE); - } - s->cpu_hotplug_legacy = value; -} - static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s) { @@ -558,10 +532,6 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); } - s->cpu_hotplug_legacy = false; - object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", - piix4_get_cpu_hotplug_legacy, - piix4_set_cpu_hotplug_legacy); cpu_hotplug_hw_init(parent, OBJECT(s), &s->cpuhp_state, PIIX4_CPU_HOTPLUG_IO_BASE); @@ -576,9 +546,7 @@ static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) PIIX4PMState *s = PIIX4_PM(adev); acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); - if (!s->cpu_hotplug_legacy) { - acpi_cpu_ospm_status(&s->cpuhp_state, list); - } + acpi_cpu_ospm_status(&s->cpuhp_state, list); } static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 23147ddc25e7..bf7ed2e50837 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -960,9 +960,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, scope); - if (pcmc->legacy_cpu_hotplug) { - build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); - } else { + { CPUHotplugFeatures opts = { .acpi_1_compatible = true, .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 245fe08dc245..6a21472eb32e 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -53,8 +53,6 @@ typedef struct ICH9LPCPMRegs { uint32_t pm_io_base; Notifier powerdown_notifier; - bool cpu_hotplug_legacy; - AcpiCpuHotplug gpe_cpu; CPUHotplugState cpuhp_state; bool keep_pci_slot_hpc; diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h index eb1c122d8069..e075f0cbeaf1 100644 --- a/include/hw/acpi/piix4.h +++ b/include/hw/acpi/piix4.h @@ -63,8 +63,6 @@ struct PIIX4PMState { uint8_t disable_s4; uint8_t s4_val; - bool cpu_hotplug_legacy; - AcpiCpuHotplug gpe_cpu; CPUHotplugState cpuhp_state; MemHotplugState acpi_memory_hotplug; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index e83157ab358f..698e3fb84af0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -110,9 +110,6 @@ struct PCMachineClass { bool enforce_amd_1tb_hole; bool isa_bios_alias; - /* generate legacy CPU hotplug AML */ - bool legacy_cpu_hotplug; - /* use PVH to load kernels that support this feature */ bool pvh_enabled; -- 2.34.1
On Wed, 3 Dec 2025 00:28:11 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Now all PC & Q35 machiens are using modern hotplug from the beginning, and all legacy_cpu_hotplug flags keep false during runtime.
So it's safe to remove legacy_cpu_hotplug flags and related properties, with unused gpe_cpu field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
--- Changes since v4: * Referring Igor's v5 [*], drop gpe_cpu field and does not only remove build_legacy_cpu_hotplug_aml(), but instead remove the entire cpu_hotplug.c file in a separate patch.
[*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/ich9.c | 40 ++++------------------------------------ hw/acpi/piix4.c | 40 ++++------------------------------------ hw/i386/acpi-build.c | 4 +--- include/hw/acpi/ich9.h | 2 -- include/hw/acpi/piix4.h | 2 -- include/hw/i386/pc.h | 3 --- 6 files changed, 9 insertions(+), 82 deletions(-)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 54590129c695..f254f3879716 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -339,26 +339,6 @@ static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name, visit_type_uint32(v, name, &value, errp); }
-static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp) -{ - ICH9LPCState *s = ICH9_LPC_DEVICE(obj); - - return s->pm.cpu_hotplug_legacy; -} - -static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value, - Error **errp) -{ - ICH9LPCState *s = ICH9_LPC_DEVICE(obj); - - assert(!value); - if (s->pm.cpu_hotplug_legacy && value == false) { - acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state, - ICH9_CPU_HOTPLUG_IO_BASE); - } - s->pm.cpu_hotplug_legacy = value; -} - static bool ich9_pm_get_enable_tco(Object *obj, Error **errp) { ICH9LPCState *s = ICH9_LPC_DEVICE(obj); @@ -403,7 +383,6 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) { static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; pm->acpi_memory_hotplug.is_enabled = true; - pm->cpu_hotplug_legacy = false; pm->disable_s3 = 0; pm->disable_s4 = 0; pm->s4_val = 2; @@ -422,9 +401,6 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) NULL, NULL, pm); object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, &gpe0_len, OBJ_PROP_FLAG_READ); - object_property_add_bool(obj, "cpu-hotplug-legacy", - ich9_pm_get_cpu_hotplug_legacy, - ich9_pm_set_cpu_hotplug_legacy); object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED, &pm->disable_s3, OBJ_PROP_FLAG_READWRITE); object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED, @@ -477,11 +453,7 @@ void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, dev, errp); } } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { - if (lpc->pm.cpu_hotplug_legacy) { - legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp); - } else { - acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); - } + acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, dev, errp); @@ -500,8 +472,7 @@ void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev, acpi_memory_unplug_request_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !lpc->pm.cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { uint64_t negotiated = lpc->smi_negotiated_features;
if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && @@ -533,8 +504,7 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !lpc->pm.cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, @@ -556,7 +526,5 @@ void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list); - if (!s->pm.cpu_hotplug_legacy) { - acpi_cpu_ospm_status(&s->pm.cpuhp_state, list); - } + acpi_cpu_ospm_status(&s->pm.cpuhp_state, list); } diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index a7a29b0d09a9..6ad5f1d1c19d 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -336,11 +336,7 @@ static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { - if (s->cpu_hotplug_legacy) { - legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); - } else { - acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); - } + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); } else { g_assert_not_reached(); } @@ -358,8 +354,7 @@ static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !s->cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); } else { error_setg(errp, "acpi: device unplug request for not supported device" @@ -378,8 +373,7 @@ static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); - } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && - !s->cpu_hotplug_legacy) { + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); } else { error_setg(errp, "acpi: device unplug for not supported device" @@ -523,26 +517,6 @@ static const MemoryRegionOps piix4_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, };
- -static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) -{ - PIIX4PMState *s = PIIX4_PM(obj); - - return s->cpu_hotplug_legacy; -} - -static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) -{ - PIIX4PMState *s = PIIX4_PM(obj); - - assert(!value); - if (s->cpu_hotplug_legacy && value == false) { - acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, - PIIX4_CPU_HOTPLUG_IO_BASE); - } - s->cpu_hotplug_legacy = value; -} - static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s) { @@ -558,10 +532,6 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); }
- s->cpu_hotplug_legacy = false; - object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", - piix4_get_cpu_hotplug_legacy, - piix4_set_cpu_hotplug_legacy); cpu_hotplug_hw_init(parent, OBJECT(s), &s->cpuhp_state, PIIX4_CPU_HOTPLUG_IO_BASE);
@@ -576,9 +546,7 @@ static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) PIIX4PMState *s = PIIX4_PM(adev);
acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); - if (!s->cpu_hotplug_legacy) { - acpi_cpu_ospm_status(&s->cpuhp_state, list); - } + acpi_cpu_ospm_status(&s->cpuhp_state, list); }
static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 23147ddc25e7..bf7ed2e50837 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -960,9 +960,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, scope);
- if (pcmc->legacy_cpu_hotplug) { - build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); - } else { + { CPUHotplugFeatures opts = { .acpi_1_compatible = true, .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 245fe08dc245..6a21472eb32e 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -53,8 +53,6 @@ typedef struct ICH9LPCPMRegs { uint32_t pm_io_base; Notifier powerdown_notifier;
- bool cpu_hotplug_legacy; - AcpiCpuHotplug gpe_cpu; CPUHotplugState cpuhp_state;
bool keep_pci_slot_hpc; diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h index eb1c122d8069..e075f0cbeaf1 100644 --- a/include/hw/acpi/piix4.h +++ b/include/hw/acpi/piix4.h @@ -63,8 +63,6 @@ struct PIIX4PMState { uint8_t disable_s4; uint8_t s4_val;
- bool cpu_hotplug_legacy; - AcpiCpuHotplug gpe_cpu; CPUHotplugState cpuhp_state;
MemHotplugState acpi_memory_hotplug; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index e83157ab358f..698e3fb84af0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -110,9 +110,6 @@ struct PCMachineClass { bool enforce_amd_1tb_hole; bool isa_bios_alias;
- /* generate legacy CPU hotplug AML */ - bool legacy_cpu_hotplug; - /* use PVH to load kernels that support this feature */ bool pvh_enabled;
From: Igor Mammedov <imammedo@redhat.com> The cpu_hotplug.h and cpu_hotplug.c contain legacy cpu hotplug utilities. Now there's no use case of legacy cpu hotplug, so it's safe to drop legacy cpu hotplug support totally. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch split off from Igor's v5 [*]. [*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/acpi-cpu-hotplug-stub.c | 19 +- hw/acpi/cpu_hotplug.c | 348 -------------------------------- hw/acpi/generic_event_device.c | 1 + hw/acpi/ich9.c | 1 + hw/acpi/meson.build | 2 +- hw/acpi/piix4.c | 2 +- hw/i386/acpi-build.c | 1 + hw/i386/pc.c | 3 +- hw/i386/x86-common.c | 1 - include/hw/acpi/cpu_hotplug.h | 40 ---- include/hw/acpi/ich9.h | 2 +- include/hw/acpi/piix4.h | 2 +- 12 files changed, 10 insertions(+), 412 deletions(-) delete mode 100644 hw/acpi/cpu_hotplug.c delete mode 100644 include/hw/acpi/cpu_hotplug.h diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c index 9872dd55e43f..72c5f05f5c4e 100644 --- a/hw/acpi/acpi-cpu-hotplug-stub.c +++ b/hw/acpi/acpi-cpu-hotplug-stub.c @@ -1,22 +1,10 @@ #include "qemu/osdep.h" -#include "hw/acpi/cpu_hotplug.h" #include "migration/vmstate.h" - +#include "hw/acpi/cpu.h" /* Following stubs are all related to ACPI cpu hotplug */ const VMStateDescription vmstate_cpu_hotplug; -void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port) -{ -} - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base) -{ -} - void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, CPUHotplugState *state, hwaddr base_addr) { @@ -31,11 +19,6 @@ void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, { } -void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp) -{ -} - void acpi_cpu_unplug_cb(CPUHotplugState *cpu_st, DeviceState *dev, Error **errp) { diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c deleted file mode 100644 index aa0e1e3efa54..000000000000 --- a/hw/acpi/cpu_hotplug.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * QEMU ACPI hotplug utilities - * - * Copyright (C) 2013 Red Hat Inc - * - * Authors: - * Igor Mammedov <imammedo@redhat.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ -#include "qemu/osdep.h" -#include "hw/acpi/cpu_hotplug.h" -#include "qapi/error.h" -#include "hw/core/cpu.h" -#include "hw/i386/x86.h" -#include "hw/pci/pci_device.h" -#include "qemu/error-report.h" - -#define CPU_EJECT_METHOD "CPEJ" -#define CPU_MAT_METHOD "CPMA" -#define CPU_ON_BITMAP "CPON" -#define CPU_STATUS_METHOD "CPST" -#define CPU_STATUS_MAP "PRS" -#define CPU_SCAN_METHOD "PRSC" - -static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) -{ - AcpiCpuHotplug *cpus = opaque; - uint64_t val = cpus->sts[addr]; - - return val; -} - -static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, - unsigned int size) -{ - /* firmware never used to write in CPU present bitmap so use - this fact as means to switch QEMU into modern CPU hotplug - mode by writing 0 at the beginning of legacy CPU bitmap - */ - if (addr == 0 && data == 0) { - AcpiCpuHotplug *cpus = opaque; - object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, - &error_abort); - } -} - -static const MemoryRegionOps AcpiCpuHotplug_ops = { - .read = cpu_status_read, - .write = cpu_status_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - }, - .impl = { - .max_access_size = 1, - }, -}; - -static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu, - bool *swtchd_to_modern) -{ - int64_t cpu_id; - - cpu_id = cpu->cc->get_arch_id(cpu); - if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { - object_property_set_bool(g->device, "cpu-hotplug-legacy", false, - &error_abort); - *swtchd_to_modern = true; - return; - } - - *swtchd_to_modern = false; - g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); -} - -void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp) -{ - bool swtchd_to_modern; - Error *local_err = NULL; - - acpi_set_cpu_present_bit(g, CPU(dev), &swtchd_to_modern); - if (swtchd_to_modern) { - /* propagate the hotplug to the modern interface */ - hotplug_handler_plug(hotplug_dev, dev, &local_err); - } else { - acpi_send_event(DEVICE(hotplug_dev), ACPI_CPU_HOTPLUG_STATUS); - } -} - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base) -{ - CPUState *cpu; - bool swtchd_to_modern; - - memory_region_init_io(&gpe_cpu->io, owner, &AcpiCpuHotplug_ops, - gpe_cpu, "acpi-cpu-hotplug", ACPI_GPE_PROC_LEN); - memory_region_add_subregion(parent, base, &gpe_cpu->io); - gpe_cpu->device = owner; - - CPU_FOREACH(cpu) { - acpi_set_cpu_present_bit(gpe_cpu, cpu, &swtchd_to_modern); - } -} - -void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port) -{ - MemoryRegion *parent = pci_address_space_io(PCI_DEVICE(gpe_cpu->device)); - - memory_region_del_subregion(parent, &gpe_cpu->io); - cpu_hotplug_hw_init(parent, gpe_cpu->device, cpuhp_state, io_port); -} - -void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine, - uint16_t io_base) -{ - Aml *dev; - Aml *crs; - Aml *pkg; - Aml *field; - Aml *method; - Aml *if_ctx; - Aml *else_ctx; - int i, apic_idx; - Aml *sb_scope = aml_scope("_SB"); - uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}; - Aml *cpu_id = aml_arg(1); - Aml *apic_id = aml_arg(0); - Aml *cpu_on = aml_local(0); - Aml *madt = aml_local(1); - Aml *cpus_map = aml_name(CPU_ON_BITMAP); - Aml *zero = aml_int(0); - Aml *one = aml_int(1); - MachineClass *mc = MACHINE_GET_CLASS(machine); - const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); - X86MachineState *x86ms = X86_MACHINE(machine); - - /* - * _MAT method - creates an madt apic buffer - * apic_id = Arg0 = Local APIC ID - * cpu_id = Arg1 = Processor ID - * cpu_on = Local0 = CPON flag for this cpu - * madt = Local1 = Buffer (in madt apic form) to return - */ - method = aml_method(CPU_MAT_METHOD, 2, AML_NOTSERIALIZED); - aml_append(method, - aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); - aml_append(method, - aml_store(aml_buffer(sizeof(madt_tmpl), madt_tmpl), madt)); - /* Update the processor id, lapic id, and enable/disable status */ - aml_append(method, aml_store(cpu_id, aml_index(madt, aml_int(2)))); - aml_append(method, aml_store(apic_id, aml_index(madt, aml_int(3)))); - aml_append(method, aml_store(cpu_on, aml_index(madt, aml_int(4)))); - aml_append(method, aml_return(madt)); - aml_append(sb_scope, method); - - /* - * _STA method - return ON status of cpu - * apic_id = Arg0 = Local APIC ID - * cpu_on = Local0 = CPON flag for this cpu - */ - method = aml_method(CPU_STATUS_METHOD, 1, AML_NOTSERIALIZED); - aml_append(method, - aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); - if_ctx = aml_if(cpu_on); - { - aml_append(if_ctx, aml_return(aml_int(0xF))); - } - aml_append(method, if_ctx); - else_ctx = aml_else(); - { - aml_append(else_ctx, aml_return(zero)); - } - aml_append(method, else_ctx); - aml_append(sb_scope, method); - - method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED); - aml_append(method, aml_sleep(200)); - aml_append(sb_scope, method); - - method = aml_method(CPU_SCAN_METHOD, 0, AML_NOTSERIALIZED); - { - Aml *while_ctx, *if_ctx2, *else_ctx2; - Aml *bus_check_evt = aml_int(1); - Aml *remove_evt = aml_int(3); - Aml *status_map = aml_local(5); /* Local5 = active cpu bitmap */ - Aml *byte = aml_local(2); /* Local2 = last read byte from bitmap */ - Aml *idx = aml_local(0); /* Processor ID / APIC ID iterator */ - Aml *is_cpu_on = aml_local(1); /* Local1 = CPON flag for cpu */ - Aml *status = aml_local(3); /* Local3 = active state for cpu */ - - aml_append(method, aml_store(aml_name(CPU_STATUS_MAP), status_map)); - aml_append(method, aml_store(zero, byte)); - aml_append(method, aml_store(zero, idx)); - - /* While (idx < SizeOf(CPON)) */ - while_ctx = aml_while(aml_lless(idx, aml_sizeof(cpus_map))); - aml_append(while_ctx, - aml_store(aml_derefof(aml_index(cpus_map, idx)), is_cpu_on)); - - if_ctx = aml_if(aml_and(idx, aml_int(0x07), NULL)); - { - /* Shift down previously read bitmap byte */ - aml_append(if_ctx, aml_shiftright(byte, one, byte)); - } - aml_append(while_ctx, if_ctx); - - else_ctx = aml_else(); - { - /* Read next byte from cpu bitmap */ - aml_append(else_ctx, aml_store(aml_derefof(aml_index(status_map, - aml_shiftright(idx, aml_int(3), NULL))), byte)); - } - aml_append(while_ctx, else_ctx); - - aml_append(while_ctx, aml_store(aml_and(byte, one, NULL), status)); - if_ctx = aml_if(aml_lnot(aml_equal(is_cpu_on, status))); - { - /* State change - update CPON with new state */ - aml_append(if_ctx, aml_store(status, aml_index(cpus_map, idx))); - if_ctx2 = aml_if(aml_equal(status, one)); - { - aml_append(if_ctx2, - aml_call2(AML_NOTIFY_METHOD, idx, bus_check_evt)); - } - aml_append(if_ctx, if_ctx2); - else_ctx2 = aml_else(); - { - aml_append(else_ctx2, - aml_call2(AML_NOTIFY_METHOD, idx, remove_evt)); - } - } - aml_append(if_ctx, else_ctx2); - aml_append(while_ctx, if_ctx); - - aml_append(while_ctx, aml_increment(idx)); /* go to next cpu */ - aml_append(method, while_ctx); - } - aml_append(sb_scope, method); - - /* The current AML generator can cover the APIC ID range [0..255], - * inclusive, for VCPU hotplug. */ - QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); - if (x86ms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { - error_report("max_cpus is too large. APIC ID of last CPU is %u", - x86ms->apic_id_limit - 1); - exit(1); - } - - /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ - dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); - aml_append(dev, - aml_name_decl("_UID", aml_string("CPU Hotplug resources")) - ); - /* device present, functioning, decoding, not shown in UI */ - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); - crs = aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, io_base, io_base, 1, ACPI_GPE_PROC_LEN) - ); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(sb_scope, dev); - /* declare CPU hotplug MMIO region and PRS field to access it */ - aml_append(sb_scope, aml_operation_region( - "PRST", AML_SYSTEM_IO, aml_int(io_base), ACPI_GPE_PROC_LEN)); - field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); - aml_append(field, aml_named_field("PRS", 256)); - aml_append(sb_scope, field); - - /* build Processor object for each processor */ - for (i = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - assert(cpu_apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); - - dev = aml_processor(i, 0, 0, "CP%.02X", cpu_apic_id); - - method = aml_method("_MAT", 0, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call2(CPU_MAT_METHOD, - aml_int(cpu_apic_id), aml_int(i)) - )); - aml_append(dev, method); - - method = aml_method("_STA", 0, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(cpu_apic_id)))); - aml_append(dev, method); - - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(cpu_apic_id), - aml_arg(0))) - ); - aml_append(dev, method); - - aml_append(sb_scope, dev); - } - - /* build this code: - * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} - */ - /* Arg0 = APIC ID */ - method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); - for (i = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - if_ctx = aml_if(aml_equal(aml_arg(0), aml_int(cpu_apic_id))); - aml_append(if_ctx, - aml_notify(aml_name("CP%.02X", cpu_apic_id), aml_arg(1)) - ); - aml_append(method, if_ctx); - } - aml_append(sb_scope, method); - - /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" - * - * Note: The ability to create variable-sized packages was first - * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages - * ith up to 255 elements. Windows guests up to win2k8 fail when - * VarPackageOp is used. - */ - pkg = x86ms->apic_id_limit <= 255 ? aml_package(x86ms->apic_id_limit) : - aml_varpackage(x86ms->apic_id_limit); - - for (i = 0, apic_idx = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - for (; apic_idx < cpu_apic_id; apic_idx++) { - aml_append(pkg, aml_int(0)); - } - aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0)); - apic_idx = cpu_apic_id + 1; - } - aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); - aml_append(ctx, sb_scope); - - method = aml_method("\\_GPE._E02", 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); - aml_append(ctx, method); -} diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index e7b773d84d50..9d0962d60203 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/acpi/acpi.h" #include "hw/acpi/pcihp.h" +#include "hw/acpi/cpu.h" #include "hw/acpi/generic_event_device.h" #include "hw/pci/pci.h" #include "hw/irq.h" diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index f254f3879716..bbb1bd60a206 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -40,6 +40,7 @@ #include "hw/southbridge/ich9.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" +#include "hw/acpi/pc-hotplug.h" static void ich9_pm_update_sci_fn(ACPIREGS *regs) { diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index 56b5d1ec9691..66c978aae836 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -6,7 +6,7 @@ acpi_ss.add(files( 'core.c', 'utils.c', )) -acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu.c', 'cpu_hotplug.c')) +acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu.c')) acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_false: files('acpi-cpu-hotplug-stub.c')) acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_true: files('memory_hotplug.c')) acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_false: files('acpi-mem-hotplug-stub.c')) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 6ad5f1d1c19d..87a2e4a68247 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -33,7 +33,6 @@ #include "system/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/hotplug.h" #include "hw/mem/pc-dimm.h" @@ -43,6 +42,7 @@ #include "migration/vmstate.h" #include "hw/core/cpu.h" #include "qom/object.h" +#include "hw/acpi/pc-hotplug.h" #define GPE_BASE 0xafe0 #define GPE_LEN 4 diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index bf7ed2e50837..a744eb6c3a9b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -35,6 +35,7 @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu.h" +#include "hw/acpi/pc-hotplug.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/acpi_aml_interface.h" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f8b919cb6c47..2b8d3982c4a0 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -48,7 +48,8 @@ #include "hw/xen/xen.h" #include "qobject/qlist.h" #include "qemu/error-report.h" -#include "hw/acpi/cpu_hotplug.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/pc-hotplug.h" #include "acpi-build.h" #include "hw/mem/nvdimm.h" #include "hw/cxl/cxl_host.h" diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index c844749900a3..60b7ab80433a 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -36,7 +36,6 @@ #include "hw/rtc/mc146818rtc.h" #include "target/i386/sev.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/irq.h" #include "hw/loader.h" #include "multiboot.h" diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h deleted file mode 100644 index 3b932abbbbee..000000000000 --- a/include/hw/acpi/cpu_hotplug.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * QEMU ACPI hotplug utilities - * - * Copyright (C) 2013 Red Hat Inc - * - * Authors: - * Igor Mammedov <imammedo@redhat.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef HW_ACPI_CPU_HOTPLUG_H -#define HW_ACPI_CPU_HOTPLUG_H - -#include "hw/acpi/acpi.h" -#include "hw/acpi/pc-hotplug.h" -#include "hw/acpi/aml-build.h" -#include "hw/hotplug.h" -#include "hw/acpi/cpu.h" - -typedef struct AcpiCpuHotplug { - Object *device; - MemoryRegion io; - uint8_t sts[ACPI_GPE_PROC_LEN]; -} AcpiCpuHotplug; - -void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp); - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base); - -void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port); - -void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine, - uint16_t io_base); -#endif diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 6a21472eb32e..019f0915c110 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -22,12 +22,12 @@ #define HW_ACPI_ICH9_H #include "hw/acpi/acpi.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/acpi/ich9_tco.h" +#include "hw/acpi/cpu.h" #define ACPI_PCIHP_ADDR_ICH9 0x0cc0 diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h index e075f0cbeaf1..863382a814ad 100644 --- a/include/hw/acpi/piix4.h +++ b/include/hw/acpi/piix4.h @@ -24,11 +24,11 @@ #include "hw/pci/pci_device.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/pcihp.h" #include "hw/i2c/pm_smbus.h" #include "hw/isa/apm.h" +#include "hw/acpi/cpu.h" #define TYPE_PIIX4_PM "PIIX4_PM" OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM) -- 2.34.1
On Wed, 3 Dec 2025 00:28:12 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Igor Mammedov <imammedo@redhat.com> ditto see 2/28 comment
The cpu_hotplug.h and cpu_hotplug.c contain legacy cpu hotplug utilities. Now there's no use case of legacy cpu hotplug, so it's safe to drop legacy cpu hotplug support totally.
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
--- Changes since v4: * New patch split off from Igor's v5 [*].
[*]: https://lore.kernel.org/qemu-devel/20251031142825.179239-1-imammedo@redhat.c... --- hw/acpi/acpi-cpu-hotplug-stub.c | 19 +- hw/acpi/cpu_hotplug.c | 348 -------------------------------- hw/acpi/generic_event_device.c | 1 + hw/acpi/ich9.c | 1 + hw/acpi/meson.build | 2 +- hw/acpi/piix4.c | 2 +- hw/i386/acpi-build.c | 1 + hw/i386/pc.c | 3 +- hw/i386/x86-common.c | 1 - include/hw/acpi/cpu_hotplug.h | 40 ---- include/hw/acpi/ich9.h | 2 +- include/hw/acpi/piix4.h | 2 +- 12 files changed, 10 insertions(+), 412 deletions(-) delete mode 100644 hw/acpi/cpu_hotplug.c delete mode 100644 include/hw/acpi/cpu_hotplug.h
diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c index 9872dd55e43f..72c5f05f5c4e 100644 --- a/hw/acpi/acpi-cpu-hotplug-stub.c +++ b/hw/acpi/acpi-cpu-hotplug-stub.c @@ -1,22 +1,10 @@ #include "qemu/osdep.h" -#include "hw/acpi/cpu_hotplug.h" #include "migration/vmstate.h" - +#include "hw/acpi/cpu.h"
/* Following stubs are all related to ACPI cpu hotplug */ const VMStateDescription vmstate_cpu_hotplug;
-void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port) -{ -} - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base) -{ -} - void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, CPUHotplugState *state, hwaddr base_addr) { @@ -31,11 +19,6 @@ void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, { }
-void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp) -{ -} - void acpi_cpu_unplug_cb(CPUHotplugState *cpu_st, DeviceState *dev, Error **errp) { diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c deleted file mode 100644 index aa0e1e3efa54..000000000000 --- a/hw/acpi/cpu_hotplug.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * QEMU ACPI hotplug utilities - * - * Copyright (C) 2013 Red Hat Inc - * - * Authors: - * Igor Mammedov <imammedo@redhat.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ -#include "qemu/osdep.h" -#include "hw/acpi/cpu_hotplug.h" -#include "qapi/error.h" -#include "hw/core/cpu.h" -#include "hw/i386/x86.h" -#include "hw/pci/pci_device.h" -#include "qemu/error-report.h" - -#define CPU_EJECT_METHOD "CPEJ" -#define CPU_MAT_METHOD "CPMA" -#define CPU_ON_BITMAP "CPON" -#define CPU_STATUS_METHOD "CPST" -#define CPU_STATUS_MAP "PRS" -#define CPU_SCAN_METHOD "PRSC" - -static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) -{ - AcpiCpuHotplug *cpus = opaque; - uint64_t val = cpus->sts[addr]; - - return val; -} - -static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, - unsigned int size) -{ - /* firmware never used to write in CPU present bitmap so use - this fact as means to switch QEMU into modern CPU hotplug - mode by writing 0 at the beginning of legacy CPU bitmap - */ - if (addr == 0 && data == 0) { - AcpiCpuHotplug *cpus = opaque; - object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, - &error_abort); - } -} - -static const MemoryRegionOps AcpiCpuHotplug_ops = { - .read = cpu_status_read, - .write = cpu_status_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - }, - .impl = { - .max_access_size = 1, - }, -}; - -static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu, - bool *swtchd_to_modern) -{ - int64_t cpu_id; - - cpu_id = cpu->cc->get_arch_id(cpu); - if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { - object_property_set_bool(g->device, "cpu-hotplug-legacy", false, - &error_abort); - *swtchd_to_modern = true; - return; - } - - *swtchd_to_modern = false; - g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); -} - -void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp) -{ - bool swtchd_to_modern; - Error *local_err = NULL; - - acpi_set_cpu_present_bit(g, CPU(dev), &swtchd_to_modern); - if (swtchd_to_modern) { - /* propagate the hotplug to the modern interface */ - hotplug_handler_plug(hotplug_dev, dev, &local_err); - } else { - acpi_send_event(DEVICE(hotplug_dev), ACPI_CPU_HOTPLUG_STATUS); - } -} - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base) -{ - CPUState *cpu; - bool swtchd_to_modern; - - memory_region_init_io(&gpe_cpu->io, owner, &AcpiCpuHotplug_ops, - gpe_cpu, "acpi-cpu-hotplug", ACPI_GPE_PROC_LEN); - memory_region_add_subregion(parent, base, &gpe_cpu->io); - gpe_cpu->device = owner; - - CPU_FOREACH(cpu) { - acpi_set_cpu_present_bit(gpe_cpu, cpu, &swtchd_to_modern); - } -} - -void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port) -{ - MemoryRegion *parent = pci_address_space_io(PCI_DEVICE(gpe_cpu->device)); - - memory_region_del_subregion(parent, &gpe_cpu->io); - cpu_hotplug_hw_init(parent, gpe_cpu->device, cpuhp_state, io_port); -} - -void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine, - uint16_t io_base) -{ - Aml *dev; - Aml *crs; - Aml *pkg; - Aml *field; - Aml *method; - Aml *if_ctx; - Aml *else_ctx; - int i, apic_idx; - Aml *sb_scope = aml_scope("_SB"); - uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}; - Aml *cpu_id = aml_arg(1); - Aml *apic_id = aml_arg(0); - Aml *cpu_on = aml_local(0); - Aml *madt = aml_local(1); - Aml *cpus_map = aml_name(CPU_ON_BITMAP); - Aml *zero = aml_int(0); - Aml *one = aml_int(1); - MachineClass *mc = MACHINE_GET_CLASS(machine); - const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); - X86MachineState *x86ms = X86_MACHINE(machine); - - /* - * _MAT method - creates an madt apic buffer - * apic_id = Arg0 = Local APIC ID - * cpu_id = Arg1 = Processor ID - * cpu_on = Local0 = CPON flag for this cpu - * madt = Local1 = Buffer (in madt apic form) to return - */ - method = aml_method(CPU_MAT_METHOD, 2, AML_NOTSERIALIZED); - aml_append(method, - aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); - aml_append(method, - aml_store(aml_buffer(sizeof(madt_tmpl), madt_tmpl), madt)); - /* Update the processor id, lapic id, and enable/disable status */ - aml_append(method, aml_store(cpu_id, aml_index(madt, aml_int(2)))); - aml_append(method, aml_store(apic_id, aml_index(madt, aml_int(3)))); - aml_append(method, aml_store(cpu_on, aml_index(madt, aml_int(4)))); - aml_append(method, aml_return(madt)); - aml_append(sb_scope, method); - - /* - * _STA method - return ON status of cpu - * apic_id = Arg0 = Local APIC ID - * cpu_on = Local0 = CPON flag for this cpu - */ - method = aml_method(CPU_STATUS_METHOD, 1, AML_NOTSERIALIZED); - aml_append(method, - aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); - if_ctx = aml_if(cpu_on); - { - aml_append(if_ctx, aml_return(aml_int(0xF))); - } - aml_append(method, if_ctx); - else_ctx = aml_else(); - { - aml_append(else_ctx, aml_return(zero)); - } - aml_append(method, else_ctx); - aml_append(sb_scope, method); - - method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED); - aml_append(method, aml_sleep(200)); - aml_append(sb_scope, method); - - method = aml_method(CPU_SCAN_METHOD, 0, AML_NOTSERIALIZED); - { - Aml *while_ctx, *if_ctx2, *else_ctx2; - Aml *bus_check_evt = aml_int(1); - Aml *remove_evt = aml_int(3); - Aml *status_map = aml_local(5); /* Local5 = active cpu bitmap */ - Aml *byte = aml_local(2); /* Local2 = last read byte from bitmap */ - Aml *idx = aml_local(0); /* Processor ID / APIC ID iterator */ - Aml *is_cpu_on = aml_local(1); /* Local1 = CPON flag for cpu */ - Aml *status = aml_local(3); /* Local3 = active state for cpu */ - - aml_append(method, aml_store(aml_name(CPU_STATUS_MAP), status_map)); - aml_append(method, aml_store(zero, byte)); - aml_append(method, aml_store(zero, idx)); - - /* While (idx < SizeOf(CPON)) */ - while_ctx = aml_while(aml_lless(idx, aml_sizeof(cpus_map))); - aml_append(while_ctx, - aml_store(aml_derefof(aml_index(cpus_map, idx)), is_cpu_on)); - - if_ctx = aml_if(aml_and(idx, aml_int(0x07), NULL)); - { - /* Shift down previously read bitmap byte */ - aml_append(if_ctx, aml_shiftright(byte, one, byte)); - } - aml_append(while_ctx, if_ctx); - - else_ctx = aml_else(); - { - /* Read next byte from cpu bitmap */ - aml_append(else_ctx, aml_store(aml_derefof(aml_index(status_map, - aml_shiftright(idx, aml_int(3), NULL))), byte)); - } - aml_append(while_ctx, else_ctx); - - aml_append(while_ctx, aml_store(aml_and(byte, one, NULL), status)); - if_ctx = aml_if(aml_lnot(aml_equal(is_cpu_on, status))); - { - /* State change - update CPON with new state */ - aml_append(if_ctx, aml_store(status, aml_index(cpus_map, idx))); - if_ctx2 = aml_if(aml_equal(status, one)); - { - aml_append(if_ctx2, - aml_call2(AML_NOTIFY_METHOD, idx, bus_check_evt)); - } - aml_append(if_ctx, if_ctx2); - else_ctx2 = aml_else(); - { - aml_append(else_ctx2, - aml_call2(AML_NOTIFY_METHOD, idx, remove_evt)); - } - } - aml_append(if_ctx, else_ctx2); - aml_append(while_ctx, if_ctx); - - aml_append(while_ctx, aml_increment(idx)); /* go to next cpu */ - aml_append(method, while_ctx); - } - aml_append(sb_scope, method); - - /* The current AML generator can cover the APIC ID range [0..255], - * inclusive, for VCPU hotplug. */ - QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); - if (x86ms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { - error_report("max_cpus is too large. APIC ID of last CPU is %u", - x86ms->apic_id_limit - 1); - exit(1); - } - - /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ - dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); - aml_append(dev, - aml_name_decl("_UID", aml_string("CPU Hotplug resources")) - ); - /* device present, functioning, decoding, not shown in UI */ - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); - crs = aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, io_base, io_base, 1, ACPI_GPE_PROC_LEN) - ); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(sb_scope, dev); - /* declare CPU hotplug MMIO region and PRS field to access it */ - aml_append(sb_scope, aml_operation_region( - "PRST", AML_SYSTEM_IO, aml_int(io_base), ACPI_GPE_PROC_LEN)); - field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); - aml_append(field, aml_named_field("PRS", 256)); - aml_append(sb_scope, field); - - /* build Processor object for each processor */ - for (i = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - assert(cpu_apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); - - dev = aml_processor(i, 0, 0, "CP%.02X", cpu_apic_id); - - method = aml_method("_MAT", 0, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call2(CPU_MAT_METHOD, - aml_int(cpu_apic_id), aml_int(i)) - )); - aml_append(dev, method); - - method = aml_method("_STA", 0, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(cpu_apic_id)))); - aml_append(dev, method); - - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(cpu_apic_id), - aml_arg(0))) - ); - aml_append(dev, method); - - aml_append(sb_scope, dev); - } - - /* build this code: - * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} - */ - /* Arg0 = APIC ID */ - method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); - for (i = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - if_ctx = aml_if(aml_equal(aml_arg(0), aml_int(cpu_apic_id))); - aml_append(if_ctx, - aml_notify(aml_name("CP%.02X", cpu_apic_id), aml_arg(1)) - ); - aml_append(method, if_ctx); - } - aml_append(sb_scope, method); - - /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" - * - * Note: The ability to create variable-sized packages was first - * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages - * ith up to 255 elements. Windows guests up to win2k8 fail when - * VarPackageOp is used. - */ - pkg = x86ms->apic_id_limit <= 255 ? aml_package(x86ms->apic_id_limit) : - aml_varpackage(x86ms->apic_id_limit); - - for (i = 0, apic_idx = 0; i < apic_ids->len; i++) { - int cpu_apic_id = apic_ids->cpus[i].arch_id; - - for (; apic_idx < cpu_apic_id; apic_idx++) { - aml_append(pkg, aml_int(0)); - } - aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0)); - apic_idx = cpu_apic_id + 1; - } - aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); - aml_append(ctx, sb_scope); - - method = aml_method("\\_GPE._E02", 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); - aml_append(ctx, method); -} diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index e7b773d84d50..9d0962d60203 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/acpi/acpi.h" #include "hw/acpi/pcihp.h" +#include "hw/acpi/cpu.h" #include "hw/acpi/generic_event_device.h" #include "hw/pci/pci.h" #include "hw/irq.h" diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index f254f3879716..bbb1bd60a206 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -40,6 +40,7 @@ #include "hw/southbridge/ich9.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" +#include "hw/acpi/pc-hotplug.h"
static void ich9_pm_update_sci_fn(ACPIREGS *regs) { diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index 56b5d1ec9691..66c978aae836 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -6,7 +6,7 @@ acpi_ss.add(files( 'core.c', 'utils.c', )) -acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu.c', 'cpu_hotplug.c')) +acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu.c')) acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_false: files('acpi-cpu-hotplug-stub.c')) acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_true: files('memory_hotplug.c')) acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_false: files('acpi-mem-hotplug-stub.c')) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 6ad5f1d1c19d..87a2e4a68247 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -33,7 +33,6 @@ #include "system/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/hotplug.h" #include "hw/mem/pc-dimm.h" @@ -43,6 +42,7 @@ #include "migration/vmstate.h" #include "hw/core/cpu.h" #include "qom/object.h" +#include "hw/acpi/pc-hotplug.h"
#define GPE_BASE 0xafe0 #define GPE_LEN 4 diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index bf7ed2e50837..a744eb6c3a9b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -35,6 +35,7 @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu.h" +#include "hw/acpi/pc-hotplug.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/acpi_aml_interface.h" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f8b919cb6c47..2b8d3982c4a0 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -48,7 +48,8 @@ #include "hw/xen/xen.h" #include "qobject/qlist.h" #include "qemu/error-report.h" -#include "hw/acpi/cpu_hotplug.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/pc-hotplug.h" #include "acpi-build.h" #include "hw/mem/nvdimm.h" #include "hw/cxl/cxl_host.h" diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index c844749900a3..60b7ab80433a 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -36,7 +36,6 @@ #include "hw/rtc/mc146818rtc.h" #include "target/i386/sev.h"
-#include "hw/acpi/cpu_hotplug.h" #include "hw/irq.h" #include "hw/loader.h" #include "multiboot.h" diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h deleted file mode 100644 index 3b932abbbbee..000000000000 --- a/include/hw/acpi/cpu_hotplug.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * QEMU ACPI hotplug utilities - * - * Copyright (C) 2013 Red Hat Inc - * - * Authors: - * Igor Mammedov <imammedo@redhat.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef HW_ACPI_CPU_HOTPLUG_H -#define HW_ACPI_CPU_HOTPLUG_H - -#include "hw/acpi/acpi.h" -#include "hw/acpi/pc-hotplug.h" -#include "hw/acpi/aml-build.h" -#include "hw/hotplug.h" -#include "hw/acpi/cpu.h" - -typedef struct AcpiCpuHotplug { - Object *device; - MemoryRegion io; - uint8_t sts[ACPI_GPE_PROC_LEN]; -} AcpiCpuHotplug; - -void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, - AcpiCpuHotplug *g, DeviceState *dev, Error **errp); - -void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, - AcpiCpuHotplug *gpe_cpu, uint16_t base); - -void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, - CPUHotplugState *cpuhp_state, - uint16_t io_port); - -void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine, - uint16_t io_base); -#endif diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 6a21472eb32e..019f0915c110 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -22,12 +22,12 @@ #define HW_ACPI_ICH9_H
#include "hw/acpi/acpi.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/acpi/ich9_tco.h" +#include "hw/acpi/cpu.h"
#define ACPI_PCIHP_ADDR_ICH9 0x0cc0
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h index e075f0cbeaf1..863382a814ad 100644 --- a/include/hw/acpi/piix4.h +++ b/include/hw/acpi/piix4.h @@ -24,11 +24,11 @@
#include "hw/pci/pci_device.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/pcihp.h" #include "hw/i2c/pm_smbus.h" #include "hw/isa/apm.h" +#include "hw/acpi/cpu.h"
#define TYPE_PIIX4_PM "PIIX4_PM" OBJECT_DECLARE_SIMPLE_TYPE(PIIX4PMState, PIIX4_PM)
Legacy cpu hotplug has been removed totally and machines start with modern cpu hotplug interface directly. Therefore, update the documentation to describe current QEMU cpu hotplug logic. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch. --- docs/specs/acpi_cpu_hotplug.rst | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.rst b/docs/specs/acpi_cpu_hotplug.rst index 351057c96761..f49678100044 100644 --- a/docs/specs/acpi_cpu_hotplug.rst +++ b/docs/specs/acpi_cpu_hotplug.rst @@ -8,22 +8,6 @@ ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add and hot-remove events. -Legacy ACPI CPU hotplug interface registers -------------------------------------------- - -CPU present bitmap for: - -- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access) -- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) -- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only. -- The first DWORD in bitmap is used in write mode to switch from legacy - to modern CPU hotplug interface, write 0 into it to do switch. - -QEMU sets corresponding CPU bit on hot-add event and issues SCI -with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler -to notify OS about CPU hot-add events. CPU hot-remove isn't supported. - - Modern ACPI CPU hotplug interface registers ------------------------------------------- @@ -189,20 +173,14 @@ Typical usecases (x86) Detecting and enabling modern CPU hotplug interface ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -QEMU starts with legacy CPU hotplug interface enabled. Detecting and -switching to modern interface is based on the 2 legacy CPU hotplug features: - -#. Writes into CPU bitmap are ignored. -#. CPU bitmap always has bit #0 set, corresponding to boot CPU. - -Use following steps to detect and enable modern CPU hotplug interface: +QEMU starts with modern CPU hotplug interface enabled. Use following steps to +detect modern CPU hotplug interface: -#. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode #. Store 0x0 to the 'CPU selector' register, to ensure valid selector value #. Store 0x0 to the 'Command field' register #. Read the 'Command data 2' register. If read value is 0x0, the modern interface is enabled. - Otherwise legacy or no CPU hotplug interface available + Otherwise no CPU hotplug interface available Get a cpu with pending event ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -- 2.34.1
On Wed, 3 Dec 2025 00:28:13 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
Legacy cpu hotplug has been removed totally and machines start with modern cpu hotplug interface directly.
Therefore, update the documentation to describe current QEMU cpu hotplug logic.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- Changes since v4: * New patch. --- docs/specs/acpi_cpu_hotplug.rst | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-)
diff --git a/docs/specs/acpi_cpu_hotplug.rst b/docs/specs/acpi_cpu_hotplug.rst index 351057c96761..f49678100044 100644 --- a/docs/specs/acpi_cpu_hotplug.rst +++ b/docs/specs/acpi_cpu_hotplug.rst @@ -8,22 +8,6 @@ ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add and hot-remove events.
-Legacy ACPI CPU hotplug interface registers -------------------------------------------- - -CPU present bitmap for: - -- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access) -- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) -- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only. -- The first DWORD in bitmap is used in write mode to switch from legacy - to modern CPU hotplug interface, write 0 into it to do switch. - -QEMU sets corresponding CPU bit on hot-add event and issues SCI -with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler -to notify OS about CPU hot-add events. CPU hot-remove isn't supported. - - Modern ACPI CPU hotplug interface registers -------------------------------------------
@@ -189,20 +173,14 @@ Typical usecases (x86) Detecting and enabling modern CPU hotplug interface ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-QEMU starts with legacy CPU hotplug interface enabled. Detecting and -switching to modern interface is based on the 2 legacy CPU hotplug features: - -#. Writes into CPU bitmap are ignored. -#. CPU bitmap always has bit #0 set, corresponding to boot CPU. - -Use following steps to detect and enable modern CPU hotplug interface: +QEMU starts with modern CPU hotplug interface enabled. Use following steps to +detect modern CPU hotplug interface:
-#. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode #. Store 0x0 to the 'CPU selector' register, to ensure valid selector value #. Store 0x0 to the 'Command field' register #. Read the 'Command data 2' register. If read value is 0x0, the modern interface is enabled. - Otherwise legacy or no CPU hotplug interface available + Otherwise no CPU hotplug interface available
Get a cpu with pending event ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support. Update DSDT tables for pc machine. The following diff changes show only _INIT methods are removed from DSDT tables. * tests/data/acpi/x86/pc/DSDT: --- /tmp/asl-6MNNG3.dsl 2025-11-27 11:35:53.011791359 +0800 +++ /tmp/asl-ENING3.dsl 2025-11-27 11:35:53.004791360 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT, Thu Nov 27 11:35:53 2025 + * Disassembly of /tmp/aml-RMING3, Thu Nov 27 11:35:53 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021A3 (8611) + * Length 0x00002196 (8598) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF0 + * Checksum 0xF7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.acpierst: --- /tmp/asl-0Q9CG3.dsl 2025-11-27 11:36:09.513790743 +0800 +++ /tmp/asl-0A3CG3.dsl 2025-11-27 11:36:09.505790743 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.acpierst, Thu Nov 27 11:36:09 2025 + * Disassembly of /tmp/aml-S72CG3, Thu Nov 27 11:36:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000214A (8522) + * Length 0x0000213D (8509) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x38 + * Checksum 0x3F * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.acpihmat: --- /tmp/asl-5ICTG3.dsl 2025-11-27 11:36:11.803790658 +0800 +++ /tmp/asl-5A4SG3.dsl 2025-11-27 11:36:11.795790658 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.acpihmat, Thu Nov 27 11:36:11 2025 + * Disassembly of /tmp/aml-273SG3, Thu Nov 27 11:36:11 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000026D0 (9936) + * Length 0x000026C3 (9923) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xAD + * Checksum 0xB4 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/pc/DSDT.bridge: --- /tmp/asl-0OWEG3.dsl 2025-11-27 11:35:57.430791194 +0800 +++ /tmp/asl-H2CFG3.dsl 2025-11-27 11:35:57.415791195 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.bridge, Thu Nov 27 11:35:57 2025 + * Disassembly of /tmp/aml-P89EG3, Thu Nov 27 11:35:57 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003C7A (15482) + * Length 0x00003C6D (15469) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFE + * Checksum 0x05 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.cphp: --- /tmp/asl-Z59FG3.dsl 2025-11-27 11:36:01.356791048 +0800 +++ /tmp/asl-UVSGG3.dsl 2025-11-27 11:36:01.348791048 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.cphp, Thu Nov 27 11:36:01 2025 + * Disassembly of /tmp/aml-JUSGG3, Thu Nov 27 11:36:01 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002373 (9075) + * Length 0x00002366 (9062) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x63 + * Checksum 0x6A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/pc/DSDT.dimmpxm: --- /tmp/asl-87HXG3.dsl 2025-11-27 11:36:10.604790702 +0800 +++ /tmp/asl-GXDXG3.dsl 2025-11-27 11:36:10.597790703 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.dimmpxm, Thu Nov 27 11:36:10 2025 + * Disassembly of /tmp/aml-8TDXG3, Thu Nov 27 11:36:10 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002819 (10265) + * Length 0x0000280C (10252) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x10 + * Checksum 0x17 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj) Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 @@ -1484,37 +1484,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/pc/DSDT.hpbridge: --- /tmp/asl-85THG3.dsl 2025-11-27 11:36:19.302790377 +0800 +++ /tmp/asl-JXOHG3.dsl 2025-11-27 11:36:19.292790378 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.hpbridge, Thu Nov 27 11:36:19 2025 + * Disassembly of /tmp/aml-7XOHG3, Thu Nov 27 11:36:19 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002172 (8562) + * Length 0x00002165 (8549) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x24 + * Checksum 0x2B * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.hpbrroot: --- /tmp/asl-9C0IG3.dsl 2025-11-27 11:36:17.217790455 +0800 +++ /tmp/asl-P7LJG3.dsl 2025-11-27 11:36:17.213790456 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.hpbrroot, Thu Nov 27 11:36:17 2025 + * Disassembly of /tmp/aml-97LJG3, Thu Nov 27 11:36:17 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000013EC (5100) + * Length 0x000013DF (5087) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x63 + * Checksum 0x6A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1389,37 +1389,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.ipmikcs: --- /tmp/asl-W20MG3.dsl 2025-11-27 11:36:00.052791096 +0800 +++ /tmp/asl-STSMG3.dsl 2025-11-27 11:36:00.041791097 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.ipmikcs, Thu Nov 27 11:36:00 2025 + * Disassembly of /tmp/aml-C1SMG3, Thu Nov 27 11:36:00 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021EB (8683) + * Length 0x000021DE (8670) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x6C + * Checksum 0x73 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.memhp: --- /tmp/asl-X0EDG3.dsl 2025-11-27 11:36:09.487790744 +0800 +++ /tmp/asl-9EXDG3.dsl 2025-11-27 11:36:09.477790744 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.memhp, Thu Nov 27 11:36:09 2025 + * Disassembly of /tmp/aml-PCXDG3, Thu Nov 27 11:36:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000026F2 (9970) + * Length 0x000026E5 (9957) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xC4 + * Checksum 0xCB * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.nohpet: --- /tmp/asl-AY9OG3.dsl 2025-11-27 11:36:07.974790801 +0800 +++ /tmp/asl-Q8PPG3.dsl 2025-11-27 11:36:07.964790801 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.nohpet, Thu Nov 27 11:36:07 2025 + * Disassembly of /tmp/aml-HLQPG3, Thu Nov 27 11:36:07 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002115 (8469) + * Length 0x00002108 (8456) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xB9 + * Checksum 0xC0 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1437,37 +1437,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.numamem: --- /tmp/asl-GVAYG3.dsl 2025-11-27 11:36:02.576791002 +0800 +++ /tmp/asl-856XG3.dsl 2025-11-27 11:36:02.568791002 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.numamem, Thu Nov 27 11:36:02 2025 + * Disassembly of /tmp/aml-926XG3, Thu Nov 27 11:36:02 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021A9 (8617) + * Length 0x0000219C (8604) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7C + * Checksum 0x83 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/pc/DSDT.roothp: --- /tmp/asl-VG4JG3.dsl 2025-11-27 11:36:18.176790420 +0800 +++ /tmp/asl-R0LKG3.dsl 2025-11-27 11:36:18.169790420 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.roothp, Thu Nov 27 11:36:18 2025 + * Disassembly of /tmp/aml-NYLKG3, Thu Nov 27 11:36:18 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003074 (12404) + * Length 0x00003067 (12391) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7C + * Checksum 0x83 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch. --- tests/data/acpi/x86/pc/DSDT | Bin 8611 -> 8598 bytes tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8522 -> 8509 bytes tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9936 -> 9923 bytes tests/data/acpi/x86/pc/DSDT.bridge | Bin 15482 -> 15469 bytes tests/data/acpi/x86/pc/DSDT.cphp | Bin 9075 -> 9062 bytes tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10265 -> 10252 bytes tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8562 -> 8549 bytes tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5100 -> 5087 bytes tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8683 -> 8670 bytes tests/data/acpi/x86/pc/DSDT.memhp | Bin 9970 -> 9957 bytes tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8469 -> 8456 bytes tests/data/acpi/x86/pc/DSDT.numamem | Bin 8617 -> 8604 bytes tests/data/acpi/x86/pc/DSDT.roothp | Bin 12404 -> 12391 bytes tests/qtest/bios-tables-test-allowed-diff.h | 13 ------------- 14 files changed, 13 deletions(-) diff --git a/tests/data/acpi/x86/pc/DSDT b/tests/data/acpi/x86/pc/DSDT index 4beb5194b84a711fcb52e3e52cc2096497d18442..6ea2d36d138daffb59a8636759078500adc58f24 100644 GIT binary patch delta 39 vcmZ4NJk6QQCD<ionj!-O<M)kRr+K(so#KO?;-j0qIVa!enYp=@S55=~{=N*| delta 53 zcmbQ{yx5t`CD<iou_6Nl<A;r0r+K)Xoa2L?;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq??t1OUPD58VI& diff --git a/tests/data/acpi/x86/pc/DSDT.acpierst b/tests/data/acpi/x86/pc/DSDT.acpierst index abda6863b64c5dc8ba5aba1a286cbfa76772a1e4..d8c173aa613f51b1c76ea7b9dee19e899cba240d 100644 GIT binary patch delta 39 vcmX@*wAYEtCD<jzR*`{$(S9S>X&x?Dr}$u}_~<5Y&dK+AW^QifJt_<U?(Yn~ delta 53 zcmdn%bjpd#CD<jzOOb(r(PAUlX&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHZc?3;?HG5552Z diff --git a/tests/data/acpi/x86/pc/DSDT.acpihmat b/tests/data/acpi/x86/pc/DSDT.acpihmat index d081db26d7ba504b3344fad130d5812419291ac0..ba363d6af76af728b7c88bbaf47f7e0ea3dcb41f 100644 GIT binary patch delta 39 vcmccMd)SxDCD<k8uo?pc<CcwFr+K(sJmQ0$;-j0qIVa!enYp=@*IN<*4-pM< delta 53 zcmX@?d%>5>CD<k8f*Jz@<Jyf}r+K&>J>!F&;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq{bQ5&+kc5ODwi diff --git a/tests/data/acpi/x86/pc/DSDT.bridge b/tests/data/acpi/x86/pc/DSDT.bridge index e16897dc5f0fbb3f7b4de8db913884046246cc3b..b68302363cb24181988d6e3dceb04a0946838d5e 100644 GIT binary patch delta 39 vcmexW@wS4?CD<h-*M@<Ck#!^2X&x?Dr}$u}_~<5Y&dK+AW^Qif{i+855Lyl9 delta 53 zcmaD`@vDN%CD<jT%7%e~@!v+S(>z>G&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT*3QQ4*>hl5#|5@ diff --git a/tests/data/acpi/x86/pc/DSDT.cphp b/tests/data/acpi/x86/pc/DSDT.cphp index e95711cd9cde5d50b841b701ae0fed5a4b15e872..20688edf2da41146ece4faa4141517408a42870c 100644 GIT binary patch delta 39 vcmezD_RNjTCD<h-O__m#F>52&X&x@u`1oL__~<5Y&dK+AW^QifeJ2V42kQ;C delta 53 zcmaFn_SucgCD<jTSeb!=F?l1`X&x@8g!o{m_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHbzq3INN05VimS diff --git a/tests/data/acpi/x86/pc/DSDT.dimmpxm b/tests/data/acpi/x86/pc/DSDT.dimmpxm index 90ba66b9164f9a958d5a3c4371b1eec03e922828..8d4be05d2c71ca8de6d732d3e48e0e323143160c 100644 GIT binary patch delta 39 vcmbOk&=bJr66_Mfqrt$yD87;FJ`a~)aD1>+d~}mH=j6{kGdIuVZIA*0-<AwM delta 53 zcmeAPm>Iz366_KpslmX&D6o<1J`b07NPMtUd~}ls*W}MUGkHaL;ywL5ISLq@gI#?# J_wY7I0RWRv4?X|@ diff --git a/tests/data/acpi/x86/pc/DSDT.hpbridge b/tests/data/acpi/x86/pc/DSDT.hpbridge index 0eafe5fbf3d73719c9c3e6e26371863bfb44ed2f..2b5b885b862a2fe8bc4a24446400dccf685dab85 100644 GIT binary patch delta 39 vcmez5^wf#VCD<h-Rgr;#QF|lTX&x?Dr}$u}_~<5Y&dK+AW^QifeJczA{o4&n delta 53 zcmaFr^vQ|KCD<jTNRfeoQDr07X&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHbzu3;?^p5J~_5 diff --git a/tests/data/acpi/x86/pc/DSDT.hpbrroot b/tests/data/acpi/x86/pc/DSDT.hpbrroot index 077a4cc988dc417a1bc9317dddd2dbd96ff1ff50..cc6f26a3f8fe85f34a8acb5432bab3cf4d3ab1f6 100644 GIT binary patch delta 39 vcmaE(eqWu-CD<k8zAys=W7bBl9BwXGr}$u}_~<5Y&dCkjGdHX89AgIn`U?zT delta 53 zcmcbw{zje4CD<k8jW7cPWAa9>9BwWr=lEc!_~<4NuE`DDGkHaL;ywL5ISLq@gI#?# JOY$6J2LQ7!4`2WQ diff --git a/tests/data/acpi/x86/pc/DSDT.ipmikcs b/tests/data/acpi/x86/pc/DSDT.ipmikcs index 8d465f027772f9c59b0c328c1a099e374a6d2a90..052a84e294eee4ecef9a36341493f841caf887a5 100644 GIT binary patch delta 39 vcmaFue9xK7CD<k8o+1MSWAR3=(>z?RPVvD`@zG7*oRjbK%-r0{n<fGP5J?Sr delta 53 zcmccT{MwnzCD<k8wITxpW6nmd(>z>G&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT)~?r0sz<r5P1Lq diff --git a/tests/data/acpi/x86/pc/DSDT.memhp b/tests/data/acpi/x86/pc/DSDT.memhp index e3b49757cb7abd7536ee89a6824967d2cb2485cf..7efc12a46cb87c0684b7d880b2cc94d302744e03 100644 GIT binary patch delta 39 vcmez5`_z}qCD<k8sTu<V<LQlDr+K)%o#KO?;-j0qIVa!enYp=@H&+q>AHfb0 delta 53 zcmaFr`^lHfCD<k8lNtj9<B^SAr+K(Moa2L?;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq>%W5&-Wd5fK0Y diff --git a/tests/data/acpi/x86/pc/DSDT.nohpet b/tests/data/acpi/x86/pc/DSDT.nohpet index 9e772c1316d0ea07c51717466c4c7e383553f345..7eedfcd64ebd0193744864b4f6cbead35c7c3ab2 100644 GIT binary patch delta 39 vcmbR0)ZxVC66_Mfp~%3%cwi%!Ef1HgQ+%*fd~}mH=j1@1nVY}!$cX>|)oKe* delta 53 zcmeBhn(D;m66_Kps>r~=xN{?yEf1HIb9}H<d~}ls*W^H+nY<!A@t%I390d%{!LB}= JU-8I^004Ze4o?68 diff --git a/tests/data/acpi/x86/pc/DSDT.numamem b/tests/data/acpi/x86/pc/DSDT.numamem index 9bfbfc28213713c208dfc38a85abb46fb190871d..910b4952a0757025cfed1c60416d16054e70846f 100644 GIT binary patch delta 39 vcmZ4KJja>KCD<iojv@mCWAjF?(>z?>PVvD`@zG7*oRjbK%-r0{t0Dpb_GAo) delta 53 zcmbQ^ywaJ=CD<ior6L0ZW6egc(>z=r&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT*0d%0syp+4~GB% diff --git a/tests/data/acpi/x86/pc/DSDT.roothp b/tests/data/acpi/x86/pc/DSDT.roothp index efbee6d8aa5c62ff4fcb83e6c5cff59542977850..45d3dbe1b69143a956b4f829913ca47f07134741 100644 GIT binary patch delta 39 vcmey8@H~ObCD<h--GG6Cv3VocX&x?Dr}$u}_~<5Y&dK+AW^QifeXj%n5y%b% delta 53 zcmaE!@FjuECD<jT#DIZ;v1TLJX&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHb#I1OV9F5d;7L diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index eed8ded69335..2ed74f72e7c9 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,17 +1,4 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/x86/pc/DSDT", -"tests/data/acpi/x86/pc/DSDT.bridge", -"tests/data/acpi/x86/pc/DSDT.ipmikcs", -"tests/data/acpi/x86/pc/DSDT.cphp", -"tests/data/acpi/x86/pc/DSDT.numamem", -"tests/data/acpi/x86/pc/DSDT.nohpet", -"tests/data/acpi/x86/pc/DSDT.memhp", -"tests/data/acpi/x86/pc/DSDT.dimmpxm", -"tests/data/acpi/x86/pc/DSDT.acpihmat", -"tests/data/acpi/x86/pc/DSDT.acpierst", -"tests/data/acpi/x86/pc/DSDT.roothp", -"tests/data/acpi/x86/pc/DSDT.hpbridge", -"tests/data/acpi/x86/pc/DSDT.hpbrroot", "tests/data/acpi/x86/q35/DSDT", "tests/data/acpi/x86/q35/DSDT.tis.tpm2", "tests/data/acpi/x86/q35/DSDT.tis.tpm12", -- 2.34.1
On Wed, 3 Dec 2025 00:28:14 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support.
Update DSDT tables for pc machine.
The following diff changes show only _INIT methods are removed from DSDT tables.
below diff in commit message confuses git am, I'd suggests to point out only what's deleted and skip the rest, aka. removed section in x86 DSDTs: - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } ditto for blurb in the next patch
* tests/data/acpi/x86/pc/DSDT:
--- /tmp/asl-6MNNG3.dsl 2025-11-27 11:35:53.011791359 +0800 +++ /tmp/asl-ENING3.dsl 2025-11-27 11:35:53.004791360 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT, Thu Nov 27 11:35:53 2025 + * Disassembly of /tmp/aml-RMING3, Thu Nov 27 11:35:53 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021A3 (8611) + * Length 0x00002196 (8598) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF0 + * Checksum 0xF7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.acpierst:
--- /tmp/asl-0Q9CG3.dsl 2025-11-27 11:36:09.513790743 +0800 +++ /tmp/asl-0A3CG3.dsl 2025-11-27 11:36:09.505790743 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.acpierst, Thu Nov 27 11:36:09 2025 + * Disassembly of /tmp/aml-S72CG3, Thu Nov 27 11:36:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000214A (8522) + * Length 0x0000213D (8509) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x38 + * Checksum 0x3F * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.acpihmat:
--- /tmp/asl-5ICTG3.dsl 2025-11-27 11:36:11.803790658 +0800 +++ /tmp/asl-5A4SG3.dsl 2025-11-27 11:36:11.795790658 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.acpihmat, Thu Nov 27 11:36:11 2025 + * Disassembly of /tmp/aml-273SG3, Thu Nov 27 11:36:11 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000026D0 (9936) + * Length 0x000026C3 (9923) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xAD + * Checksum 0xB4 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/pc/DSDT.bridge:
--- /tmp/asl-0OWEG3.dsl 2025-11-27 11:35:57.430791194 +0800 +++ /tmp/asl-H2CFG3.dsl 2025-11-27 11:35:57.415791195 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.bridge, Thu Nov 27 11:35:57 2025 + * Disassembly of /tmp/aml-P89EG3, Thu Nov 27 11:35:57 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003C7A (15482) + * Length 0x00003C6D (15469) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFE + * Checksum 0x05 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.cphp:
--- /tmp/asl-Z59FG3.dsl 2025-11-27 11:36:01.356791048 +0800 +++ /tmp/asl-UVSGG3.dsl 2025-11-27 11:36:01.348791048 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.cphp, Thu Nov 27 11:36:01 2025 + * Disassembly of /tmp/aml-JUSGG3, Thu Nov 27 11:36:01 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002373 (9075) + * Length 0x00002366 (9062) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x63 + * Checksum 0x6A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/pc/DSDT.dimmpxm:
--- /tmp/asl-87HXG3.dsl 2025-11-27 11:36:10.604790702 +0800 +++ /tmp/asl-GXDXG3.dsl 2025-11-27 11:36:10.597790703 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.dimmpxm, Thu Nov 27 11:36:10 2025 + * Disassembly of /tmp/aml-8TDXG3, Thu Nov 27 11:36:10 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002819 (10265) + * Length 0x0000280C (10252) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x10 + * Checksum 0x17 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj)
Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 @@ -1484,37 +1484,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/pc/DSDT.hpbridge:
--- /tmp/asl-85THG3.dsl 2025-11-27 11:36:19.302790377 +0800 +++ /tmp/asl-JXOHG3.dsl 2025-11-27 11:36:19.292790378 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.hpbridge, Thu Nov 27 11:36:19 2025 + * Disassembly of /tmp/aml-7XOHG3, Thu Nov 27 11:36:19 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002172 (8562) + * Length 0x00002165 (8549) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x24 + * Checksum 0x2B * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.hpbrroot:
--- /tmp/asl-9C0IG3.dsl 2025-11-27 11:36:17.217790455 +0800 +++ /tmp/asl-P7LJG3.dsl 2025-11-27 11:36:17.213790456 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.hpbrroot, Thu Nov 27 11:36:17 2025 + * Disassembly of /tmp/aml-97LJG3, Thu Nov 27 11:36:17 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000013EC (5100) + * Length 0x000013DF (5087) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x63 + * Checksum 0x6A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1389,37 +1389,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.ipmikcs:
--- /tmp/asl-W20MG3.dsl 2025-11-27 11:36:00.052791096 +0800 +++ /tmp/asl-STSMG3.dsl 2025-11-27 11:36:00.041791097 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.ipmikcs, Thu Nov 27 11:36:00 2025 + * Disassembly of /tmp/aml-C1SMG3, Thu Nov 27 11:36:00 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021EB (8683) + * Length 0x000021DE (8670) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x6C + * Checksum 0x73 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.memhp:
--- /tmp/asl-X0EDG3.dsl 2025-11-27 11:36:09.487790744 +0800 +++ /tmp/asl-9EXDG3.dsl 2025-11-27 11:36:09.477790744 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.memhp, Thu Nov 27 11:36:09 2025 + * Disassembly of /tmp/aml-PCXDG3, Thu Nov 27 11:36:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000026F2 (9970) + * Length 0x000026E5 (9957) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xC4 + * Checksum 0xCB * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.nohpet:
--- /tmp/asl-AY9OG3.dsl 2025-11-27 11:36:07.974790801 +0800 +++ /tmp/asl-Q8PPG3.dsl 2025-11-27 11:36:07.964790801 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.nohpet, Thu Nov 27 11:36:07 2025 + * Disassembly of /tmp/aml-HLQPG3, Thu Nov 27 11:36:07 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002115 (8469) + * Length 0x00002108 (8456) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xB9 + * Checksum 0xC0 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1437,37 +1437,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.numamem:
--- /tmp/asl-GVAYG3.dsl 2025-11-27 11:36:02.576791002 +0800 +++ /tmp/asl-856XG3.dsl 2025-11-27 11:36:02.568791002 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.numamem, Thu Nov 27 11:36:02 2025 + * Disassembly of /tmp/aml-926XG3, Thu Nov 27 11:36:02 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000021A9 (8617) + * Length 0x0000219C (8604) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7C + * Checksum 0x83 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/pc/DSDT.roothp:
--- /tmp/asl-VG4JG3.dsl 2025-11-27 11:36:18.176790420 +0800 +++ /tmp/asl-R0LKG3.dsl 2025-11-27 11:36:18.169790420 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/pc/DSDT.roothp, Thu Nov 27 11:36:18 2025 + * Disassembly of /tmp/aml-NYLKG3, Thu Nov 27 11:36:18 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003074 (12404) + * Length 0x00003067 (12391) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7C + * Checksum 0x83 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -1478,37 +1478,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch. --- tests/data/acpi/x86/pc/DSDT | Bin 8611 -> 8598 bytes tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8522 -> 8509 bytes tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9936 -> 9923 bytes tests/data/acpi/x86/pc/DSDT.bridge | Bin 15482 -> 15469 bytes tests/data/acpi/x86/pc/DSDT.cphp | Bin 9075 -> 9062 bytes tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10265 -> 10252 bytes tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8562 -> 8549 bytes tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5100 -> 5087 bytes tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8683 -> 8670 bytes tests/data/acpi/x86/pc/DSDT.memhp | Bin 9970 -> 9957 bytes tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8469 -> 8456 bytes tests/data/acpi/x86/pc/DSDT.numamem | Bin 8617 -> 8604 bytes tests/data/acpi/x86/pc/DSDT.roothp | Bin 12404 -> 12391 bytes tests/qtest/bios-tables-test-allowed-diff.h | 13 ------------- 14 files changed, 13 deletions(-)
diff --git a/tests/data/acpi/x86/pc/DSDT b/tests/data/acpi/x86/pc/DSDT index 4beb5194b84a711fcb52e3e52cc2096497d18442..6ea2d36d138daffb59a8636759078500adc58f24 100644 GIT binary patch delta 39 vcmZ4NJk6QQCD<ionj!-O<M)kRr+K(so#KO?;-j0qIVa!enYp=@S55=~{=N*|
delta 53 zcmbQ{yx5t`CD<iou_6Nl<A;r0r+K)Xoa2L?;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq??t1OUPD58VI&
diff --git a/tests/data/acpi/x86/pc/DSDT.acpierst b/tests/data/acpi/x86/pc/DSDT.acpierst index abda6863b64c5dc8ba5aba1a286cbfa76772a1e4..d8c173aa613f51b1c76ea7b9dee19e899cba240d 100644 GIT binary patch delta 39 vcmX@*wAYEtCD<jzR*`{$(S9S>X&x?Dr}$u}_~<5Y&dK+AW^QifJt_<U?(Yn~
delta 53 zcmdn%bjpd#CD<jzOOb(r(PAUlX&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHZc?3;?HG5552Z
diff --git a/tests/data/acpi/x86/pc/DSDT.acpihmat b/tests/data/acpi/x86/pc/DSDT.acpihmat index d081db26d7ba504b3344fad130d5812419291ac0..ba363d6af76af728b7c88bbaf47f7e0ea3dcb41f 100644 GIT binary patch delta 39 vcmccMd)SxDCD<k8uo?pc<CcwFr+K(sJmQ0$;-j0qIVa!enYp=@*IN<*4-pM<
delta 53 zcmX@?d%>5>CD<k8f*Jz@<Jyf}r+K&>J>!F&;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq{bQ5&+kc5ODwi
diff --git a/tests/data/acpi/x86/pc/DSDT.bridge b/tests/data/acpi/x86/pc/DSDT.bridge index e16897dc5f0fbb3f7b4de8db913884046246cc3b..b68302363cb24181988d6e3dceb04a0946838d5e 100644 GIT binary patch delta 39 vcmexW@wS4?CD<h-*M@<Ck#!^2X&x?Dr}$u}_~<5Y&dK+AW^Qif{i+855Lyl9
delta 53 zcmaD`@vDN%CD<jT%7%e~@!v+S(>z>G&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT*3QQ4*>hl5#|5@
diff --git a/tests/data/acpi/x86/pc/DSDT.cphp b/tests/data/acpi/x86/pc/DSDT.cphp index e95711cd9cde5d50b841b701ae0fed5a4b15e872..20688edf2da41146ece4faa4141517408a42870c 100644 GIT binary patch delta 39 vcmezD_RNjTCD<h-O__m#F>52&X&x@u`1oL__~<5Y&dK+AW^QifeJ2V42kQ;C
delta 53 zcmaFn_SucgCD<jTSeb!=F?l1`X&x@8g!o{m_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHbzq3INN05VimS
diff --git a/tests/data/acpi/x86/pc/DSDT.dimmpxm b/tests/data/acpi/x86/pc/DSDT.dimmpxm index 90ba66b9164f9a958d5a3c4371b1eec03e922828..8d4be05d2c71ca8de6d732d3e48e0e323143160c 100644 GIT binary patch delta 39 vcmbOk&=bJr66_Mfqrt$yD87;FJ`a~)aD1>+d~}mH=j6{kGdIuVZIA*0-<AwM
delta 53 zcmeAPm>Iz366_KpslmX&D6o<1J`b07NPMtUd~}ls*W}MUGkHaL;ywL5ISLq@gI#?# J_wY7I0RWRv4?X|@
diff --git a/tests/data/acpi/x86/pc/DSDT.hpbridge b/tests/data/acpi/x86/pc/DSDT.hpbridge index 0eafe5fbf3d73719c9c3e6e26371863bfb44ed2f..2b5b885b862a2fe8bc4a24446400dccf685dab85 100644 GIT binary patch delta 39 vcmez5^wf#VCD<h-Rgr;#QF|lTX&x?Dr}$u}_~<5Y&dK+AW^QifeJczA{o4&n
delta 53 zcmaFr^vQ|KCD<jTNRfeoQDr07X&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHbzu3;?^p5J~_5
diff --git a/tests/data/acpi/x86/pc/DSDT.hpbrroot b/tests/data/acpi/x86/pc/DSDT.hpbrroot index 077a4cc988dc417a1bc9317dddd2dbd96ff1ff50..cc6f26a3f8fe85f34a8acb5432bab3cf4d3ab1f6 100644 GIT binary patch delta 39 vcmaE(eqWu-CD<k8zAys=W7bBl9BwXGr}$u}_~<5Y&dCkjGdHX89AgIn`U?zT
delta 53 zcmcbw{zje4CD<k8jW7cPWAa9>9BwWr=lEc!_~<4NuE`DDGkHaL;ywL5ISLq@gI#?# JOY$6J2LQ7!4`2WQ
diff --git a/tests/data/acpi/x86/pc/DSDT.ipmikcs b/tests/data/acpi/x86/pc/DSDT.ipmikcs index 8d465f027772f9c59b0c328c1a099e374a6d2a90..052a84e294eee4ecef9a36341493f841caf887a5 100644 GIT binary patch delta 39 vcmaFue9xK7CD<k8o+1MSWAR3=(>z?RPVvD`@zG7*oRjbK%-r0{n<fGP5J?Sr
delta 53 zcmccT{MwnzCD<k8wITxpW6nmd(>z>G&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT)~?r0sz<r5P1Lq
diff --git a/tests/data/acpi/x86/pc/DSDT.memhp b/tests/data/acpi/x86/pc/DSDT.memhp index e3b49757cb7abd7536ee89a6824967d2cb2485cf..7efc12a46cb87c0684b7d880b2cc94d302744e03 100644 GIT binary patch delta 39 vcmez5`_z}qCD<k8sTu<V<LQlDr+K)%o#KO?;-j0qIVa!enYp=@H&+q>AHfb0
delta 53 zcmaFr`^lHfCD<k8lNtj9<B^SAr+K(Moa2L?;-i~9xF+A{naL}{6YuHg$x*=I9PH|| Jxq>%W5&-Wd5fK0Y
diff --git a/tests/data/acpi/x86/pc/DSDT.nohpet b/tests/data/acpi/x86/pc/DSDT.nohpet index 9e772c1316d0ea07c51717466c4c7e383553f345..7eedfcd64ebd0193744864b4f6cbead35c7c3ab2 100644 GIT binary patch delta 39 vcmbR0)ZxVC66_Mfp~%3%cwi%!Ef1HgQ+%*fd~}mH=j1@1nVY}!$cX>|)oKe*
delta 53 zcmeBhn(D;m66_Kps>r~=xN{?yEf1HIb9}H<d~}ls*W^H+nY<!A@t%I390d%{!LB}= JU-8I^004Ze4o?68
diff --git a/tests/data/acpi/x86/pc/DSDT.numamem b/tests/data/acpi/x86/pc/DSDT.numamem index 9bfbfc28213713c208dfc38a85abb46fb190871d..910b4952a0757025cfed1c60416d16054e70846f 100644 GIT binary patch delta 39 vcmZ4KJja>KCD<iojv@mCWAjF?(>z?>PVvD`@zG7*oRjbK%-r0{t0Dpb_GAo)
delta 53 zcmbQ^ywaJ=CD<ior6L0ZW6egc(>z=r&hf!c@zG5lT$Atf%;Xi}iTCvL<S1Zp4tDj~ JT*0d%0syp+4~GB%
diff --git a/tests/data/acpi/x86/pc/DSDT.roothp b/tests/data/acpi/x86/pc/DSDT.roothp index efbee6d8aa5c62ff4fcb83e6c5cff59542977850..45d3dbe1b69143a956b4f829913ca47f07134741 100644 GIT binary patch delta 39 vcmey8@H~ObCD<h--GG6Cv3VocX&x?Dr}$u}_~<5Y&dK+AW^QifeXj%n5y%b%
delta 53 zcmaE!@FjuECD<jT#DIZ;v1TLJX&x>o=lEc!_~<4NuF3a#X7Y;g#C!UAauhH)2fO-g JuHb#I1OV9F5d;7L
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index eed8ded69335..2ed74f72e7c9 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,17 +1,4 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/x86/pc/DSDT", -"tests/data/acpi/x86/pc/DSDT.bridge", -"tests/data/acpi/x86/pc/DSDT.ipmikcs", -"tests/data/acpi/x86/pc/DSDT.cphp", -"tests/data/acpi/x86/pc/DSDT.numamem", -"tests/data/acpi/x86/pc/DSDT.nohpet", -"tests/data/acpi/x86/pc/DSDT.memhp", -"tests/data/acpi/x86/pc/DSDT.dimmpxm", -"tests/data/acpi/x86/pc/DSDT.acpihmat", -"tests/data/acpi/x86/pc/DSDT.acpierst", -"tests/data/acpi/x86/pc/DSDT.roothp", -"tests/data/acpi/x86/pc/DSDT.hpbridge", -"tests/data/acpi/x86/pc/DSDT.hpbrroot", "tests/data/acpi/x86/q35/DSDT", "tests/data/acpi/x86/q35/DSDT.tis.tpm2", "tests/data/acpi/x86/q35/DSDT.tis.tpm12",
On Wed, Dec 17, 2025 at 03:16:27PM +0100, Igor Mammedov wrote:
Date: Wed, 17 Dec 2025 15:16:27 +0100 From: Igor Mammedov <imammedo@redhat.com> Subject: Re: [PATCH v5 07/28] tests/acpi: Update DSDT tables for pc machine X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu)
On Wed, 3 Dec 2025 00:28:14 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support.
Update DSDT tables for pc machine.
The following diff changes show only _INIT methods are removed from DSDT tables.
below diff in commit message confuses git am, I'd suggests to point out only what's deleted and skip the rest, aka. removed section in x86 DSDTs: - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - }
ditto for blurb in the next patch
Yes, good idea. Indeed, this nearly duplicated information makes the commit message quite lengthy, so I had to split it into two patches. Will merge these 2 patches (this patch and next patch). Thanks, Zhao
Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support. Update DSDT tables for q35 machine. The following diff changes show only _INIT methods are removed from DSDT tables. * tests/data/acpi/x86/q35/DSDT: --- /tmp/asl-BSAVG3.dsl 2025-11-27 15:29:29.707267890 +0800 +++ /tmp/asl-WDGVG3.dsl 2025-11-27 15:29:29.700267890 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT, Thu Nov 27 15:29:29 2025 + * Disassembly of /tmp/aml-AFGVG3, Thu Nov 27 15:29:29 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000020F8 (8440) + * Length 0x000020EB (8427) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xBE + * Checksum 0xC5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.acpierst: --- /tmp/asl-5FERG3.dsl 2025-11-27 15:29:23.887268107 +0800 +++ /tmp/asl-PPKRG3.dsl 2025-11-27 15:29:23.881268108 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpierst, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-0QKRG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002109 (8457) + * Length 0x000020FC (8444) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5D + * Checksum 0x65 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.acpihmat: --- /tmp/asl-JRLYG3.dsl 2025-11-27 15:29:21.552268195 +0800 +++ /tmp/asl-QETYG3.dsl 2025-11-27 15:29:21.544268195 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-2FTYG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002625 (9765) + * Length 0x00002618 (9752) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7A + * Checksum 0x81 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x: --- /tmp/asl-38KFG3.dsl 2025-11-27 15:29:14.394268462 +0800 +++ /tmp/asl-9ETFG3.dsl 2025-11-27 15:29:14.384268462 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x, Thu Nov 27 15:29:14 2025 + * Disassembly of /tmp/aml-OHTFG3, Thu Nov 27 15:29:14 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000316A (12650) + * Length 0x0000315D (12637) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x1F + * Checksum 0x35 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator: --- /tmp/asl-N0VHG3.dsl 2025-11-27 15:29:16.287268391 +0800 +++ /tmp/asl-XTAIG3.dsl 2025-11-27 15:29:16.277268392 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator, Thu Nov 27 15:29:16 2025 + * Disassembly of /tmp/aml-1UAIG3, Thu Nov 27 15:29:16 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000220F (8719) + * Length 0x00002202 (8706) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x34 + * Checksum 0x3B * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.applesmc: --- /tmp/asl-XR4EG3.dsl 2025-11-27 15:29:25.412268050 +0800 +++ /tmp/asl-6IBFG3.dsl 2025-11-27 15:29:25.404268051 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.applesmc, Thu Nov 27 15:29:25 2025 + * Disassembly of /tmp/aml-TPBFG3, Thu Nov 27 15:29:25 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002126 (8486) + * Length 0x00002119 (8473) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xAD + * Checksum 0xB4 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.bridge: --- /tmp/asl-7WRVG3.dsl 2025-11-27 15:28:59.686269011 +0800 +++ /tmp/asl-KEYVG3.dsl 2025-11-27 15:28:59.676269012 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.bridge, Thu Nov 27 15:28:59 2025 + * Disassembly of /tmp/aml-NCYVG3, Thu Nov 27 15:28:59 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002F15 (12053) + * Length 0x00002F08 (12040) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xD9 + * Checksum 0xE0 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.core-count: --- /tmp/asl-RENPG3.dsl 2025-11-27 15:29:21.971268179 +0800 +++ /tmp/asl-IGXPG3.dsl 2025-11-27 15:29:21.961268179 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.core-count, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-GPWPG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000032C6 (12998) + * Length 0x000032B9 (12985) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x36 + * Checksum 0x3D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.core-count2: --- /tmp/asl-YGFMG3.dsl 2025-11-27 15:29:23.094268137 +0800 +++ /tmp/asl-SU2MG3.dsl 2025-11-27 15:29:23.063268138 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.core-count2, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-OW2MG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000843F (33855) + * Length 0x00008432 (33842) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.cphp: --- /tmp/asl-SAFWG3.dsl 2025-11-27 15:29:09.652268639 +0800 +++ /tmp/asl-1BJWG3.dsl 2025-11-27 15:29:09.646268639 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.cphp, Thu Nov 27 15:29:09 2025 + * Disassembly of /tmp/aml-JAJWG3, Thu Nov 27 15:29:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000022C8 (8904) + * Length 0x000022BB (8891) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x31 + * Checksum 0x38 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.cxl: --- /tmp/asl-VYSRG3.dsl 2025-11-27 15:29:35.869267660 +0800 +++ /tmp/asl-RAZRG3.dsl 2025-11-27 15:29:35.862267660 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.cxl, Thu Nov 27 15:29:35 2025 + * Disassembly of /tmp/aml-ZBZRG3, Thu Nov 27 15:29:35 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000033AF (13231) + * Length 0x000033A2 (13218) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF2 + * Checksum 0xF9 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.dimmpxm: --- /tmp/asl-A93JG3.dsl 2025-11-27 15:29:20.180268246 +0800 +++ /tmp/asl-CEBKG3.dsl 2025-11-27 15:29:20.172268246 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.dimmpxm, Thu Nov 27 15:29:20 2025 + * Disassembly of /tmp/aml-MFBKG3, Thu Nov 27 15:29:20 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000276E (10094) + * Length 0x00002761 (10081) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xDE + * Checksum 0xE5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj) Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 @@ -2891,37 +2891,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.ipmibt: --- /tmp/asl-SW1YG3.dsl 2025-11-27 15:29:04.532268830 +0800 +++ /tmp/asl-KJQCG3.dsl 2025-11-27 15:29:04.524268831 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ipmibt, Thu Nov 27 15:29:04 2025 + * Disassembly of /tmp/aml-MMQCG3, Thu Nov 27 15:29:04 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002143 (8515) + * Length 0x00002136 (8502) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF1 + * Checksum 0xF8 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.ipmismbus: --- /tmp/asl-5BDMG3.dsl 2025-11-27 15:29:31.075267839 +0800 +++ /tmp/asl-KKIMG3.dsl 2025-11-27 15:29:31.068267839 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ipmismbus, Thu Nov 27 15:29:31 2025 + * Disassembly of /tmp/aml-8LIMG3, Thu Nov 27 15:29:31 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002150 (8528) + * Length 0x00002143 (8515) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x62 + * Checksum 0x69 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.ivrs: --- /tmp/asl-AZ0SG3.dsl 2025-11-27 15:29:27.813267961 +0800 +++ /tmp/asl-QV7SG3.dsl 2025-11-27 15:29:27.804267961 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ivrs, Thu Nov 27 15:29:27 2025 + * Disassembly of /tmp/aml-PU7SG3, Thu Nov 27 15:29:27 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002109 (8457) + * Length 0x000020FC (8444) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5D + * Checksum 0x65 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.memhp: --- /tmp/asl-VVJNG3.dsl 2025-11-27 15:29:19.018268289 +0800 +++ /tmp/asl-EIONG3.dsl 2025-11-27 15:29:19.013268289 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.memhp, Thu Nov 27 15:29:19 2025 + * Disassembly of /tmp/aml-FHONG3, Thu Nov 27 15:29:19 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002647 (9799) + * Length 0x0000263A (9786) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x91 + * Checksum 0x98 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.mmio64: --- /tmp/asl-7NEUG3.dsl 2025-11-27 15:29:22.749268150 +0800 +++ /tmp/asl-FQSUG3.dsl 2025-11-27 15:29:22.741268150 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.mmio64, Thu Nov 27 15:29:22 2025 + * Disassembly of /tmp/aml-WPSUG3, Thu Nov 27 15:29:22 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002562 (9570) + * Length 0x00002555 (9557) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x52 + * Checksum 0x59 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.multi-bridge: --- /tmp/asl-JNDLG3.dsl 2025-11-27 15:29:02.126268920 +0800 +++ /tmp/asl-6QNLG3.dsl 2025-11-27 15:29:02.113268921 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.multi-bridge, Thu Nov 27 15:29:02 2025 + * Disassembly of /tmp/aml-0ONLG3, Thu Nov 27 15:29:02 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000033ED (13293) + * Length 0x000033E0 (13280) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xD3 + * Checksum 0xDA * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.noacpihp: --- /tmp/asl-5PGXG3.dsl 2025-11-27 15:29:04.605268828 +0800 +++ /tmp/asl-WLPXG3.dsl 2025-11-27 15:29:04.597268828 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.noacpihp, Thu Nov 27 15:29:04 2025 + * Disassembly of /tmp/aml-VNPXG3, Thu Nov 27 15:29:04 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000206E (8302) + * Length 0x00002061 (8289) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xA0 + * Checksum 0xA7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2796,37 +2796,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.nohpet: --- /tmp/asl-CF4OG3.dsl 2025-11-27 15:29:14.994268440 +0800 +++ /tmp/asl-KFBPG3.dsl 2025-11-27 15:29:14.987268440 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.nohpet, Thu Nov 27 15:29:14 2025 + * Disassembly of /tmp/aml-QHBPG3, Thu Nov 27 15:29:14 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000206A (8298) + * Length 0x0000205D (8285) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2844,37 +2844,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.numamem: --- /tmp/asl-IPHHG3.dsl 2025-11-27 15:29:07.303268727 +0800 +++ /tmp/asl-67NHG3.dsl 2025-11-27 15:29:07.295268727 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.numamem, Thu Nov 27 15:29:07 2025 + * Disassembly of /tmp/aml-NAOHG3, Thu Nov 27 15:29:07 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000020FE (8446) + * Length 0x000020F1 (8433) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x4A + * Checksum 0x51 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.pvpanic-isa: --- /tmp/asl-WJDHG3.dsl 2025-11-27 15:29:18.306268316 +0800 +++ /tmp/asl-6RHHG3.dsl 2025-11-27 15:29:18.300268316 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.pvpanic-isa, Thu Nov 27 15:29:18 2025 + * Disassembly of /tmp/aml-XUNHG3, Thu Nov 27 15:29:18 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000215D (8541) + * Length 0x00002150 (8528) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x70 + * Checksum 0x77 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.thread-count: --- /tmp/asl-TWDTG3.dsl 2025-11-27 15:29:23.799268111 +0800 +++ /tmp/asl-USNTG3.dsl 2025-11-27 15:29:23.788268111 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.thread-count, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-ASNTG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000032C6 (12998) + * Length 0x000032B9 (12985) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x36 + * Checksum 0x3D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.thread-count2: --- /tmp/asl-I56IG3.dsl 2025-11-27 15:29:25.246268057 +0800 +++ /tmp/asl-Z2YJG3.dsl 2025-11-27 15:29:25.213268058 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.thread-count2, Thu Nov 27 15:29:25 2025 + * Disassembly of /tmp/aml-L4YJG3, Thu Nov 27 15:29:25 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000843F (33855) + * Length 0x00008432 (33842) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.tis.tpm12: --- /tmp/asl-SHLRG3.dsl 2025-11-27 15:29:01.877268929 +0800 +++ /tmp/asl-1LQRG3.dsl 2025-11-27 15:29:01.871268930 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.tis.tpm12, Thu Nov 27 15:29:01 2025 + * Disassembly of /tmp/aml-9MQRG3, Thu Nov 27 15:29:01 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002356 (9046) + * Length 0x00002349 (9033) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xEE + * Checksum 0xF5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.tis.tpm2: --- /tmp/asl-KISFG3.dsl 2025-11-27 15:28:57.380269097 +0800 +++ /tmp/asl-ZIYFG3.dsl 2025-11-27 15:28:57.373269098 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.tis.tpm2, Thu Nov 27 15:28:57 2025 + * Disassembly of /tmp/aml-ZJYFG3, Thu Nov 27 15:28:57 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002370 (9072) + * Length 0x00002363 (9059) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xA8 + * Checksum 0xAF * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.type4-count: --- /tmp/asl-PJ6JG3.dsl 2025-11-27 15:29:21.179268209 +0800 +++ /tmp/asl-GPJKG3.dsl 2025-11-27 15:29:21.168268209 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.type4-count, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-FRJKG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000048F2 (18674) + * Length 0x000048E5 (18661) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x53 + * Checksum 0x5A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) * tests/data/acpi/x86/q35/DSDT.viot: --- /tmp/asl-9POJG3.dsl 2025-11-27 15:29:26.204268021 +0800 +++ /tmp/asl-BEXJG3.dsl 2025-11-27 15:29:26.192268021 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.viot, Thu Nov 27 15:29:26 2025 + * Disassembly of /tmp/aml-YDXJG3, Thu Nov 27 15:29:26 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003969 (14697) + * Length 0x0000395C (14684) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x90 + * Checksum 0x97 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } } Method (CSTA, 1, Serialized) { * tests/data/acpi/x86/q35/DSDT.xapic: --- /tmp/asl-JOGEG3.dsl 2025-11-27 15:29:32.463267787 +0800 +++ /tmp/asl-6UFFG3.dsl 2025-11-27 15:29:32.428267788 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.xapic, Thu Nov 27 15:29:32 2025 + * Disassembly of /tmp/aml-U2EFG3, Thu Nov 27 15:29:32 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00008BDB (35803) + * Length 0x00008BCE (35790) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x83 + * Checksum 0x8A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 } Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } } Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } If ((Arg0 == One)) { Notify (C001, Arg1) Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch. --- tests/data/acpi/x86/q35/DSDT | Bin 8440 -> 8427 bytes tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9765 -> 9752 bytes .../data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12650 -> 12637 bytes .../acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8719 -> 8706 bytes tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8486 -> 8473 bytes tests/data/acpi/x86/q35/DSDT.bridge | Bin 12053 -> 12040 bytes tests/data/acpi/x86/q35/DSDT.core-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.cphp | Bin 8904 -> 8891 bytes tests/data/acpi/x86/q35/DSDT.cxl | Bin 13231 -> 13218 bytes tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10094 -> 10081 bytes tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8515 -> 8502 bytes tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8528 -> 8515 bytes tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.memhp | Bin 9799 -> 9786 bytes tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9570 -> 9557 bytes tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13293 -> 13280 bytes tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8302 -> 8289 bytes tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8298 -> 8285 bytes tests/data/acpi/x86/q35/DSDT.numamem | Bin 8446 -> 8433 bytes tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8541 -> 8528 bytes tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 9046 -> 9033 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 9072 -> 9059 bytes tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18674 -> 18661 bytes tests/data/acpi/x86/q35/DSDT.viot | Bin 14697 -> 14684 bytes tests/data/acpi/x86/q35/DSDT.xapic | Bin 35803 -> 35790 bytes tests/qtest/bios-tables-test-allowed-diff.h | 29 ------------------ 30 files changed, 29 deletions(-) diff --git a/tests/data/acpi/x86/q35/DSDT b/tests/data/acpi/x86/q35/DSDT index e5e8d1e041e20e1b3ee56a5c93fe3d6ebd721ee6..377e880175f6f11101548c0c64da61b5aee00bd9 100644 GIT binary patch delta 39 vcmez2_}Y=nCD<k8wE_bJ<I#;=l9F7mPVvD`@zG7*oRf7WXKubMsmcxj3Rw)V delta 53 zcmaFu_`{LQCD<k8hXMlw<Gzhtl9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|?Nk4gkhs53c|K diff --git a/tests/data/acpi/x86/q35/DSDT.acpierst b/tests/data/acpi/x86/q35/DSDT.acpierst index 072a3fe2cd17dfe06658dfd82588f69787810114..026bfdfebf66c1803f158ac8c115eb5f49b5cb19 100644 GIT binary patch delta 39 vcmeBl`s2vu66_N4M}dKXF?A!Cq$HQCQ+%*fd~}mH=VV>UnVT<5ny~`_^t=od delta 53 zcmez4*y+UO66_MfsmQ><7`u^6Qj*KbIX>7aKDx<+YqGB7OkNS5cuzl1jsgbfU{{~b I$0W_z0eo!^6aWAK diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat b/tests/data/acpi/x86/q35/DSDT.acpihmat index 2a4f2fc1d5c5649673353186e67ff5b5e59e8d53..f1b8483d8da21dd57f3e5e7a1e4eb787df2c38ac 100644 GIT binary patch delta 39 vcmZ4LGsB0=CD<iILXClev2i1pq$HP%M|`kTd~}mH=VV>UnVT<52Jrv@*4zt4 delta 53 zcmbQ?v($&nCD<iIRgHmxv1%iiq$HQ4XMC_zd~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4Xmc004Yz4n+U} diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x b/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x index 7911c058bba5005d318b8db8d6da5c1ee381b0f1..a7731403f460a235bf705770a1547dafeee069ab 100644 GIT binary patch delta 39 vcmaErbT^61CD<h-){udL(R3r1q$HP<Uwp7rd~}mH=VV>UnVT<5P8SCN^mq(Y delta 53 zcmcbc^eTzVCD<h-%aDPAQGO$rq$HQWUwp7rd~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4a7!2LPlJ4^sdD diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator index 580b4a456a20fc0cc0a832eaf74193b46d8ae8b1..cb4995de7e33cd9f2d134ec96651d217873d6944 100644 GIT binary patch delta 39 ucmeBoX>#Fm33dr#Qet3WwBE=iDaqv%93SiyAKm25Iayb7=H|<iHXH!OR0^U1 delta 53 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100644 GIT binary patch delta 40 wcmX?>x-*r_CD<iorx61KqwPj6NlEVJc*gi(r}*e5Z_dejk~247k^Ce900Y(yC;$Ke delta 54 zcmdm)dMuU8CD<k8m=Oa5quE9-NlEU81jhJar}*e553b32k~4Wlc;Y?%JUI#&oP%9` KHXoP#Bmn@rP7o*n diff --git a/tests/data/acpi/x86/q35/DSDT.core-count2 b/tests/data/acpi/x86/q35/DSDT.core-count2 index d0394558a1faa0b4ba43abab66d474d96b477ff3..f460be2bf74ae512db8f24418b42e8cf2a56202d 100644 GIT binary patch delta 42 ycmdnr!L+G^iOVI}CB&$Ofq}7aBbTHkcTX8xe6Uk|bdxvdWIf55o3BV_X8`~d01a>e delta 56 zcmdng!L+}FiOVI}CB(jkfq}7oBbTHkcV{_Ue6Uk|bdv|yWIf55ydpgDo_?Mj1q{x? Mu0ETOOJ-*Q0MS7ZZ~y=R diff --git a/tests/data/acpi/x86/q35/DSDT.cphp b/tests/data/acpi/x86/q35/DSDT.cphp index a055c2e7d3c4f5a00a03be20fd73227e322283a4..7c87d41d03fcfd2b5b82f2581f16de6bc0bb10bf 100644 GIT binary patch delta 39 vcmX@%y4#h@CD<iow-N&bqs2xpNl7l(`1oL__~<5Y&dIuxGdEwB{K^3U?XnDt delta 53 zcmdn(dcu{<CD<k8gc1V-qv1v_Nl7lJg!o{m_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACvsb0RWs;4~hT) diff --git a/tests/data/acpi/x86/q35/DSDT.cxl b/tests/data/acpi/x86/q35/DSDT.cxl index 20843549f54af1cb0e6017c4cfff7463318d9eb7..da86b25f51b550ab20771111cb0a2bc49e713186 100644 GIT binary patch delta 39 vcmZ3Vz9^l`CD<iokud`U<Ijy;l9F7mPVvD`@zG7*oRf7WXKubMc}Efe|Hln5 delta 53 zcmZ3KzCNAHCD<ioy)gp=<EM>Wl9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|=lb5&*aE5HJ7$ diff --git a/tests/data/acpi/x86/q35/DSDT.dimmpxm b/tests/data/acpi/x86/q35/DSDT.dimmpxm index 664e926e90765550136242f7e3e0bdc7719c1853..a2d812e5a23a3ce7739789246b342e703f8c96c0 100644 GIT binary patch delta 39 vcmaFo_t1~aCD<h-QJsN-@##h`T}dv#;P_yt_~<5Y&dH9FGdDk%Z07|41ThT| delta 53 zcmaFp_s);YCD<h-Po05*@!m!*T}dwQkoaJy_~<4NuE~y)GkHaL;ywL5ISLq@gI#?# J-;!+S1pvOk5D)+W diff --git a/tests/data/acpi/x86/q35/DSDT.ipmibt b/tests/data/acpi/x86/q35/DSDT.ipmibt index 4066a76d26aa380dfbecc58aa3f83ab5db2baadb..43ac1bd693d1b3f67d2a9e89ccaf8a56656df22d 100644 GIT binary patch delta 39 vcmX@?w9SdjCD<jzOp$?s@yA9kNl7kOr}$u}_~<5Y&dIuxGdEwBEMNx!>rf04 delta 53 zcmdnybl8c@CD<jzS&@N(@#97=Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACoL#2LPI>4-o(W diff --git a/tests/data/acpi/x86/q35/DSDT.ipmismbus b/tests/data/acpi/x86/q35/DSDT.ipmismbus index 6d0b6b95c2a9fd01befc37b26650781ee1562e2a..1b998820d46e522b3129e42a867ed691c1f83e8f 100644 GIT binary patch delta 39 vcmccMbl8c@CD<jzS&@N(F>@oAq$HQCQ+%*fd~}mH=VV>UnVT<5*0KWt;?)bb delta 53 zcmX@?bis+sCD<h-K#_rgF=->0q$HP<b9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4e_D0|1PE4z>UQ diff --git a/tests/data/acpi/x86/q35/DSDT.ivrs b/tests/data/acpi/x86/q35/DSDT.ivrs index 072a3fe2cd17dfe06658dfd82588f69787810114..026bfdfebf66c1803f158ac8c115eb5f49b5cb19 100644 GIT binary patch delta 39 vcmeBl`s2vu66_N4M}dKXF?A!Cq$HQCQ+%*fd~}mH=VV>UnVT<5ny~`_^t=od delta 53 zcmez4*y+UO66_MfsmQ><7`u^6Qj*KbIX>7aKDx<+YqGB7OkNS5cuzl1jsgbfU{{~b I$0W_z0eo!^6aWAK diff --git a/tests/data/acpi/x86/q35/DSDT.memhp b/tests/data/acpi/x86/q35/DSDT.memhp index 4f2f9bcfceff076490cc49b8286380295a340004..7346125d23fb3174c0ce678a2cdf2fdc77c4a9fa 100644 GIT binary patch delta 39 vcmX@^v&)CeCD<jzN{xYmamGe2Nl7kmr}$u}_~<5Y&dIuxGdEwBEa3qF=Zp*G delta 53 zcmdnxbKHl^CD<jzU5$Z(apFcUNl7jb=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACoNM0RWT#4&?v< diff --git a/tests/data/acpi/x86/q35/DSDT.mmio64 b/tests/data/acpi/x86/q35/DSDT.mmio64 index 0fb6aab16f1bd79f3c0790cc9f644f7e52ac37b1..15a291dbfb62e6ceb0249e02eb25b319744e351f 100644 GIT binary patch delta 39 vcmaFlb=8Z@CD<h-RF#2&F>)i9q$HQOQ+%*fd~}mH=VV>UnVT<5_HzRO>=z6S delta 53 zcmccW^~j6MCD<h-NtJ<tF=!)~q$HPzb9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4g4(0|1#o4-5bR diff --git a/tests/data/acpi/x86/q35/DSDT.multi-bridge b/tests/data/acpi/x86/q35/DSDT.multi-bridge index f6afa6d96d2525d512cc46f17439f7a49962b730..889a9040d950dd08980408d57f1037a5fc20c961 100644 GIT binary patch delta 39 vcmaEx{ve&pCD<k8fiVLE<E@Qcl9F7mPVvD`@zG7*oRf7WXKubMDJ2B}6!;Aa delta 53 zcmaEm{x+S<CD<k8tuX@w<K>N9l9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|-z81pw8G5DEYQ diff --git a/tests/data/acpi/x86/q35/DSDT.noacpihp b/tests/data/acpi/x86/q35/DSDT.noacpihp index 9f7261d1b06bbf5d8a3e5a7a46b247a2a21eb544..780616774f97a2d7305faf9e9a9d12afeb0e2fa2 100644 GIT binary patch delta 39 vcmaFo@X&$FCD<h-QGtPhars8BUE*A>PVvD`@zG7*oRiOq&)i%h@rxY*2F?wn delta 53 zcmaFp@XmqDCD<h-Pl17faluBeUE*9$&hf!c@zG5lT$9g<&*T;1iTCvL<S1Zp4tDj~ JoG$T;9RSJJ5TpPA diff --git a/tests/data/acpi/x86/q35/DSDT.nohpet b/tests/data/acpi/x86/q35/DSDT.nohpet index 99ad629c9171ff6ab346d6b4c519e77ca23e5b1c..0f862ab2938e0e11aa8335630fad389095b37edd 100644 GIT binary patch delta 39 vcmaFmaMyv$CD<h-R)K+mv2P<+w*;4~Q+%*fd~}mH=j8bkGdH_Rs<HzB`rQm5 delta 53 zcmccX@XCS9CD<h-OM!ubv3(;~w*;4yb9}H<d~}ls*W~#UGkHaL;ywL5ISLq@gI#?# JTS%(10|2(>4<G;l diff --git a/tests/data/acpi/x86/q35/DSDT.numamem b/tests/data/acpi/x86/q35/DSDT.numamem index fd1d8a79d3d9b071c8796e5e99b76698a9a8d29c..df8edc05b69ecd1331973b16e534b44616b50f58 100644 GIT binary patch delta 39 vcmez8_|cKeCD<k8qXGj1W8g+ENl7kmr}$u}_~<5Y&dIuxGdEwB)Mf_&0sjnH delta 53 zcmez9_|K8cCD<k8p8^8|qt`|*Nl7jb=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACuH(2LQPL4_N>J diff --git a/tests/data/acpi/x86/q35/DSDT.pvpanic-isa b/tests/data/acpi/x86/q35/DSDT.pvpanic-isa index 89032fa0290f496be0c06c6382586541aa1118a8..da3ce12787c28e555b6ba5eacb26275bdd4587f1 100644 GIT binary patch delta 39 vcmccXbis+sCD<h-K#_rgv3w(!q$HQCQ+%*fd~}mH=VV>UnVT<5cCiBh>8}g; delta 53 zcmccMbk~W?CD<h-R*`{$v0x*Yq$HP<b9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4bj10|1sj4)_27 diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count b/tests/data/acpi/x86/q35/DSDT.thread-count index 7ebfceeb66460d0ad98471924ce224b7153e87ef..50ca91b065d9a2ba95f97d01856865f0e7c615f6 100644 GIT binary patch delta 40 wcmX?>x-*r_CD<iorx61KqwPj6NlEVJc*gi(r}*e5Z_dejk~247k^Ce900Y(yC;$Ke delta 54 zcmdm)dMuU8CD<k8m=Oa5quE9-NlEU81jhJar}*e553b32k~4Wlc;Y?%JUI#&oP%9` KHXoP#Bmn@rP7o*n diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count2 b/tests/data/acpi/x86/q35/DSDT.thread-count2 index d0394558a1faa0b4ba43abab66d474d96b477ff3..f460be2bf74ae512db8f24418b42e8cf2a56202d 100644 GIT binary patch delta 42 ycmdnr!L+G^iOVI}CB&$Ofq}7aBbTHkcTX8xe6Uk|bdxvdWIf55o3BV_X8`~d01a>e delta 56 zcmdng!L+}FiOVI}CB(jkfq}7oBbTHkcV{_Ue6Uk|bdv|yWIf55ydpgDo_?Mj1q{x? Mu0ETOOJ-*Q0MS7ZZ~y=R diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm12 b/tests/data/acpi/x86/q35/DSDT.tis.tpm12 index f2ed40ca70cb13e733e39f4bad756be8688e01fe..67ebd7c158759221b801ecb67d8562d92fa219d5 100644 GIT binary patch delta 39 vcmccScG8W@CD<jzQ<;H*@#{t|Nl7kOr}$u}_~<5Y&dIuxGdEwBY~}<2^lc1g delta 53 zcmX@<cFm2;CD<h-Oqqd!@!du)Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACqk61OTT-4`u)W diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm2 b/tests/data/acpi/x86/q35/DSDT.tis.tpm2 index 5c975d2162d0bfee5a3a089e79b5ba038f82b7ef..c6b58472157d575e2625557d1346586be06b927c 100644 GIT binary patch delta 39 vcmez1_SlWfCD<h-S($->as5UvNl7kOr}$u}_~<5Y&dIuxGdEwBoXZIS_>T;T delta 53 zcmaFt_Q8$ICD<jTK$(Goam7Y1Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACsKR2>`3u4~PH& diff --git a/tests/data/acpi/x86/q35/DSDT.type4-count b/tests/data/acpi/x86/q35/DSDT.type4-count index 3194a82b8b4f66aff1ecf7d2d60b4890181fc600..17a64adb2055ad3168754ca121bf29851d2ee496 100644 GIT binary patch delta 42 ycmew~k@4w7MlP3Nmyo9(3=E7>8@VJUx%&??#RogZM>lzMPS%s0x%rBuoIU_FstxM^ delta 56 zcmaDlk@3?+MlP3Nmyk~$3=E9H8@VJUxqA*V#RogZM>lzJP1ci~$t%JW@9F2sQNZ9F M?CP`mxTKsu001Nq>i_@% diff --git a/tests/data/acpi/x86/q35/DSDT.viot b/tests/data/acpi/x86/q35/DSDT.viot index 129d43e1e561be3fd7cd71406829ab81d0a8aba0..6eb30e8f4b2c54e4789c649475adff356c8c58a4 100644 GIT binary patch delta 39 vcmaD^bf<{RCD<h-#*%@7ar#CsNl7kOr}$u}_~<5Y&dIuxGdEwBoF)$d0-g-m delta 53 zcmcap^s<P{CD<h-(~^OKal%F}Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACsIW4*<Dl57+<z diff --git a/tests/data/acpi/x86/q35/DSDT.xapic b/tests/data/acpi/x86/q35/DSDT.xapic index b37ab591110d1c8201575ad6bba83449d7b90b21..111bb041dc0d114351add07c040dde61643d157a 100644 GIT binary patch delta 42 ycmcaTo$1_kCN7s?mymPa3=E828@VJUxjR0v#RogZM>lzMPS%s0x%rADdl3LU$qs)2 delta 56 zcmX>%o$2;;CN7s?myp}t3=E9T8@VJUxm!Q7#RogZM>lzJP1ci~$t%JW@9F2sQNZ9F M?CP`mxFmZK01fjIe*gdg diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 2ed74f72e7c9..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,30 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/x86/q35/DSDT", -"tests/data/acpi/x86/q35/DSDT.tis.tpm2", -"tests/data/acpi/x86/q35/DSDT.tis.tpm12", -"tests/data/acpi/x86/q35/DSDT.bridge", -"tests/data/acpi/x86/q35/DSDT.noacpihp", -"tests/data/acpi/x86/q35/DSDT.multi-bridge", -"tests/data/acpi/x86/q35/DSDT.ipmibt", -"tests/data/acpi/x86/q35/DSDT.cphp", -"tests/data/acpi/x86/q35/DSDT.numamem", -"tests/data/acpi/x86/q35/DSDT.nohpet", -"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator", -"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x", -"tests/data/acpi/x86/q35/DSDT.memhp", -"tests/data/acpi/x86/q35/DSDT.dimmpxm", -"tests/data/acpi/x86/q35/DSDT.acpihmat", -"tests/data/acpi/x86/q35/DSDT.mmio64", -"tests/data/acpi/x86/q35/DSDT.acpierst", -"tests/data/acpi/x86/q35/DSDT.applesmc", -"tests/data/acpi/x86/q35/DSDT.pvpanic-isa", -"tests/data/acpi/x86/q35/DSDT.ivrs", -"tests/data/acpi/x86/q35/DSDT.type4-count", -"tests/data/acpi/x86/q35/DSDT.core-count", -"tests/data/acpi/x86/q35/DSDT.core-count2", -"tests/data/acpi/x86/q35/DSDT.thread-count", -"tests/data/acpi/x86/q35/DSDT.thread-count2", -"tests/data/acpi/x86/q35/DSDT.viot", -"tests/data/acpi/x86/q35/DSDT.cxl", -"tests/data/acpi/x86/q35/DSDT.ipmismbus", -"tests/data/acpi/x86/q35/DSDT.xapic", -- 2.34.1
On Wed, 3 Dec 2025 00:28:15 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
Now the legacy cpu hotplug way has gone away, and there's no _INIT method in DSDT table for modern cpu hotplug support.
Update DSDT tables for q35 machine.
The following diff changes show only _INIT methods are removed from DSDT tables.
* tests/data/acpi/x86/q35/DSDT:
missing SoB squash this into previous patch with that Acked-by: Igor Mammedov <imammedo@redhat.com>
--- /tmp/asl-BSAVG3.dsl 2025-11-27 15:29:29.707267890 +0800 +++ /tmp/asl-WDGVG3.dsl 2025-11-27 15:29:29.700267890 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT, Thu Nov 27 15:29:29 2025 + * Disassembly of /tmp/aml-AFGVG3, Thu Nov 27 15:29:29 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000020F8 (8440) + * Length 0x000020EB (8427) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xBE + * Checksum 0xC5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.acpierst:
--- /tmp/asl-5FERG3.dsl 2025-11-27 15:29:23.887268107 +0800 +++ /tmp/asl-PPKRG3.dsl 2025-11-27 15:29:23.881268108 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpierst, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-0QKRG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002109 (8457) + * Length 0x000020FC (8444) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5D + * Checksum 0x65 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.acpihmat:
--- /tmp/asl-JRLYG3.dsl 2025-11-27 15:29:21.552268195 +0800 +++ /tmp/asl-QETYG3.dsl 2025-11-27 15:29:21.544268195 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-2FTYG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002625 (9765) + * Length 0x00002618 (9752) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x7A + * Checksum 0x81 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x:
--- /tmp/asl-38KFG3.dsl 2025-11-27 15:29:14.394268462 +0800 +++ /tmp/asl-9ETFG3.dsl 2025-11-27 15:29:14.384268462 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x, Thu Nov 27 15:29:14 2025 + * Disassembly of /tmp/aml-OHTFG3, Thu Nov 27 15:29:14 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000316A (12650) + * Length 0x0000315D (12637) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x1F + * Checksum 0x35 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator:
--- /tmp/asl-N0VHG3.dsl 2025-11-27 15:29:16.287268391 +0800 +++ /tmp/asl-XTAIG3.dsl 2025-11-27 15:29:16.277268392 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator, Thu Nov 27 15:29:16 2025 + * Disassembly of /tmp/aml-1UAIG3, Thu Nov 27 15:29:16 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000220F (8719) + * Length 0x00002202 (8706) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x34 + * Checksum 0x3B * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.applesmc:
--- /tmp/asl-XR4EG3.dsl 2025-11-27 15:29:25.412268050 +0800 +++ /tmp/asl-6IBFG3.dsl 2025-11-27 15:29:25.404268051 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.applesmc, Thu Nov 27 15:29:25 2025 + * Disassembly of /tmp/aml-TPBFG3, Thu Nov 27 15:29:25 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002126 (8486) + * Length 0x00002119 (8473) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xAD + * Checksum 0xB4 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.bridge:
--- /tmp/asl-7WRVG3.dsl 2025-11-27 15:28:59.686269011 +0800 +++ /tmp/asl-KEYVG3.dsl 2025-11-27 15:28:59.676269012 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.bridge, Thu Nov 27 15:28:59 2025 + * Disassembly of /tmp/aml-NCYVG3, Thu Nov 27 15:28:59 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002F15 (12053) + * Length 0x00002F08 (12040) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xD9 + * Checksum 0xE0 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.core-count:
--- /tmp/asl-RENPG3.dsl 2025-11-27 15:29:21.971268179 +0800 +++ /tmp/asl-IGXPG3.dsl 2025-11-27 15:29:21.961268179 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.core-count, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-GPWPG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000032C6 (12998) + * Length 0x000032B9 (12985) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x36 + * Checksum 0x3D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.core-count2:
--- /tmp/asl-YGFMG3.dsl 2025-11-27 15:29:23.094268137 +0800 +++ /tmp/asl-SU2MG3.dsl 2025-11-27 15:29:23.063268138 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.core-count2, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-OW2MG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000843F (33855) + * Length 0x00008432 (33842) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.cphp:
--- /tmp/asl-SAFWG3.dsl 2025-11-27 15:29:09.652268639 +0800 +++ /tmp/asl-1BJWG3.dsl 2025-11-27 15:29:09.646268639 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.cphp, Thu Nov 27 15:29:09 2025 + * Disassembly of /tmp/aml-JAJWG3, Thu Nov 27 15:29:09 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000022C8 (8904) + * Length 0x000022BB (8891) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x31 + * Checksum 0x38 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.cxl:
--- /tmp/asl-VYSRG3.dsl 2025-11-27 15:29:35.869267660 +0800 +++ /tmp/asl-RAZRG3.dsl 2025-11-27 15:29:35.862267660 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.cxl, Thu Nov 27 15:29:35 2025 + * Disassembly of /tmp/aml-ZBZRG3, Thu Nov 27 15:29:35 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000033AF (13231) + * Length 0x000033A2 (13218) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF2 + * Checksum 0xF9 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.dimmpxm:
--- /tmp/asl-A93JG3.dsl 2025-11-27 15:29:20.180268246 +0800 +++ /tmp/asl-CEBKG3.dsl 2025-11-27 15:29:20.172268246 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.dimmpxm, Thu Nov 27 15:29:20 2025 + * Disassembly of /tmp/aml-MFBKG3, Thu Nov 27 15:29:20 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000276E (10094) + * Length 0x00002761 (10081) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xDE + * Checksum 0xE5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj)
Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 @@ -2891,37 +2891,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.ipmibt:
--- /tmp/asl-SW1YG3.dsl 2025-11-27 15:29:04.532268830 +0800 +++ /tmp/asl-KJQCG3.dsl 2025-11-27 15:29:04.524268831 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ipmibt, Thu Nov 27 15:29:04 2025 + * Disassembly of /tmp/aml-MMQCG3, Thu Nov 27 15:29:04 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002143 (8515) + * Length 0x00002136 (8502) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF1 + * Checksum 0xF8 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.ipmismbus:
--- /tmp/asl-5BDMG3.dsl 2025-11-27 15:29:31.075267839 +0800 +++ /tmp/asl-KKIMG3.dsl 2025-11-27 15:29:31.068267839 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ipmismbus, Thu Nov 27 15:29:31 2025 + * Disassembly of /tmp/aml-8LIMG3, Thu Nov 27 15:29:31 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002150 (8528) + * Length 0x00002143 (8515) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x62 + * Checksum 0x69 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.ivrs:
--- /tmp/asl-AZ0SG3.dsl 2025-11-27 15:29:27.813267961 +0800 +++ /tmp/asl-QV7SG3.dsl 2025-11-27 15:29:27.804267961 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.ivrs, Thu Nov 27 15:29:27 2025 + * Disassembly of /tmp/aml-PU7SG3, Thu Nov 27 15:29:27 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002109 (8457) + * Length 0x000020FC (8444) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5D + * Checksum 0x65 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.memhp:
--- /tmp/asl-VVJNG3.dsl 2025-11-27 15:29:19.018268289 +0800 +++ /tmp/asl-EIONG3.dsl 2025-11-27 15:29:19.013268289 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.memhp, Thu Nov 27 15:29:19 2025 + * Disassembly of /tmp/aml-FHONG3, Thu Nov 27 15:29:19 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002647 (9799) + * Length 0x0000263A (9786) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x91 + * Checksum 0x98 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.mmio64:
--- /tmp/asl-7NEUG3.dsl 2025-11-27 15:29:22.749268150 +0800 +++ /tmp/asl-FQSUG3.dsl 2025-11-27 15:29:22.741268150 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.mmio64, Thu Nov 27 15:29:22 2025 + * Disassembly of /tmp/aml-WPSUG3, Thu Nov 27 15:29:22 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002562 (9570) + * Length 0x00002555 (9557) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x52 + * Checksum 0x59 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.multi-bridge:
--- /tmp/asl-JNDLG3.dsl 2025-11-27 15:29:02.126268920 +0800 +++ /tmp/asl-6QNLG3.dsl 2025-11-27 15:29:02.113268921 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.multi-bridge, Thu Nov 27 15:29:02 2025 + * Disassembly of /tmp/aml-0ONLG3, Thu Nov 27 15:29:02 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000033ED (13293) + * Length 0x000033E0 (13280) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xD3 + * Checksum 0xDA * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.noacpihp:
--- /tmp/asl-5PGXG3.dsl 2025-11-27 15:29:04.605268828 +0800 +++ /tmp/asl-WLPXG3.dsl 2025-11-27 15:29:04.597268828 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.noacpihp, Thu Nov 27 15:29:04 2025 + * Disassembly of /tmp/aml-VNPXG3, Thu Nov 27 15:29:04 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000206E (8302) + * Length 0x00002061 (8289) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xA0 + * Checksum 0xA7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2796,37 +2796,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.nohpet:
--- /tmp/asl-CF4OG3.dsl 2025-11-27 15:29:14.994268440 +0800 +++ /tmp/asl-KFBPG3.dsl 2025-11-27 15:29:14.987268440 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.nohpet, Thu Nov 27 15:29:14 2025 + * Disassembly of /tmp/aml-QHBPG3, Thu Nov 27 15:29:14 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000206A (8298) + * Length 0x0000205D (8285) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2844,37 +2844,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.numamem:
--- /tmp/asl-IPHHG3.dsl 2025-11-27 15:29:07.303268727 +0800 +++ /tmp/asl-67NHG3.dsl 2025-11-27 15:29:07.295268727 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.numamem, Thu Nov 27 15:29:07 2025 + * Disassembly of /tmp/aml-NAOHG3, Thu Nov 27 15:29:07 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000020FE (8446) + * Length 0x000020F1 (8433) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x4A + * Checksum 0x51 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.pvpanic-isa:
--- /tmp/asl-WJDHG3.dsl 2025-11-27 15:29:18.306268316 +0800 +++ /tmp/asl-6RHHG3.dsl 2025-11-27 15:29:18.300268316 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.pvpanic-isa, Thu Nov 27 15:29:18 2025 + * Disassembly of /tmp/aml-XUNHG3, Thu Nov 27 15:29:18 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000215D (8541) + * Length 0x00002150 (8528) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x70 + * Checksum 0x77 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.thread-count:
--- /tmp/asl-TWDTG3.dsl 2025-11-27 15:29:23.799268111 +0800 +++ /tmp/asl-USNTG3.dsl 2025-11-27 15:29:23.788268111 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.thread-count, Thu Nov 27 15:29:23 2025 + * Disassembly of /tmp/aml-ASNTG3, Thu Nov 27 15:29:23 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000032C6 (12998) + * Length 0x000032B9 (12985) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x36 + * Checksum 0x3D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.thread-count2:
--- /tmp/asl-I56IG3.dsl 2025-11-27 15:29:25.246268057 +0800 +++ /tmp/asl-Z2YJG3.dsl 2025-11-27 15:29:25.213268058 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.thread-count2, Thu Nov 27 15:29:25 2025 + * Disassembly of /tmp/aml-L4YJG3, Thu Nov 27 15:29:25 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x0000843F (33855) + * Length 0x00008432 (33842) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x87 + * Checksum 0x8E * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.tis.tpm12:
--- /tmp/asl-SHLRG3.dsl 2025-11-27 15:29:01.877268929 +0800 +++ /tmp/asl-1LQRG3.dsl 2025-11-27 15:29:01.871268930 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.tis.tpm12, Thu Nov 27 15:29:01 2025 + * Disassembly of /tmp/aml-9MQRG3, Thu Nov 27 15:29:01 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002356 (9046) + * Length 0x00002349 (9033) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xEE + * Checksum 0xF5 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.tis.tpm2:
--- /tmp/asl-KISFG3.dsl 2025-11-27 15:28:57.380269097 +0800 +++ /tmp/asl-ZIYFG3.dsl 2025-11-27 15:28:57.373269098 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.tis.tpm2, Thu Nov 27 15:28:57 2025 + * Disassembly of /tmp/aml-ZJYFG3, Thu Nov 27 15:28:57 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00002370 (9072) + * Length 0x00002363 (9059) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xA8 + * Checksum 0xAF * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.type4-count:
--- /tmp/asl-PJ6JG3.dsl 2025-11-27 15:29:21.179268209 +0800 +++ /tmp/asl-GPJKG3.dsl 2025-11-27 15:29:21.168268209 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.type4-count, Thu Nov 27 15:29:21 2025 + * Disassembly of /tmp/aml-FRJKG3, Thu Nov 27 15:29:21 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x000048F2 (18674) + * Length 0x000048E5 (18661) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x53 + * Checksum 0x5A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
* tests/data/acpi/x86/q35/DSDT.viot:
--- /tmp/asl-9POJG3.dsl 2025-11-27 15:29:26.204268021 +0800 +++ /tmp/asl-BEXJG3.dsl 2025-11-27 15:29:26.192268021 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.viot, Thu Nov 27 15:29:26 2025 + * Disassembly of /tmp/aml-YDXJG3, Thu Nov 27 15:29:26 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00003969 (14697) + * Length 0x0000395C (14684) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x90 + * Checksum 0x97 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) } }
Method (CSTA, 1, Serialized) {
* tests/data/acpi/x86/q35/DSDT.xapic:
--- /tmp/asl-JOGEG3.dsl 2025-11-27 15:29:32.463267787 +0800 +++ /tmp/asl-6UFFG3.dsl 2025-11-27 15:29:32.428267788 +0800 @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/x86/q35/DSDT.xapic, Thu Nov 27 15:29:32 2025 + * Disassembly of /tmp/aml-U2EFG3, Thu Nov 27 15:29:32 2025 * * Original Table Header: * Signature "DSDT" - * Length 0x00008BDB (35803) + * Length 0x00008BCE (35790) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x83 + * Checksum 0x8A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 }
@@ -2885,37 +2885,32 @@ Offset (0x04), CPEN, 1, CINS, 1, CRMV, 1, CEJ0, 1, CEJF, 1, Offset (0x05), CCMD, 8 }
Field (PRST, DWordAcc, NoLock, Preserve) { CSEL, 32, Offset (0x08), CDAT, 32 } - - Method (_INI, 0, Serialized) // _INI: Initialize - { - CSEL = Zero - } }
Device (\_SB.CPUS) { Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID Method (CTFY, 2, NotSerialized) { If ((Arg0 == Zero)) { Notify (C000, Arg1) }
If ((Arg0 == One)) { Notify (C001, Arg1)
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * New patch. --- tests/data/acpi/x86/q35/DSDT | Bin 8440 -> 8427 bytes tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9765 -> 9752 bytes .../data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12650 -> 12637 bytes .../acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8719 -> 8706 bytes tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8486 -> 8473 bytes tests/data/acpi/x86/q35/DSDT.bridge | Bin 12053 -> 12040 bytes tests/data/acpi/x86/q35/DSDT.core-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.cphp | Bin 8904 -> 8891 bytes tests/data/acpi/x86/q35/DSDT.cxl | Bin 13231 -> 13218 bytes tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10094 -> 10081 bytes tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8515 -> 8502 bytes tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8528 -> 8515 bytes tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8457 -> 8444 bytes tests/data/acpi/x86/q35/DSDT.memhp | Bin 9799 -> 9786 bytes tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9570 -> 9557 bytes tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13293 -> 13280 bytes tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8302 -> 8289 bytes tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8298 -> 8285 bytes tests/data/acpi/x86/q35/DSDT.numamem | Bin 8446 -> 8433 bytes tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8541 -> 8528 bytes tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12998 -> 12985 bytes tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33855 -> 33842 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 9046 -> 9033 bytes tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 9072 -> 9059 bytes tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18674 -> 18661 bytes tests/data/acpi/x86/q35/DSDT.viot | Bin 14697 -> 14684 bytes tests/data/acpi/x86/q35/DSDT.xapic | Bin 35803 -> 35790 bytes tests/qtest/bios-tables-test-allowed-diff.h | 29 ------------------ 30 files changed, 29 deletions(-)
diff --git a/tests/data/acpi/x86/q35/DSDT b/tests/data/acpi/x86/q35/DSDT index e5e8d1e041e20e1b3ee56a5c93fe3d6ebd721ee6..377e880175f6f11101548c0c64da61b5aee00bd9 100644 GIT binary patch delta 39 vcmez2_}Y=nCD<k8wE_bJ<I#;=l9F7mPVvD`@zG7*oRf7WXKubMsmcxj3Rw)V
delta 53 zcmaFu_`{LQCD<k8hXMlw<Gzhtl9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|?Nk4gkhs53c|K
diff --git a/tests/data/acpi/x86/q35/DSDT.acpierst b/tests/data/acpi/x86/q35/DSDT.acpierst index 072a3fe2cd17dfe06658dfd82588f69787810114..026bfdfebf66c1803f158ac8c115eb5f49b5cb19 100644 GIT binary patch delta 39 vcmeBl`s2vu66_N4M}dKXF?A!Cq$HQCQ+%*fd~}mH=VV>UnVT<5ny~`_^t=od
delta 53 zcmez4*y+UO66_MfsmQ><7`u^6Qj*KbIX>7aKDx<+YqGB7OkNS5cuzl1jsgbfU{{~b I$0W_z0eo!^6aWAK
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat b/tests/data/acpi/x86/q35/DSDT.acpihmat index 2a4f2fc1d5c5649673353186e67ff5b5e59e8d53..f1b8483d8da21dd57f3e5e7a1e4eb787df2c38ac 100644 GIT binary patch delta 39 vcmZ4LGsB0=CD<iILXClev2i1pq$HP%M|`kTd~}mH=VV>UnVT<52Jrv@*4zt4
delta 53 zcmbQ?v($&nCD<iIRgHmxv1%iiq$HQ4XMC_zd~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4Xmc004Yz4n+U}
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x b/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x index 7911c058bba5005d318b8db8d6da5c1ee381b0f1..a7731403f460a235bf705770a1547dafeee069ab 100644 GIT binary patch delta 39 vcmaErbT^61CD<h-){udL(R3r1q$HP<Uwp7rd~}mH=VV>UnVT<5P8SCN^mq(Y
delta 53 zcmcbc^eTzVCD<h-%aDPAQGO$rq$HQWUwp7rd~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4a7!2LPlJ4^sdD
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator index 580b4a456a20fc0cc0a832eaf74193b46d8ae8b1..cb4995de7e33cd9f2d134ec96651d217873d6944 100644 GIT binary patch delta 39 ucmeBoX>#Fm33dr#Qet3WwBE=iDaqv%93SiyAKm25Iayb7=H|<iHXH!OR0^U1
delta 53 zcmZp2>389B33dtLS7KmbG}*`{Daqv-5+CdoAKm1^HCb13Ca(xjyr-WhM*)L#u&dAJ IW0E!;0Apnhq5uE@
diff --git a/tests/data/acpi/x86/q35/DSDT.applesmc b/tests/data/acpi/x86/q35/DSDT.applesmc index 5e8220e38d6f88b103f6eb3eb7c78dfa466882dc..92c8fdb6cbb8ae8bdf5ede9679eea92486eaf372 100644 GIT binary patch delta 39 vcmZ4HG}DR8CD<iIQjvjyamz+7Nl7kOr}$u}_~<5Y&dIuxGdEwB3}y!a*l-J3
delta 53 zcmbQ~w9JXiCD<iIO_70taqUJfNl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACnAb2LOLh4p{&I
diff --git a/tests/data/acpi/x86/q35/DSDT.bridge b/tests/data/acpi/x86/q35/DSDT.bridge index ee039453af1071e00a81ee7b37cf8f417f524257..957b3ad90c787616eac212865bce0a19a5ac1e6e 100644 GIT binary patch delta 39 vcmbOl*Ad6%66_Mfq0hj;_+TTKq$HQCQ+%*fd~}mH=VV>UnVT<5I*9@R-%JaY
delta 53 zcmeB(n;OUE66_Kps?Wf{cyl9{q$HP<b9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4ZX-0sx7f4wV1^
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count b/tests/data/acpi/x86/q35/DSDT.core-count index 7ebfceeb66460d0ad98471924ce224b7153e87ef..50ca91b065d9a2ba95f97d01856865f0e7c615f6 100644 GIT binary patch delta 40 wcmX?>x-*r_CD<iorx61KqwPj6NlEVJc*gi(r}*e5Z_dejk~247k^Ce900Y(yC;$Ke
delta 54 zcmdm)dMuU8CD<k8m=Oa5quE9-NlEU81jhJar}*e553b32k~4Wlc;Y?%JUI#&oP%9` KHXoP#Bmn@rP7o*n
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count2 b/tests/data/acpi/x86/q35/DSDT.core-count2 index d0394558a1faa0b4ba43abab66d474d96b477ff3..f460be2bf74ae512db8f24418b42e8cf2a56202d 100644 GIT binary patch delta 42 ycmdnr!L+G^iOVI}CB&$Ofq}7aBbTHkcTX8xe6Uk|bdxvdWIf55o3BV_X8`~d01a>e
delta 56 zcmdng!L+}FiOVI}CB(jkfq}7oBbTHkcV{_Ue6Uk|bdv|yWIf55ydpgDo_?Mj1q{x? Mu0ETOOJ-*Q0MS7ZZ~y=R
diff --git a/tests/data/acpi/x86/q35/DSDT.cphp b/tests/data/acpi/x86/q35/DSDT.cphp index a055c2e7d3c4f5a00a03be20fd73227e322283a4..7c87d41d03fcfd2b5b82f2581f16de6bc0bb10bf 100644 GIT binary patch delta 39 vcmX@%y4#h@CD<iow-N&bqs2xpNl7l(`1oL__~<5Y&dIuxGdEwB{K^3U?XnDt
delta 53 zcmdn(dcu{<CD<k8gc1V-qv1v_Nl7lJg!o{m_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACvsb0RWs;4~hT)
diff --git a/tests/data/acpi/x86/q35/DSDT.cxl b/tests/data/acpi/x86/q35/DSDT.cxl index 20843549f54af1cb0e6017c4cfff7463318d9eb7..da86b25f51b550ab20771111cb0a2bc49e713186 100644 GIT binary patch delta 39 vcmZ3Vz9^l`CD<iokud`U<Ijy;l9F7mPVvD`@zG7*oRf7WXKubMc}Efe|Hln5
delta 53 zcmZ3KzCNAHCD<ioy)gp=<EM>Wl9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|=lb5&*aE5HJ7$
diff --git a/tests/data/acpi/x86/q35/DSDT.dimmpxm b/tests/data/acpi/x86/q35/DSDT.dimmpxm index 664e926e90765550136242f7e3e0bdc7719c1853..a2d812e5a23a3ce7739789246b342e703f8c96c0 100644 GIT binary patch delta 39 vcmaFo_t1~aCD<h-QJsN-@##h`T}dv#;P_yt_~<5Y&dH9FGdDk%Z07|41ThT|
delta 53 zcmaFp_s);YCD<h-Po05*@!m!*T}dwQkoaJy_~<4NuE~y)GkHaL;ywL5ISLq@gI#?# J-;!+S1pvOk5D)+W
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmibt b/tests/data/acpi/x86/q35/DSDT.ipmibt index 4066a76d26aa380dfbecc58aa3f83ab5db2baadb..43ac1bd693d1b3f67d2a9e89ccaf8a56656df22d 100644 GIT binary patch delta 39 vcmX@?w9SdjCD<jzOp$?s@yA9kNl7kOr}$u}_~<5Y&dIuxGdEwBEMNx!>rf04
delta 53 zcmdnybl8c@CD<jzS&@N(@#97=Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACoL#2LPI>4-o(W
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmismbus b/tests/data/acpi/x86/q35/DSDT.ipmismbus index 6d0b6b95c2a9fd01befc37b26650781ee1562e2a..1b998820d46e522b3129e42a867ed691c1f83e8f 100644 GIT binary patch delta 39 vcmccMbl8c@CD<jzS&@N(F>@oAq$HQCQ+%*fd~}mH=VV>UnVT<5*0KWt;?)bb
delta 53 zcmX@?bis+sCD<h-K#_rgF=->0q$HP<b9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4e_D0|1PE4z>UQ
diff --git a/tests/data/acpi/x86/q35/DSDT.ivrs b/tests/data/acpi/x86/q35/DSDT.ivrs index 072a3fe2cd17dfe06658dfd82588f69787810114..026bfdfebf66c1803f158ac8c115eb5f49b5cb19 100644 GIT binary patch delta 39 vcmeBl`s2vu66_N4M}dKXF?A!Cq$HQCQ+%*fd~}mH=VV>UnVT<5ny~`_^t=od
delta 53 zcmez4*y+UO66_MfsmQ><7`u^6Qj*KbIX>7aKDx<+YqGB7OkNS5cuzl1jsgbfU{{~b I$0W_z0eo!^6aWAK
diff --git a/tests/data/acpi/x86/q35/DSDT.memhp b/tests/data/acpi/x86/q35/DSDT.memhp index 4f2f9bcfceff076490cc49b8286380295a340004..7346125d23fb3174c0ce678a2cdf2fdc77c4a9fa 100644 GIT binary patch delta 39 vcmX@^v&)CeCD<jzN{xYmamGe2Nl7kmr}$u}_~<5Y&dIuxGdEwBEa3qF=Zp*G
delta 53 zcmdnxbKHl^CD<jzU5$Z(apFcUNl7jb=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACoNM0RWT#4&?v<
diff --git a/tests/data/acpi/x86/q35/DSDT.mmio64 b/tests/data/acpi/x86/q35/DSDT.mmio64 index 0fb6aab16f1bd79f3c0790cc9f644f7e52ac37b1..15a291dbfb62e6ceb0249e02eb25b319744e351f 100644 GIT binary patch delta 39 vcmaFlb=8Z@CD<h-RF#2&F>)i9q$HQOQ+%*fd~}mH=VV>UnVT<5_HzRO>=z6S
delta 53 zcmccW^~j6MCD<h-NtJ<tF=!)~q$HPzb9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4g4(0|1#o4-5bR
diff --git a/tests/data/acpi/x86/q35/DSDT.multi-bridge b/tests/data/acpi/x86/q35/DSDT.multi-bridge index f6afa6d96d2525d512cc46f17439f7a49962b730..889a9040d950dd08980408d57f1037a5fc20c961 100644 GIT binary patch delta 39 vcmaEx{ve&pCD<k8fiVLE<E@Qcl9F7mPVvD`@zG7*oRf7WXKubMDJ2B}6!;Aa
delta 53 zcmaEm{x+S<CD<k8tuX@w<K>N9l9F6b&hf!c@zG5lT$6PrXYz{h#C!UAauhH)2fO-g JJ|-z81pw8G5DEYQ
diff --git a/tests/data/acpi/x86/q35/DSDT.noacpihp b/tests/data/acpi/x86/q35/DSDT.noacpihp index 9f7261d1b06bbf5d8a3e5a7a46b247a2a21eb544..780616774f97a2d7305faf9e9a9d12afeb0e2fa2 100644 GIT binary patch delta 39 vcmaFo@X&$FCD<h-QGtPhars8BUE*A>PVvD`@zG7*oRiOq&)i%h@rxY*2F?wn
delta 53 zcmaFp@XmqDCD<h-Pl17faluBeUE*9$&hf!c@zG5lT$9g<&*T;1iTCvL<S1Zp4tDj~ JoG$T;9RSJJ5TpPA
diff --git a/tests/data/acpi/x86/q35/DSDT.nohpet b/tests/data/acpi/x86/q35/DSDT.nohpet index 99ad629c9171ff6ab346d6b4c519e77ca23e5b1c..0f862ab2938e0e11aa8335630fad389095b37edd 100644 GIT binary patch delta 39 vcmaFmaMyv$CD<h-R)K+mv2P<+w*;4~Q+%*fd~}mH=j8bkGdH_Rs<HzB`rQm5
delta 53 zcmccX@XCS9CD<h-OM!ubv3(;~w*;4yb9}H<d~}ls*W~#UGkHaL;ywL5ISLq@gI#?# JTS%(10|2(>4<G;l
diff --git a/tests/data/acpi/x86/q35/DSDT.numamem b/tests/data/acpi/x86/q35/DSDT.numamem index fd1d8a79d3d9b071c8796e5e99b76698a9a8d29c..df8edc05b69ecd1331973b16e534b44616b50f58 100644 GIT binary patch delta 39 vcmez8_|cKeCD<k8qXGj1W8g+ENl7kmr}$u}_~<5Y&dIuxGdEwB)Mf_&0sjnH
delta 53 zcmez9_|K8cCD<k8p8^8|qt`|*Nl7jb=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACuH(2LQPL4_N>J
diff --git a/tests/data/acpi/x86/q35/DSDT.pvpanic-isa b/tests/data/acpi/x86/q35/DSDT.pvpanic-isa index 89032fa0290f496be0c06c6382586541aa1118a8..da3ce12787c28e555b6ba5eacb26275bdd4587f1 100644 GIT binary patch delta 39 vcmccXbis+sCD<h-K#_rgv3w(!q$HQCQ+%*fd~}mH=VV>UnVT<5cCiBh>8}g;
delta 53 zcmccMbk~W?CD<h-R*`{$v0x*Yq$HP<b9}H<d~}ls*JNGEnY<!A@t%I390d%{!LB}= Jk4bj10|1sj4)_27
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count b/tests/data/acpi/x86/q35/DSDT.thread-count index 7ebfceeb66460d0ad98471924ce224b7153e87ef..50ca91b065d9a2ba95f97d01856865f0e7c615f6 100644 GIT binary patch delta 40 wcmX?>x-*r_CD<iorx61KqwPj6NlEVJc*gi(r}*e5Z_dejk~247k^Ce900Y(yC;$Ke
delta 54 zcmdm)dMuU8CD<k8m=Oa5quE9-NlEU81jhJar}*e553b32k~4Wlc;Y?%JUI#&oP%9` KHXoP#Bmn@rP7o*n
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count2 b/tests/data/acpi/x86/q35/DSDT.thread-count2 index d0394558a1faa0b4ba43abab66d474d96b477ff3..f460be2bf74ae512db8f24418b42e8cf2a56202d 100644 GIT binary patch delta 42 ycmdnr!L+G^iOVI}CB&$Ofq}7aBbTHkcTX8xe6Uk|bdxvdWIf55o3BV_X8`~d01a>e
delta 56 zcmdng!L+}FiOVI}CB(jkfq}7oBbTHkcV{_Ue6Uk|bdv|yWIf55ydpgDo_?Mj1q{x? Mu0ETOOJ-*Q0MS7ZZ~y=R
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm12 b/tests/data/acpi/x86/q35/DSDT.tis.tpm12 index f2ed40ca70cb13e733e39f4bad756be8688e01fe..67ebd7c158759221b801ecb67d8562d92fa219d5 100644 GIT binary patch delta 39 vcmccScG8W@CD<jzQ<;H*@#{t|Nl7kOr}$u}_~<5Y&dIuxGdEwBY~}<2^lc1g
delta 53 zcmX@<cFm2;CD<h-Oqqd!@!du)Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACqk61OTT-4`u)W
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm2 b/tests/data/acpi/x86/q35/DSDT.tis.tpm2 index 5c975d2162d0bfee5a3a089e79b5ba038f82b7ef..c6b58472157d575e2625557d1346586be06b927c 100644 GIT binary patch delta 39 vcmez1_SlWfCD<h-S($->as5UvNl7kOr}$u}_~<5Y&dIuxGdEwBoXZIS_>T;T
delta 53 zcmaFt_Q8$ICD<jTK$(Goam7Y1Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACsKR2>`3u4~PH&
diff --git a/tests/data/acpi/x86/q35/DSDT.type4-count b/tests/data/acpi/x86/q35/DSDT.type4-count index 3194a82b8b4f66aff1ecf7d2d60b4890181fc600..17a64adb2055ad3168754ca121bf29851d2ee496 100644 GIT binary patch delta 42 ycmew~k@4w7MlP3Nmyo9(3=E7>8@VJUx%&??#RogZM>lzMPS%s0x%rBuoIU_FstxM^
delta 56 zcmaDlk@3?+MlP3Nmyk~$3=E9H8@VJUxqA*V#RogZM>lzJP1ci~$t%JW@9F2sQNZ9F M?CP`mxTKsu001Nq>i_@%
diff --git a/tests/data/acpi/x86/q35/DSDT.viot b/tests/data/acpi/x86/q35/DSDT.viot index 129d43e1e561be3fd7cd71406829ab81d0a8aba0..6eb30e8f4b2c54e4789c649475adff356c8c58a4 100644 GIT binary patch delta 39 vcmaD^bf<{RCD<h-#*%@7ar#CsNl7kOr}$u}_~<5Y&dIuxGdEwBoF)$d0-g-m
delta 53 zcmcap^s<P{CD<h-(~^OKal%F}Nl7jz=lEc!_~<4NuF1NRGkHaL;ywL5ISLq@gI#?# JACsIW4*<Dl57+<z
diff --git a/tests/data/acpi/x86/q35/DSDT.xapic b/tests/data/acpi/x86/q35/DSDT.xapic index b37ab591110d1c8201575ad6bba83449d7b90b21..111bb041dc0d114351add07c040dde61643d157a 100644 GIT binary patch delta 42 ycmcaTo$1_kCN7s?mymPa3=E828@VJUxjR0v#RogZM>lzMPS%s0x%rADdl3LU$qs)2
delta 56 zcmX>%o$2;;CN7s?myp}t3=E9T8@VJUxm!Q7#RogZM>lzJP1ci~$t%JW@9F2sQNZ9F M?CP`mxFmZK01fjIe*gdg
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 2ed74f72e7c9..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,30 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/x86/q35/DSDT", -"tests/data/acpi/x86/q35/DSDT.tis.tpm2", -"tests/data/acpi/x86/q35/DSDT.tis.tpm12", -"tests/data/acpi/x86/q35/DSDT.bridge", -"tests/data/acpi/x86/q35/DSDT.noacpihp", -"tests/data/acpi/x86/q35/DSDT.multi-bridge", -"tests/data/acpi/x86/q35/DSDT.ipmibt", -"tests/data/acpi/x86/q35/DSDT.cphp", -"tests/data/acpi/x86/q35/DSDT.numamem", -"tests/data/acpi/x86/q35/DSDT.nohpet", -"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator", -"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x", -"tests/data/acpi/x86/q35/DSDT.memhp", -"tests/data/acpi/x86/q35/DSDT.dimmpxm", -"tests/data/acpi/x86/q35/DSDT.acpihmat", -"tests/data/acpi/x86/q35/DSDT.mmio64", -"tests/data/acpi/x86/q35/DSDT.acpierst", -"tests/data/acpi/x86/q35/DSDT.applesmc", -"tests/data/acpi/x86/q35/DSDT.pvpanic-isa", -"tests/data/acpi/x86/q35/DSDT.ivrs", -"tests/data/acpi/x86/q35/DSDT.type4-count", -"tests/data/acpi/x86/q35/DSDT.core-count", -"tests/data/acpi/x86/q35/DSDT.core-count2", -"tests/data/acpi/x86/q35/DSDT.thread-count", -"tests/data/acpi/x86/q35/DSDT.thread-count2", -"tests/data/acpi/x86/q35/DSDT.viot", -"tests/data/acpi/x86/q35/DSDT.cxl", -"tests/data/acpi/x86/q35/DSDT.ipmismbus", -"tests/data/acpi/x86/q35/DSDT.xapic",
From: Philippe Mathieu-Daudé <philmd@linaro.org> Rename fw_cfg_init_mem() as fw_cfg_init_mem_nodma() to distinct with the DMA version (currently named fw_cfg_init_mem_wide). Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/hppa/machine.c | 2 +- hw/nvram/fw_cfg.c | 7 +++---- include/hw/nvram/fw_cfg.h | 3 ++- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 8c66eed5a269..479fbf25b9ac 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -208,7 +208,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms, PCIBus *pci_bus, int btlb_entries = HPPA_BTLB_ENTRIES(&cpu[0]->env); int len; - fw_cfg = fw_cfg_init_mem(addr, addr + 4); + fw_cfg = fw_cfg_init_mem_nodma(addr, addr + 4, 1); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index aa240504935b..2b8715679fe7 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1088,11 +1088,10 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, return s; } -FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) +FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, + unsigned data_width) { - return fw_cfg_init_mem_wide(ctl_addr, data_addr, - fw_cfg_data_mem_ops.valid.max_access_size, - 0, NULL); + return fw_cfg_init_mem_wide(ctl_addr, data_addr, data_width, 0, NULL); } diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index d41b9328fd13..d5161a794362 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -307,7 +307,8 @@ bool fw_cfg_add_file_from_generator(FWCfgState *s, FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, AddressSpace *dma_as); -FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr); +FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, + unsigned data_width); FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr, uint32_t data_width, hwaddr dma_addr, AddressSpace *dma_as); -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> fw_cfg_init_mem_wide() is prefered to initialize fw_cfg with DMA support. Without DMA, use fw_cfg_init_mem_nodma(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/mips/loongson3_virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 77dc895648f3..a630aa8eb836 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -287,7 +287,7 @@ static void fw_conf_init(void) FWCfgState *fw_cfg; hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; - fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL); + fw_cfg = fw_cfg_init_mem_nodma(cfg_addr, cfg_addr + 8, 8); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, loaderparams.ram_size); -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> Factor fw_cfg_init_mem_internal() out of fw_cfg_init_mem_wide(). In fw_cfg_init_mem_wide(), assert DMA arguments are provided. Callers without DMA have to use the fw_cfg_init_mem() helper. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Fix a "typo" argument in fw_cfg_init_mem_wide(). --- hw/nvram/fw_cfg.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 2b8715679fe7..c65deeb7c382 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1054,9 +1054,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, return s; } -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as) +static FWCfgState *fw_cfg_init_mem_internal(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) { DeviceState *dev; SysBusDevice *sbd; @@ -1088,10 +1088,19 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, return s; } +FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) +{ + assert(dma_addr && dma_as); + return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_width, + dma_addr, dma_as); +} + FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width) { - return fw_cfg_init_mem_wide(ctl_addr, data_addr, data_width, 0, NULL); + return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_width, 0, NULL); } -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> "wide" in fw_cfg_init_mem_wide() means "DMA support". Rename for clarity. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Fix a missing case in hw/loongarch/fw_cfg.c. --- hw/arm/virt.c | 2 +- hw/loongarch/fw_cfg.c | 4 ++-- hw/nvram/fw_cfg.c | 6 +++--- hw/riscv/virt.c | 4 ++-- include/hw/nvram/fw_cfg.h | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 25fb2bab5680..23d88e2fd014 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1412,7 +1412,7 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) FWCfgState *fw_cfg; char *nodename; - fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); + fw_cfg = fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, as); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c index 493563669e5b..d2a79efbf767 100644 --- a/hw/loongarch/fw_cfg.c +++ b/hw/loongarch/fw_cfg.c @@ -23,8 +23,8 @@ FWCfgState *virt_fw_cfg_init(ram_addr_t ram_size, MachineState *ms) int max_cpus = ms->smp.max_cpus; int smp_cpus = ms->smp.cpus; - fw_cfg = fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8, - VIRT_FWCFG_BASE + 16, &address_space_memory); + fw_cfg = fw_cfg_init_mem_dma(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8, + VIRT_FWCFG_BASE + 16, &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index c65deeb7c382..3f0d337eb9c5 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1088,9 +1088,9 @@ static FWCfgState *fw_cfg_init_mem_internal(hwaddr ctl_addr, return s; } -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as) +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) { assert(dma_addr && dma_as); return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_width, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17909206c7ef..bfbb28f5bd26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1274,8 +1274,8 @@ static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; - fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, - &address_space_memory); + fw_cfg = fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, + &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index d5161a794362..c4c49886754c 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -309,9 +309,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as); +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as); FWCfgState *fw_cfg_find(void); bool fw_cfg_dma_enabled(void *opaque); -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The X86MachineClass::fwcfg_dma_enabled boolean was only used by the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Remove it and simplify. 'multiboot.bin' isn't used anymore, we'll remove it in the next commit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/microvm.c | 3 --- hw/i386/multiboot.c | 7 +------ hw/i386/x86-common.c | 3 +-- hw/i386/x86.c | 2 -- include/hw/i386/x86.h | 2 -- 5 files changed, 2 insertions(+), 15 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 94d22a232aca..812f2ac2f983 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -640,7 +640,6 @@ GlobalProperty microvm_properties[] = { static void microvm_class_init(ObjectClass *oc, const void *data) { - X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); MicrovmMachineClass *mmc = MICROVM_MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); @@ -674,8 +673,6 @@ static void microvm_class_init(ObjectClass *oc, const void *data) hc->unplug_request = microvm_device_unplug_request_cb; hc->unplug = microvm_device_unplug_cb; - x86mc->fwcfg_dma_enabled = true; - object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto", microvm_machine_get_rtc, microvm_machine_set_rtc, diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 78690781b74c..3b993126edb6 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -153,7 +153,6 @@ int load_multiboot(X86MachineState *x86ms, int kernel_file_size, uint8_t *header) { - bool multiboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; int i, is_multiboot = 0; uint32_t flags = 0; uint32_t mh_entry_addr; @@ -402,11 +401,7 @@ int load_multiboot(X86MachineState *x86ms, fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, mb_bootinfo_data, sizeof(bootinfo)); - if (multiboot_dma_enabled) { - option_rom[nb_option_roms].name = "multiboot_dma.bin"; - } else { - option_rom[nb_option_roms].name = "multiboot.bin"; - } + option_rom[nb_option_roms].name = "multiboot_dma.bin"; option_rom[nb_option_roms].bootindex = 0; nb_option_roms++; diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 60b7ab80433a..1ee55382dab8 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -645,7 +645,6 @@ void x86_load_linux(X86MachineState *x86ms, int acpi_data_size, bool pvh_enabled) { - bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; uint16_t protocol; int setup_size, kernel_size, cmdline_size; int dtb_size, setup_data_offset; @@ -1004,7 +1003,7 @@ void x86_load_linux(X86MachineState *x86ms, option_rom[nb_option_roms].bootindex = 0; option_rom[nb_option_roms].name = "linuxboot.bin"; - if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { + if (fw_cfg_dma_enabled(fw_cfg)) { option_rom[nb_option_roms].name = "linuxboot_dma.bin"; } nb_option_roms++; diff --git a/hw/i386/x86.c b/hw/i386/x86.c index f80533df1c54..dbf104d60af4 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -375,14 +375,12 @@ static void x86_machine_initfn(Object *obj) static void x86_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); - X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); mc->cpu_index_to_instance_props = x86_cpu_index_to_props; mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; mc->kvm_type = x86_kvm_type; - x86mc->fwcfg_dma_enabled = true; nc->nmi_monitor_handler = x86_nmi; object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 8755cad50a36..201eee80eb73 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -30,8 +30,6 @@ struct X86MachineClass { MachineClass parent; - /* use DMA capable linuxboot option rom */ - bool fwcfg_dma_enabled; /* CPU and apic information: */ bool apic_xrupt_override; }; -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> All PC machines now use the multiboot_dma.bin binary, we can remove the non-DMA version (multiboot.bin). This doesn't change multiboot_dma binary file. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * There's a recent change for multiboot.S: commit 4c8f69b94839. Rebase this patch on that. --- hw/i386/pc.c | 1 - pc-bios/meson.build | 1 - pc-bios/multiboot.bin | Bin 1024 -> 0 bytes pc-bios/optionrom/Makefile | 2 +- pc-bios/optionrom/multiboot.S | 232 ----------------------------- pc-bios/optionrom/multiboot_dma.S | 234 +++++++++++++++++++++++++++++- pc-bios/optionrom/optionrom.h | 4 - 7 files changed, 233 insertions(+), 241 deletions(-) delete mode 100644 pc-bios/multiboot.bin delete mode 100644 pc-bios/optionrom/multiboot.S diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2b8d3982c4a0..9d88d4a5207a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -669,7 +669,6 @@ void xen_load_linux(PCMachineState *pcms) assert(!strcmp(option_rom[i].name, "linuxboot.bin") || !strcmp(option_rom[i].name, "linuxboot_dma.bin") || !strcmp(option_rom[i].name, "pvh.bin") || - !strcmp(option_rom[i].name, "multiboot.bin") || !strcmp(option_rom[i].name, "multiboot_dma.bin")); rom_add_option(option_rom[i].name, option_rom[i].bootindex); } diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 9260aaad78e8..efe45c16705d 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -62,7 +62,6 @@ blobs = [ 'efi-e1000e.rom', 'efi-vmxnet3.rom', 'qemu-nsis.bmp', - 'multiboot.bin', 'multiboot_dma.bin', 'linuxboot.bin', 'linuxboot_dma.bin', diff --git a/pc-bios/multiboot.bin b/pc-bios/multiboot.bin deleted file mode 100644 index e772713c95749bee82c20002b50ec6d05b2d4987..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1024 zcmeHFF-Tic6utlZQ$OjD#Hxcx2u0GNQv6GySOkZR(ulaX<>%N!Y#>cWhY}nf36J7X zN(%*X6NHY>xcqO11dG^02a8L@B~ihln|%1*|7(haWa`)l@80w7;U4Ziyv0rZ8{K-w zX(Ib3tLZ)RgZ}w1ei{~QEqQq9q1J-iHc<Nk_t=0qf%XfPZVHw2DY#ujc2P|}*P%6X z5J{pPlX4<yP&N5pXK;s@UhB~&!E&UdqEwGZF6xQMIcu9YL#zeSRCoLGt{Nh+08t>} z{m%E-b32A??+@XljSYirtWObwngi<ymS1Ta*dFGMp;8@=_3Z52!v09{UU~`QnFsB_ z7BiEC)uZxH%SW9kPWCicN{_iUjmk<~D^H|R%@|m9%43Woc(Pkeq%n{&8ND5Z*tPt# zJua+xXAQhN4K(1MMs0{u_6sp>l#NmvPZ7KC<lsLdQgMFC@A6POvMoDMgW=M+K;T<o zTkpnNq6x*`vM0CGE>t40l-CQ}*)y<y--c)(x}o&1TMzwX+ToGS@VER4zR&s70fl+( qI)9<-H_-!n#lLJmGq*^~<$US&%R-@)$`@YPx#A6#|L`9<;9UXPG71m? diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile index 30d07026c790..1183ef889228 100644 --- a/pc-bios/optionrom/Makefile +++ b/pc-bios/optionrom/Makefile @@ -2,7 +2,7 @@ include config.mak SRC_DIR := $(TOPSRC_DIR)/pc-bios/optionrom VPATH = $(SRC_DIR) -all: multiboot.bin multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin +all: multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin # Dummy command so that make thinks it has done something @true diff --git a/pc-bios/optionrom/multiboot.S b/pc-bios/optionrom/multiboot.S deleted file mode 100644 index c95e35c9cb62..000000000000 --- a/pc-bios/optionrom/multiboot.S +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Multiboot Option ROM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Copyright Novell Inc, 2009 - * Authors: Alexander Graf <agraf@suse.de> - */ - -#include "optionrom.h" - -#define BOOT_ROM_PRODUCT "multiboot loader" - -#define MULTIBOOT_MAGIC 0x2badb002 - -#define GS_PROT_JUMP 0 -#define GS_GDT_DESC 6 - - -BOOT_ROM_START - -run_multiboot: - - cli - cld - - mov %cs, %eax - shl $0x4, %eax - - /* set up a long jump descriptor that is PC relative */ - - /* move stack memory to %gs */ - mov %ss, %ecx - shl $0x4, %ecx - mov %esp, %ebx - add %ebx, %ecx - sub $0x20, %ecx - sub $0x30, %esp - shr $0x4, %ecx - mov %cx, %gs - - /* now push the indirect jump descriptor there */ - mov (prot_jump), %ebx - add %eax, %ebx - movl %ebx, %gs:GS_PROT_JUMP - mov $8, %bx - movw %bx, %gs:GS_PROT_JUMP + 4 - - /* fix the gdt descriptor to be PC relative */ - movw (gdt_desc), %bx - movw %bx, %gs:GS_GDT_DESC - movl (gdt_desc+2), %ebx - add %eax, %ebx - movl %ebx, %gs:GS_GDT_DESC + 2 - - xor %eax, %eax - mov %eax, %es - - /* Read the bootinfo struct into RAM */ - read_fw_blob_dma(FW_CFG_INITRD) - - /* FS = bootinfo_struct */ - read_fw FW_CFG_INITRD_ADDR - shr $4, %eax - mov %ax, %fs - - /* Account for the EBDA in the multiboot structure's e801 - * map. - */ - int $0x12 - cwtl - movl %eax, %fs:4 - - /* ES = mmap_addr */ - mov %fs:48, %eax - shr $4, %eax - mov %ax, %es - - /* Initialize multiboot mmap structs using int 0x15(e820) */ - xor %ebx, %ebx - /* Start storing mmap data at %es:0 */ - xor %edi, %edi - -mmap_loop: - /* The multiboot entry size has offset -4, so leave some space */ - add $4, %di - /* entry size (mmap struct) & max buffer size (int15) */ - movl $20, %ecx - /* e820 */ - movl $0x0000e820, %eax - /* 'SMAP' magic */ - movl $0x534d4150, %edx - int $0x15 - -mmap_check_entry: - /* Error or last entry already done? */ - jb mmap_done - -mmap_store_entry: - /* store entry size */ - /* old as(1) doesn't like this insn so emit the bytes instead: - movl %ecx, %es:-4(%edi) - */ - .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc - - /* %edi += entry_size, store as mbs_mmap_length */ - add %ecx, %edi - movw %di, %fs:0x2c - - /* Continuation value 0 means last entry */ - test %ebx, %ebx - jnz mmap_loop - -mmap_done: - /* Calculate upper_mem field: The amount of memory between 1 MB and - the first upper memory hole. Get it from the mmap. */ - xor %di, %di - mov $0x100000, %edx -upper_mem_entry: - cmp %fs:0x2c, %di - je upper_mem_done - add $4, %di - - /* Skip if type != 1 */ - cmpl $1, %es:16(%di) - jne upper_mem_next - - /* Skip if > 4 GB */ - movl %es:4(%di), %eax - test %eax, %eax - jnz upper_mem_next - - /* Check for contiguous extension (base <= %edx < base + length) */ - movl %es:(%di), %eax - cmp %eax, %edx - jb upper_mem_next - addl %es:8(%di), %eax - cmp %eax, %edx - jae upper_mem_next - - /* If so, update %edx, and restart the search (mmap isn't ordered) */ - mov %eax, %edx - xor %di, %di - jmp upper_mem_entry - -upper_mem_next: - addl %es:-4(%di), %edi - jmp upper_mem_entry - -upper_mem_done: - sub $0x100000, %edx - shr $10, %edx - mov %edx, %fs:0x8 - -real_to_prot: - /* Load the GDT before going into protected mode */ -lgdt: - data32 lgdt %gs:GS_GDT_DESC - - /* get us to protected mode now */ - movl $1, %eax - movl %eax, %cr0 - - /* the LJMP sets CS for us and gets us to 32-bit */ -ljmp: - data32 ljmp *%gs:GS_PROT_JUMP - -prot_mode: -.code32 - - /* initialize all other segments */ - movl $0x10, %eax - movl %eax, %ss - movl %eax, %ds - movl %eax, %es - movl %eax, %fs - movl %eax, %gs - - /* Read the kernel and modules into RAM */ - read_fw_blob_dma(FW_CFG_KERNEL) - - /* Jump off to the kernel */ - read_fw FW_CFG_KERNEL_ENTRY - mov %eax, %ecx - - /* EBX contains a pointer to the bootinfo struct */ - read_fw FW_CFG_INITRD_ADDR - movl %eax, %ebx - - /* EAX has to contain the magic */ - movl $MULTIBOOT_MAGIC, %eax -ljmp2: - jmp *%ecx - -/* Variables */ -.align 4, 0 -prot_jump: .long prot_mode - .short 8 - -.align 8, 0 -gdt: - /* 0x00 */ -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - - /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 - - /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 - - /* 0x18: code segment (base=0, limit=0x0ffff, type=16bit code exec/read/conf, DPL=0, 1b) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00 - - /* 0x20: data segment (base=0, limit=0x0ffff, type=16bit data read/write, DPL=0, 1b) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0x00, 0x00 - -gdt_desc: -.short (5 * 8) - 1 -.long gdt - -BOOT_ROM_END diff --git a/pc-bios/optionrom/multiboot_dma.S b/pc-bios/optionrom/multiboot_dma.S index d809af3e23fc..c95e35c9cb62 100644 --- a/pc-bios/optionrom/multiboot_dma.S +++ b/pc-bios/optionrom/multiboot_dma.S @@ -1,2 +1,232 @@ -#define USE_FW_CFG_DMA 1 -#include "multiboot.S" +/* + * Multiboot Option ROM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + * + * Copyright Novell Inc, 2009 + * Authors: Alexander Graf <agraf@suse.de> + */ + +#include "optionrom.h" + +#define BOOT_ROM_PRODUCT "multiboot loader" + +#define MULTIBOOT_MAGIC 0x2badb002 + +#define GS_PROT_JUMP 0 +#define GS_GDT_DESC 6 + + +BOOT_ROM_START + +run_multiboot: + + cli + cld + + mov %cs, %eax + shl $0x4, %eax + + /* set up a long jump descriptor that is PC relative */ + + /* move stack memory to %gs */ + mov %ss, %ecx + shl $0x4, %ecx + mov %esp, %ebx + add %ebx, %ecx + sub $0x20, %ecx + sub $0x30, %esp + shr $0x4, %ecx + mov %cx, %gs + + /* now push the indirect jump descriptor there */ + mov (prot_jump), %ebx + add %eax, %ebx + movl %ebx, %gs:GS_PROT_JUMP + mov $8, %bx + movw %bx, %gs:GS_PROT_JUMP + 4 + + /* fix the gdt descriptor to be PC relative */ + movw (gdt_desc), %bx + movw %bx, %gs:GS_GDT_DESC + movl (gdt_desc+2), %ebx + add %eax, %ebx + movl %ebx, %gs:GS_GDT_DESC + 2 + + xor %eax, %eax + mov %eax, %es + + /* Read the bootinfo struct into RAM */ + read_fw_blob_dma(FW_CFG_INITRD) + + /* FS = bootinfo_struct */ + read_fw FW_CFG_INITRD_ADDR + shr $4, %eax + mov %ax, %fs + + /* Account for the EBDA in the multiboot structure's e801 + * map. + */ + int $0x12 + cwtl + movl %eax, %fs:4 + + /* ES = mmap_addr */ + mov %fs:48, %eax + shr $4, %eax + mov %ax, %es + + /* Initialize multiboot mmap structs using int 0x15(e820) */ + xor %ebx, %ebx + /* Start storing mmap data at %es:0 */ + xor %edi, %edi + +mmap_loop: + /* The multiboot entry size has offset -4, so leave some space */ + add $4, %di + /* entry size (mmap struct) & max buffer size (int15) */ + movl $20, %ecx + /* e820 */ + movl $0x0000e820, %eax + /* 'SMAP' magic */ + movl $0x534d4150, %edx + int $0x15 + +mmap_check_entry: + /* Error or last entry already done? */ + jb mmap_done + +mmap_store_entry: + /* store entry size */ + /* old as(1) doesn't like this insn so emit the bytes instead: + movl %ecx, %es:-4(%edi) + */ + .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc + + /* %edi += entry_size, store as mbs_mmap_length */ + add %ecx, %edi + movw %di, %fs:0x2c + + /* Continuation value 0 means last entry */ + test %ebx, %ebx + jnz mmap_loop + +mmap_done: + /* Calculate upper_mem field: The amount of memory between 1 MB and + the first upper memory hole. Get it from the mmap. */ + xor %di, %di + mov $0x100000, %edx +upper_mem_entry: + cmp %fs:0x2c, %di + je upper_mem_done + add $4, %di + + /* Skip if type != 1 */ + cmpl $1, %es:16(%di) + jne upper_mem_next + + /* Skip if > 4 GB */ + movl %es:4(%di), %eax + test %eax, %eax + jnz upper_mem_next + + /* Check for contiguous extension (base <= %edx < base + length) */ + movl %es:(%di), %eax + cmp %eax, %edx + jb upper_mem_next + addl %es:8(%di), %eax + cmp %eax, %edx + jae upper_mem_next + + /* If so, update %edx, and restart the search (mmap isn't ordered) */ + mov %eax, %edx + xor %di, %di + jmp upper_mem_entry + +upper_mem_next: + addl %es:-4(%di), %edi + jmp upper_mem_entry + +upper_mem_done: + sub $0x100000, %edx + shr $10, %edx + mov %edx, %fs:0x8 + +real_to_prot: + /* Load the GDT before going into protected mode */ +lgdt: + data32 lgdt %gs:GS_GDT_DESC + + /* get us to protected mode now */ + movl $1, %eax + movl %eax, %cr0 + + /* the LJMP sets CS for us and gets us to 32-bit */ +ljmp: + data32 ljmp *%gs:GS_PROT_JUMP + +prot_mode: +.code32 + + /* initialize all other segments */ + movl $0x10, %eax + movl %eax, %ss + movl %eax, %ds + movl %eax, %es + movl %eax, %fs + movl %eax, %gs + + /* Read the kernel and modules into RAM */ + read_fw_blob_dma(FW_CFG_KERNEL) + + /* Jump off to the kernel */ + read_fw FW_CFG_KERNEL_ENTRY + mov %eax, %ecx + + /* EBX contains a pointer to the bootinfo struct */ + read_fw FW_CFG_INITRD_ADDR + movl %eax, %ebx + + /* EAX has to contain the magic */ + movl $MULTIBOOT_MAGIC, %eax +ljmp2: + jmp *%ecx + +/* Variables */ +.align 4, 0 +prot_jump: .long prot_mode + .short 8 + +.align 8, 0 +gdt: + /* 0x00 */ +.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + + /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 + + /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 + + /* 0x18: code segment (base=0, limit=0x0ffff, type=16bit code exec/read/conf, DPL=0, 1b) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00 + + /* 0x20: data segment (base=0, limit=0x0ffff, type=16bit data read/write, DPL=0, 1b) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0x00, 0x00 + +gdt_desc: +.short (5 * 8) - 1 +.long gdt + +BOOT_ROM_END diff --git a/pc-bios/optionrom/optionrom.h b/pc-bios/optionrom/optionrom.h index 7bcdf0eeb240..2e6e2493f83f 100644 --- a/pc-bios/optionrom/optionrom.h +++ b/pc-bios/optionrom/optionrom.h @@ -117,16 +117,12 @@ * * Clobbers: %eax, %edx, %es, %ecx, %edi and adresses %esp-20 to %esp */ -#ifdef USE_FW_CFG_DMA #define read_fw_blob_dma(var) \ read_fw var ## _SIZE; \ mov %eax, %ecx; \ read_fw var ## _ADDR; \ mov %eax, %edi ; \ read_fw_dma var ## _DATA, %ecx, %edi -#else -#define read_fw_blob_dma(var) read_fw_blob(var) -#endif #define read_fw_blob_pre(var) \ read_fw var ## _SIZE; \ -- 2.34.1
On Wed, 3 Dec 2025 00:28:21 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
All PC machines now use the multiboot_dma.bin binary, we can remove the non-DMA version (multiboot.bin).
This doesn't change multiboot_dma binary file.
Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- Changes since v4: * There's a recent change for multiboot.S: commit 4c8f69b94839. Rebase this patch on that. --- hw/i386/pc.c | 1 - pc-bios/meson.build | 1 - pc-bios/multiboot.bin | Bin 1024 -> 0 bytes pc-bios/optionrom/Makefile | 2 +- pc-bios/optionrom/multiboot.S | 232 ----------------------------- pc-bios/optionrom/multiboot_dma.S | 234 +++++++++++++++++++++++++++++- pc-bios/optionrom/optionrom.h | 4 - 7 files changed, 233 insertions(+), 241 deletions(-) delete mode 100644 pc-bios/multiboot.bin delete mode 100644 pc-bios/optionrom/multiboot.S
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2b8d3982c4a0..9d88d4a5207a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -669,7 +669,6 @@ void xen_load_linux(PCMachineState *pcms) assert(!strcmp(option_rom[i].name, "linuxboot.bin") || !strcmp(option_rom[i].name, "linuxboot_dma.bin") || !strcmp(option_rom[i].name, "pvh.bin") || - !strcmp(option_rom[i].name, "multiboot.bin") || !strcmp(option_rom[i].name, "multiboot_dma.bin")); rom_add_option(option_rom[i].name, option_rom[i].bootindex); } diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 9260aaad78e8..efe45c16705d 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -62,7 +62,6 @@ blobs = [ 'efi-e1000e.rom', 'efi-vmxnet3.rom', 'qemu-nsis.bmp', - 'multiboot.bin', 'multiboot_dma.bin', 'linuxboot.bin', 'linuxboot_dma.bin', diff --git a/pc-bios/multiboot.bin b/pc-bios/multiboot.bin deleted file mode 100644 index e772713c95749bee82c20002b50ec6d05b2d4987..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
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diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile index 30d07026c790..1183ef889228 100644 --- a/pc-bios/optionrom/Makefile +++ b/pc-bios/optionrom/Makefile @@ -2,7 +2,7 @@ include config.mak SRC_DIR := $(TOPSRC_DIR)/pc-bios/optionrom VPATH = $(SRC_DIR)
-all: multiboot.bin multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin +all: multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin # Dummy command so that make thinks it has done something @true
diff --git a/pc-bios/optionrom/multiboot.S b/pc-bios/optionrom/multiboot.S deleted file mode 100644 index c95e35c9cb62..000000000000 --- a/pc-bios/optionrom/multiboot.S +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Multiboot Option ROM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Copyright Novell Inc, 2009 - * Authors: Alexander Graf <agraf@suse.de> - */ - -#include "optionrom.h" - -#define BOOT_ROM_PRODUCT "multiboot loader" - -#define MULTIBOOT_MAGIC 0x2badb002 - -#define GS_PROT_JUMP 0 -#define GS_GDT_DESC 6 - - -BOOT_ROM_START - -run_multiboot: - - cli - cld - - mov %cs, %eax - shl $0x4, %eax - - /* set up a long jump descriptor that is PC relative */ - - /* move stack memory to %gs */ - mov %ss, %ecx - shl $0x4, %ecx - mov %esp, %ebx - add %ebx, %ecx - sub $0x20, %ecx - sub $0x30, %esp - shr $0x4, %ecx - mov %cx, %gs - - /* now push the indirect jump descriptor there */ - mov (prot_jump), %ebx - add %eax, %ebx - movl %ebx, %gs:GS_PROT_JUMP - mov $8, %bx - movw %bx, %gs:GS_PROT_JUMP + 4 - - /* fix the gdt descriptor to be PC relative */ - movw (gdt_desc), %bx - movw %bx, %gs:GS_GDT_DESC - movl (gdt_desc+2), %ebx - add %eax, %ebx - movl %ebx, %gs:GS_GDT_DESC + 2 - - xor %eax, %eax - mov %eax, %es - - /* Read the bootinfo struct into RAM */ - read_fw_blob_dma(FW_CFG_INITRD) - - /* FS = bootinfo_struct */ - read_fw FW_CFG_INITRD_ADDR - shr $4, %eax - mov %ax, %fs - - /* Account for the EBDA in the multiboot structure's e801 - * map. - */ - int $0x12 - cwtl - movl %eax, %fs:4 - - /* ES = mmap_addr */ - mov %fs:48, %eax - shr $4, %eax - mov %ax, %es - - /* Initialize multiboot mmap structs using int 0x15(e820) */ - xor %ebx, %ebx - /* Start storing mmap data at %es:0 */ - xor %edi, %edi - -mmap_loop: - /* The multiboot entry size has offset -4, so leave some space */ - add $4, %di - /* entry size (mmap struct) & max buffer size (int15) */ - movl $20, %ecx - /* e820 */ - movl $0x0000e820, %eax - /* 'SMAP' magic */ - movl $0x534d4150, %edx - int $0x15 - -mmap_check_entry: - /* Error or last entry already done? */ - jb mmap_done - -mmap_store_entry: - /* store entry size */ - /* old as(1) doesn't like this insn so emit the bytes instead: - movl %ecx, %es:-4(%edi) - */ - .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc - - /* %edi += entry_size, store as mbs_mmap_length */ - add %ecx, %edi - movw %di, %fs:0x2c - - /* Continuation value 0 means last entry */ - test %ebx, %ebx - jnz mmap_loop - -mmap_done: - /* Calculate upper_mem field: The amount of memory between 1 MB and - the first upper memory hole. Get it from the mmap. */ - xor %di, %di - mov $0x100000, %edx -upper_mem_entry: - cmp %fs:0x2c, %di - je upper_mem_done - add $4, %di - - /* Skip if type != 1 */ - cmpl $1, %es:16(%di) - jne upper_mem_next - - /* Skip if > 4 GB */ - movl %es:4(%di), %eax - test %eax, %eax - jnz upper_mem_next - - /* Check for contiguous extension (base <= %edx < base + length) */ - movl %es:(%di), %eax - cmp %eax, %edx - jb upper_mem_next - addl %es:8(%di), %eax - cmp %eax, %edx - jae upper_mem_next - - /* If so, update %edx, and restart the search (mmap isn't ordered) */ - mov %eax, %edx - xor %di, %di - jmp upper_mem_entry - -upper_mem_next: - addl %es:-4(%di), %edi - jmp upper_mem_entry - -upper_mem_done: - sub $0x100000, %edx - shr $10, %edx - mov %edx, %fs:0x8 - -real_to_prot: - /* Load the GDT before going into protected mode */ -lgdt: - data32 lgdt %gs:GS_GDT_DESC - - /* get us to protected mode now */ - movl $1, %eax - movl %eax, %cr0 - - /* the LJMP sets CS for us and gets us to 32-bit */ -ljmp: - data32 ljmp *%gs:GS_PROT_JUMP - -prot_mode: -.code32 - - /* initialize all other segments */ - movl $0x10, %eax - movl %eax, %ss - movl %eax, %ds - movl %eax, %es - movl %eax, %fs - movl %eax, %gs - - /* Read the kernel and modules into RAM */ - read_fw_blob_dma(FW_CFG_KERNEL) - - /* Jump off to the kernel */ - read_fw FW_CFG_KERNEL_ENTRY - mov %eax, %ecx - - /* EBX contains a pointer to the bootinfo struct */ - read_fw FW_CFG_INITRD_ADDR - movl %eax, %ebx - - /* EAX has to contain the magic */ - movl $MULTIBOOT_MAGIC, %eax -ljmp2: - jmp *%ecx - -/* Variables */ -.align 4, 0 -prot_jump: .long prot_mode - .short 8 - -.align 8, 0 -gdt: - /* 0x00 */ -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - - /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 - - /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 - - /* 0x18: code segment (base=0, limit=0x0ffff, type=16bit code exec/read/conf, DPL=0, 1b) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00 - - /* 0x20: data segment (base=0, limit=0x0ffff, type=16bit data read/write, DPL=0, 1b) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0x00, 0x00 - -gdt_desc: -.short (5 * 8) - 1 -.long gdt - -BOOT_ROM_END diff --git a/pc-bios/optionrom/multiboot_dma.S b/pc-bios/optionrom/multiboot_dma.S index d809af3e23fc..c95e35c9cb62 100644 --- a/pc-bios/optionrom/multiboot_dma.S +++ b/pc-bios/optionrom/multiboot_dma.S @@ -1,2 +1,232 @@ -#define USE_FW_CFG_DMA 1 -#include "multiboot.S" +/* + * Multiboot Option ROM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + * + * Copyright Novell Inc, 2009 + * Authors: Alexander Graf <agraf@suse.de> + */ + +#include "optionrom.h" + +#define BOOT_ROM_PRODUCT "multiboot loader" + +#define MULTIBOOT_MAGIC 0x2badb002 + +#define GS_PROT_JUMP 0 +#define GS_GDT_DESC 6 + + +BOOT_ROM_START + +run_multiboot: + + cli + cld + + mov %cs, %eax + shl $0x4, %eax + + /* set up a long jump descriptor that is PC relative */ + + /* move stack memory to %gs */ + mov %ss, %ecx + shl $0x4, %ecx + mov %esp, %ebx + add %ebx, %ecx + sub $0x20, %ecx + sub $0x30, %esp + shr $0x4, %ecx + mov %cx, %gs + + /* now push the indirect jump descriptor there */ + mov (prot_jump), %ebx + add %eax, %ebx + movl %ebx, %gs:GS_PROT_JUMP + mov $8, %bx + movw %bx, %gs:GS_PROT_JUMP + 4 + + /* fix the gdt descriptor to be PC relative */ + movw (gdt_desc), %bx + movw %bx, %gs:GS_GDT_DESC + movl (gdt_desc+2), %ebx + add %eax, %ebx + movl %ebx, %gs:GS_GDT_DESC + 2 + + xor %eax, %eax + mov %eax, %es + + /* Read the bootinfo struct into RAM */ + read_fw_blob_dma(FW_CFG_INITRD) + + /* FS = bootinfo_struct */ + read_fw FW_CFG_INITRD_ADDR + shr $4, %eax + mov %ax, %fs + + /* Account for the EBDA in the multiboot structure's e801 + * map. + */ + int $0x12 + cwtl + movl %eax, %fs:4 + + /* ES = mmap_addr */ + mov %fs:48, %eax + shr $4, %eax + mov %ax, %es + + /* Initialize multiboot mmap structs using int 0x15(e820) */ + xor %ebx, %ebx + /* Start storing mmap data at %es:0 */ + xor %edi, %edi + +mmap_loop: + /* The multiboot entry size has offset -4, so leave some space */ + add $4, %di + /* entry size (mmap struct) & max buffer size (int15) */ + movl $20, %ecx + /* e820 */ + movl $0x0000e820, %eax + /* 'SMAP' magic */ + movl $0x534d4150, %edx + int $0x15 + +mmap_check_entry: + /* Error or last entry already done? */ + jb mmap_done + +mmap_store_entry: + /* store entry size */ + /* old as(1) doesn't like this insn so emit the bytes instead: + movl %ecx, %es:-4(%edi) + */ + .dc.b 0x26,0x67,0x66,0x89,0x4f,0xfc + + /* %edi += entry_size, store as mbs_mmap_length */ + add %ecx, %edi + movw %di, %fs:0x2c + + /* Continuation value 0 means last entry */ + test %ebx, %ebx + jnz mmap_loop + +mmap_done: + /* Calculate upper_mem field: The amount of memory between 1 MB and + the first upper memory hole. Get it from the mmap. */ + xor %di, %di + mov $0x100000, %edx +upper_mem_entry: + cmp %fs:0x2c, %di + je upper_mem_done + add $4, %di + + /* Skip if type != 1 */ + cmpl $1, %es:16(%di) + jne upper_mem_next + + /* Skip if > 4 GB */ + movl %es:4(%di), %eax + test %eax, %eax + jnz upper_mem_next + + /* Check for contiguous extension (base <= %edx < base + length) */ + movl %es:(%di), %eax + cmp %eax, %edx + jb upper_mem_next + addl %es:8(%di), %eax + cmp %eax, %edx + jae upper_mem_next + + /* If so, update %edx, and restart the search (mmap isn't ordered) */ + mov %eax, %edx + xor %di, %di + jmp upper_mem_entry + +upper_mem_next: + addl %es:-4(%di), %edi + jmp upper_mem_entry + +upper_mem_done: + sub $0x100000, %edx + shr $10, %edx + mov %edx, %fs:0x8 + +real_to_prot: + /* Load the GDT before going into protected mode */ +lgdt: + data32 lgdt %gs:GS_GDT_DESC + + /* get us to protected mode now */ + movl $1, %eax + movl %eax, %cr0 + + /* the LJMP sets CS for us and gets us to 32-bit */ +ljmp: + data32 ljmp *%gs:GS_PROT_JUMP + +prot_mode: +.code32 + + /* initialize all other segments */ + movl $0x10, %eax + movl %eax, %ss + movl %eax, %ds + movl %eax, %es + movl %eax, %fs + movl %eax, %gs + + /* Read the kernel and modules into RAM */ + read_fw_blob_dma(FW_CFG_KERNEL) + + /* Jump off to the kernel */ + read_fw FW_CFG_KERNEL_ENTRY + mov %eax, %ecx + + /* EBX contains a pointer to the bootinfo struct */ + read_fw FW_CFG_INITRD_ADDR + movl %eax, %ebx + + /* EAX has to contain the magic */ + movl $MULTIBOOT_MAGIC, %eax +ljmp2: + jmp *%ecx + +/* Variables */ +.align 4, 0 +prot_jump: .long prot_mode + .short 8 + +.align 8, 0 +gdt: + /* 0x00 */ +.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + + /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 + + /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 + + /* 0x18: code segment (base=0, limit=0x0ffff, type=16bit code exec/read/conf, DPL=0, 1b) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00 + + /* 0x20: data segment (base=0, limit=0x0ffff, type=16bit data read/write, DPL=0, 1b) */ +.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0x00, 0x00 + +gdt_desc: +.short (5 * 8) - 1 +.long gdt + +BOOT_ROM_END diff --git a/pc-bios/optionrom/optionrom.h b/pc-bios/optionrom/optionrom.h index 7bcdf0eeb240..2e6e2493f83f 100644 --- a/pc-bios/optionrom/optionrom.h +++ b/pc-bios/optionrom/optionrom.h @@ -117,16 +117,12 @@ * * Clobbers: %eax, %edx, %es, %ecx, %edi and adresses %esp-20 to %esp */ -#ifdef USE_FW_CFG_DMA #define read_fw_blob_dma(var) \ read_fw var ## _SIZE; \ mov %eax, %ecx; \ read_fw var ## _ADDR; \ mov %eax, %edi ; \ read_fw_dma var ## _DATA, %ecx, %edi -#else -#define read_fw_blob_dma(var) read_fw_blob(var) -#endif
#define read_fw_blob_pre(var) \ read_fw var ## _SIZE; \
From: Philippe Mathieu-Daudé <philmd@linaro.org> Now all calls of x86 machines to fw_cfg_init_io_dma() pass DMA arguments, so the FWCfgState (FWCfgIoState) created by x86 machines enables DMA by default. Although other callers of fw_cfg_init_io_dma() besides x86 also pass DMA arguments to create DMA-enabled FwCfgIoState, the "dma_enabled" property of FwCfgIoState cannot yet be removed, because Sun4u and Sun4v still create DMA-disabled FwCfgIoState (bypass fw_cfg_init_io_dma()) in sun4uv_init() (hw/sparc64/sun4u.c). Maybe reusing fw_cfg_init_io_dma() for them would be a better choice, or adding fw_cfg_init_io_nodma(). However, before that, first simplify the handling of FwCfgState in x86. Considering that FwCfgIoState in x86 enables DMA by default, remove the handling for DMA-disabled cases and replace DMA checks with assertions to ensure that the default DMA-enabled setting is not broken. Then 'linuxboot.bin' isn't used anymore, and it will be removed in the next commit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Keep "dma_enabled" property in fw_cfg_io_properties[]. * Replace DMA checks with assertions for x86 machines. --- hw/i386/fw_cfg.c | 16 ++++++++-------- hw/i386/x86-common.c | 6 ++---- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 5c0bcd5f8a9f..5670e8553eaa 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -215,18 +215,18 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) #ifdef CONFIG_ACPI void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) { + uint8_t io_size; + Aml *dev = aml_device("FWCF"); + Aml *crs = aml_resource_template(); + /* * when using port i/o, the 8-bit data register *always* overlaps * with half of the 16-bit control register. Hence, the total size - * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the - * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 + * of the i/o region used is FW_CFG_CTL_SIZE; And the DMA control + * register is located at FW_CFG_DMA_IO_BASE + 4 */ - Object *obj = OBJECT(fw_cfg); - uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? - ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : - FW_CFG_CTL_SIZE; - Aml *dev = aml_device("FWCF"); - Aml *crs = aml_resource_template(); + assert(fw_cfg_dma_enabled(fw_cfg)); + io_size = ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t); aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 1ee55382dab8..e8dc4d903bd6 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -1002,10 +1002,8 @@ void x86_load_linux(X86MachineState *x86ms, } option_rom[nb_option_roms].bootindex = 0; - option_rom[nb_option_roms].name = "linuxboot.bin"; - if (fw_cfg_dma_enabled(fw_cfg)) { - option_rom[nb_option_roms].name = "linuxboot_dma.bin"; - } + assert(fw_cfg_dma_enabled(fw_cfg)); + option_rom[nb_option_roms].name = "linuxboot_dma.bin"; nb_option_roms++; } -- 2.34.1
On 2/12/25 17:28, Zhao Liu wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Now all calls of x86 machines to fw_cfg_init_io_dma() pass DMA arguments, so the FWCfgState (FWCfgIoState) created by x86 machines enables DMA by default.
Although other callers of fw_cfg_init_io_dma() besides x86 also pass DMA arguments to create DMA-enabled FwCfgIoState, the "dma_enabled" property of FwCfgIoState cannot yet be removed, because Sun4u and Sun4v still create DMA-disabled FwCfgIoState (bypass fw_cfg_init_io_dma()) in sun4uv_init() (hw/sparc64/sun4u.c).
Maybe reusing fw_cfg_init_io_dma() for them would be a better choice, or adding fw_cfg_init_io_nodma(). However, before that, first simplify the handling of FwCfgState in x86.
I answered these concerns here: https://lore.kernel.org/qemu-devel/20251203060942.57851-1-philmd@linaro.org/
Considering that FwCfgIoState in x86 enables DMA by default, remove the handling for DMA-disabled cases and replace DMA checks with assertions to ensure that the default DMA-enabled setting is not broken.
Then 'linuxboot.bin' isn't used anymore, and it will be removed in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Keep "dma_enabled" property in fw_cfg_io_properties[]. * Replace DMA checks with assertions for x86 machines. --- hw/i386/fw_cfg.c | 16 ++++++++-------- hw/i386/x86-common.c | 6 ++---- 2 files changed, 10 insertions(+), 12 deletions(-)
On Wed, 3 Dec 2025 00:28:22 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Now all calls of x86 machines to fw_cfg_init_io_dma() pass DMA arguments, so the FWCfgState (FWCfgIoState) created by x86 machines enables DMA by default.
Although other callers of fw_cfg_init_io_dma() besides x86 also pass DMA arguments to create DMA-enabled FwCfgIoState, the "dma_enabled" property of FwCfgIoState cannot yet be removed, because Sun4u and Sun4v still create DMA-disabled FwCfgIoState (bypass fw_cfg_init_io_dma()) in sun4uv_init() (hw/sparc64/sun4u.c).
Maybe reusing fw_cfg_init_io_dma() for them would be a better choice, or adding fw_cfg_init_io_nodma(). However, before that, first simplify the handling of FwCfgState in x86.
Considering that FwCfgIoState in x86 enables DMA by default, remove the handling for DMA-disabled cases and replace DMA checks with assertions to ensure that the default DMA-enabled setting is not broken.
Then 'linuxboot.bin' isn't used anymore, and it will be removed in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Keep "dma_enabled" property in fw_cfg_io_properties[]. * Replace DMA checks with assertions for x86 machines. --- hw/i386/fw_cfg.c | 16 ++++++++-------- hw/i386/x86-common.c | 6 ++---- 2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 5c0bcd5f8a9f..5670e8553eaa 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -215,18 +215,18 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) #ifdef CONFIG_ACPI void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) { + uint8_t io_size; + Aml *dev = aml_device("FWCF"); + Aml *crs = aml_resource_template(); + /* * when using port i/o, the 8-bit data register *always* overlaps * with half of the 16-bit control register. Hence, the total size - * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the - * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 + * of the i/o region used is FW_CFG_CTL_SIZE; And the DMA control + * register is located at FW_CFG_DMA_IO_BASE + 4 */ - Object *obj = OBJECT(fw_cfg); - uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? - ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : - FW_CFG_CTL_SIZE; - Aml *dev = aml_device("FWCF"); - Aml *crs = aml_resource_template(); + assert(fw_cfg_dma_enabled(fw_cfg));
this was supposed to be machine agnostic, but given that it only used by x86 it shouldn't cause issues, so Acked-by: Igor Mammedov <imammedo@redhat.com>
+ io_size = ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t);
aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 1ee55382dab8..e8dc4d903bd6 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -1002,10 +1002,8 @@ void x86_load_linux(X86MachineState *x86ms, }
option_rom[nb_option_roms].bootindex = 0; - option_rom[nb_option_roms].name = "linuxboot.bin"; - if (fw_cfg_dma_enabled(fw_cfg)) { - option_rom[nb_option_roms].name = "linuxboot_dma.bin"; - } + assert(fw_cfg_dma_enabled(fw_cfg)); + option_rom[nb_option_roms].name = "linuxboot_dma.bin"; nb_option_roms++; }
From: Philippe Mathieu-Daudé <philmd@linaro.org> All machines now use the linuxboot_dma.bin binary, so it's safe to remove the non-DMA version (linuxboot.bin). Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Update commit message: not only pc, but also microvm enables DMA for FwCfgState (in microvm_memory_init). --- hw/i386/pc.c | 3 +- pc-bios/meson.build | 1 - pc-bios/optionrom/Makefile | 2 +- pc-bios/optionrom/linuxboot.S | 195 ---------------------------------- 4 files changed, 2 insertions(+), 199 deletions(-) delete mode 100644 pc-bios/optionrom/linuxboot.S diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9d88d4a5207a..2e315414aeaf 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -666,8 +666,7 @@ void xen_load_linux(PCMachineState *pcms) x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); for (i = 0; i < nb_option_roms; i++) { - assert(!strcmp(option_rom[i].name, "linuxboot.bin") || - !strcmp(option_rom[i].name, "linuxboot_dma.bin") || + assert(!strcmp(option_rom[i].name, "linuxboot_dma.bin") || !strcmp(option_rom[i].name, "pvh.bin") || !strcmp(option_rom[i].name, "multiboot_dma.bin")); rom_add_option(option_rom[i].name, option_rom[i].bootindex); diff --git a/pc-bios/meson.build b/pc-bios/meson.build index efe45c16705d..2f470ed12942 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -63,7 +63,6 @@ blobs = [ 'efi-vmxnet3.rom', 'qemu-nsis.bmp', 'multiboot_dma.bin', - 'linuxboot.bin', 'linuxboot_dma.bin', 'kvmvapic.bin', 'pvh.bin', diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile index 1183ef889228..e694c7aac007 100644 --- a/pc-bios/optionrom/Makefile +++ b/pc-bios/optionrom/Makefile @@ -2,7 +2,7 @@ include config.mak SRC_DIR := $(TOPSRC_DIR)/pc-bios/optionrom VPATH = $(SRC_DIR) -all: multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin +all: multiboot_dma.bin linuxboot_dma.bin kvmvapic.bin pvh.bin # Dummy command so that make thinks it has done something @true diff --git a/pc-bios/optionrom/linuxboot.S b/pc-bios/optionrom/linuxboot.S deleted file mode 100644 index ba821ab922da..000000000000 --- a/pc-bios/optionrom/linuxboot.S +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Linux Boot Option ROM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Copyright Novell Inc, 2009 - * Authors: Alexander Graf <agraf@suse.de> - * - * Based on code in hw/pc.c. - */ - -#include "optionrom.h" - -#define BOOT_ROM_PRODUCT "Linux loader" - -BOOT_ROM_START - -run_linuxboot: - - cli - cld - - jmp copy_kernel -boot_kernel: - - read_fw FW_CFG_SETUP_ADDR - - mov %eax, %ebx - shr $4, %ebx - - /* All segments contain real_addr */ - mov %bx, %ds - mov %bx, %es - mov %bx, %fs - mov %bx, %gs - mov %bx, %ss - - /* CX = CS we want to jump to */ - add $0x20, %bx - mov %bx, %cx - - /* SP = cmdline_addr-real_addr-16 */ - read_fw FW_CFG_CMDLINE_ADDR - mov %eax, %ebx - read_fw FW_CFG_SETUP_ADDR - sub %eax, %ebx - sub $16, %ebx - mov %ebx, %esp - - /* Build indirect lret descriptor */ - pushw %cx /* CS */ - xor %ax, %ax - pushw %ax /* IP = 0 */ - - /* Clear registers */ - xor %eax, %eax - xor %ebx, %ebx - xor %ecx, %ecx - xor %edx, %edx - xor %edi, %edi - xor %ebp, %ebp - - /* Jump to Linux */ - lret - - -copy_kernel: - /* Read info block in low memory (0x10000 or 0x90000) */ - read_fw FW_CFG_SETUP_ADDR - shr $4, %eax - mov %eax, %es - xor %edi, %edi - read_fw_blob_addr32_edi(FW_CFG_SETUP) - - cmpw $0x203, %es:0x206 // if protocol >= 0x203 - jae 1f // have initrd_max - movl $0x37ffffff, %es:0x22c // else assume 0x37ffffff -1: - - /* Check if using kernel-specified initrd address */ - read_fw FW_CFG_INITRD_ADDR - mov %eax, %edi // (load_kernel wants it in %edi) - read_fw FW_CFG_INITRD_SIZE // find end of initrd - add %edi, %eax - xor %es:0x22c, %eax // if it matches es:0x22c - and $-4096, %eax // (apart from padding for page) - jz load_kernel // then initrd is not at top - // of memory - - /* pc.c placed the initrd at end of memory. Compute a better - * initrd address based on e801 data. - */ - mov $0xe801, %ax - xor %cx, %cx - xor %dx, %dx - int $0x15 - - /* Output could be in AX/BX or CX/DX */ - or %cx, %cx - jnz 1f - or %dx, %dx - jnz 1f - mov %ax, %cx - mov %bx, %dx -1: - - or %dx, %dx - jnz 2f - addw $1024, %cx /* add 1 MB */ - movzwl %cx, %edi - shll $10, %edi /* convert to bytes */ - jmp 3f - -2: - addw $16777216 >> 16, %dx /* add 16 MB */ - movzwl %dx, %edi - shll $16, %edi /* convert to bytes */ - -3: - read_fw FW_CFG_INITRD_SIZE - subl %eax, %edi - andl $-4096, %edi /* EDI = start of initrd */ - movl %edi, %es:0x218 /* put it in the header */ - -load_kernel: - /* We need to load the kernel into memory we can't access in 16 bit - mode, so let's get into 32 bit mode, write the kernel and jump - back again. */ - - /* Reserve space on the stack for our GDT descriptor. */ - mov %esp, %ebp - sub $16, %esp - - /* Now create the GDT descriptor */ - movw $((3 * 8) - 1), -16(%bp) - mov %cs, %eax - movzwl %ax, %eax - shl $4, %eax - addl $gdt, %eax - movl %eax, -14(%bp) - - /* And load the GDT */ - data32 lgdt -16(%bp) - mov %ebp, %esp - - /* Get us to protected mode now */ - mov $1, %eax - mov %eax, %cr0 - - /* So we can set ES to a 32-bit segment */ - mov $0x10, %eax - mov %eax, %es - - /* We're now running in 16-bit CS, but 32-bit ES! */ - - /* Load kernel and initrd */ - read_fw_blob_addr32_edi(FW_CFG_INITRD) - read_fw_blob_addr32(FW_CFG_KERNEL) - read_fw_blob_addr32(FW_CFG_CMDLINE) - - /* And now jump into Linux! */ - mov $0, %eax - mov %eax, %cr0 - - /* ES = CS */ - mov %cs, %ax - mov %ax, %es - - jmp boot_kernel - -/* Variables */ - -.align 4, 0 -gdt: - /* 0x00 */ -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - - /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 - - /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 - -BOOT_ROM_END -- 2.34.1
On Wed, 3 Dec 2025 00:28:23 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
All machines now use the linuxboot_dma.bin binary, so it's safe to remove the non-DMA version (linuxboot.bin).
after applying this patch: git grep linuxboot.bin option_rom[nb_option_roms].bootindex = 0; option_rom[nb_option_roms].name = "linuxboot.bin"; if (fw_cfg_dma_enabled(fw_cfg)) { option_rom[nb_option_roms].name = "linuxboot_dma.bin"; } perhaps it should be fixed in previous patch
Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Changes since v4: * Update commit message: not only pc, but also microvm enables DMA for FwCfgState (in microvm_memory_init). --- hw/i386/pc.c | 3 +- pc-bios/meson.build | 1 - pc-bios/optionrom/Makefile | 2 +- pc-bios/optionrom/linuxboot.S | 195 ---------------------------------- 4 files changed, 2 insertions(+), 199 deletions(-) delete mode 100644 pc-bios/optionrom/linuxboot.S
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9d88d4a5207a..2e315414aeaf 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -666,8 +666,7 @@ void xen_load_linux(PCMachineState *pcms)
x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); for (i = 0; i < nb_option_roms; i++) { - assert(!strcmp(option_rom[i].name, "linuxboot.bin") || - !strcmp(option_rom[i].name, "linuxboot_dma.bin") || + assert(!strcmp(option_rom[i].name, "linuxboot_dma.bin") || !strcmp(option_rom[i].name, "pvh.bin") || !strcmp(option_rom[i].name, "multiboot_dma.bin")); rom_add_option(option_rom[i].name, option_rom[i].bootindex); diff --git a/pc-bios/meson.build b/pc-bios/meson.build index efe45c16705d..2f470ed12942 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -63,7 +63,6 @@ blobs = [ 'efi-vmxnet3.rom', 'qemu-nsis.bmp', 'multiboot_dma.bin', - 'linuxboot.bin', 'linuxboot_dma.bin', 'kvmvapic.bin', 'pvh.bin', diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile index 1183ef889228..e694c7aac007 100644 --- a/pc-bios/optionrom/Makefile +++ b/pc-bios/optionrom/Makefile @@ -2,7 +2,7 @@ include config.mak SRC_DIR := $(TOPSRC_DIR)/pc-bios/optionrom VPATH = $(SRC_DIR)
-all: multiboot_dma.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin +all: multiboot_dma.bin linuxboot_dma.bin kvmvapic.bin pvh.bin # Dummy command so that make thinks it has done something @true
diff --git a/pc-bios/optionrom/linuxboot.S b/pc-bios/optionrom/linuxboot.S deleted file mode 100644 index ba821ab922da..000000000000 --- a/pc-bios/optionrom/linuxboot.S +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Linux Boot Option ROM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Copyright Novell Inc, 2009 - * Authors: Alexander Graf <agraf@suse.de> - * - * Based on code in hw/pc.c. - */ - -#include "optionrom.h" - -#define BOOT_ROM_PRODUCT "Linux loader" - -BOOT_ROM_START - -run_linuxboot: - - cli - cld - - jmp copy_kernel -boot_kernel: - - read_fw FW_CFG_SETUP_ADDR - - mov %eax, %ebx - shr $4, %ebx - - /* All segments contain real_addr */ - mov %bx, %ds - mov %bx, %es - mov %bx, %fs - mov %bx, %gs - mov %bx, %ss - - /* CX = CS we want to jump to */ - add $0x20, %bx - mov %bx, %cx - - /* SP = cmdline_addr-real_addr-16 */ - read_fw FW_CFG_CMDLINE_ADDR - mov %eax, %ebx - read_fw FW_CFG_SETUP_ADDR - sub %eax, %ebx - sub $16, %ebx - mov %ebx, %esp - - /* Build indirect lret descriptor */ - pushw %cx /* CS */ - xor %ax, %ax - pushw %ax /* IP = 0 */ - - /* Clear registers */ - xor %eax, %eax - xor %ebx, %ebx - xor %ecx, %ecx - xor %edx, %edx - xor %edi, %edi - xor %ebp, %ebp - - /* Jump to Linux */ - lret - - -copy_kernel: - /* Read info block in low memory (0x10000 or 0x90000) */ - read_fw FW_CFG_SETUP_ADDR - shr $4, %eax - mov %eax, %es - xor %edi, %edi - read_fw_blob_addr32_edi(FW_CFG_SETUP) - - cmpw $0x203, %es:0x206 // if protocol >= 0x203 - jae 1f // have initrd_max - movl $0x37ffffff, %es:0x22c // else assume 0x37ffffff -1: - - /* Check if using kernel-specified initrd address */ - read_fw FW_CFG_INITRD_ADDR - mov %eax, %edi // (load_kernel wants it in %edi) - read_fw FW_CFG_INITRD_SIZE // find end of initrd - add %edi, %eax - xor %es:0x22c, %eax // if it matches es:0x22c - and $-4096, %eax // (apart from padding for page) - jz load_kernel // then initrd is not at top - // of memory - - /* pc.c placed the initrd at end of memory. Compute a better - * initrd address based on e801 data. - */ - mov $0xe801, %ax - xor %cx, %cx - xor %dx, %dx - int $0x15 - - /* Output could be in AX/BX or CX/DX */ - or %cx, %cx - jnz 1f - or %dx, %dx - jnz 1f - mov %ax, %cx - mov %bx, %dx -1: - - or %dx, %dx - jnz 2f - addw $1024, %cx /* add 1 MB */ - movzwl %cx, %edi - shll $10, %edi /* convert to bytes */ - jmp 3f - -2: - addw $16777216 >> 16, %dx /* add 16 MB */ - movzwl %dx, %edi - shll $16, %edi /* convert to bytes */ - -3: - read_fw FW_CFG_INITRD_SIZE - subl %eax, %edi - andl $-4096, %edi /* EDI = start of initrd */ - movl %edi, %es:0x218 /* put it in the header */ - -load_kernel: - /* We need to load the kernel into memory we can't access in 16 bit - mode, so let's get into 32 bit mode, write the kernel and jump - back again. */ - - /* Reserve space on the stack for our GDT descriptor. */ - mov %esp, %ebp - sub $16, %esp - - /* Now create the GDT descriptor */ - movw $((3 * 8) - 1), -16(%bp) - mov %cs, %eax - movzwl %ax, %eax - shl $4, %eax - addl $gdt, %eax - movl %eax, -14(%bp) - - /* And load the GDT */ - data32 lgdt -16(%bp) - mov %ebp, %esp - - /* Get us to protected mode now */ - mov $1, %eax - mov %eax, %cr0 - - /* So we can set ES to a 32-bit segment */ - mov $0x10, %eax - mov %eax, %es - - /* We're now running in 16-bit CS, but 32-bit ES! */ - - /* Load kernel and initrd */ - read_fw_blob_addr32_edi(FW_CFG_INITRD) - read_fw_blob_addr32(FW_CFG_KERNEL) - read_fw_blob_addr32(FW_CFG_CMDLINE) - - /* And now jump into Linux! */ - mov $0, %eax - mov %eax, %cr0 - - /* ES = CS */ - mov %cs, %ax - mov %ax, %es - - jmp boot_kernel - -/* Variables */ - -.align 4, 0 -gdt: - /* 0x00 */ -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - - /* 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9a, 0xcf, 0x00 - - /* 0x10: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k) */ -.byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x92, 0xcf, 0x00 - -BOOT_ROM_END
On Wed, Dec 17, 2025 at 03:55:30PM +0100, Igor Mammedov wrote:
Date: Wed, 17 Dec 2025 15:55:30 +0100 From: Igor Mammedov <imammedo@redhat.com> Subject: Re: [PATCH v5 16/28] hw/i386: Remove linuxboot.bin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu)
On Wed, 3 Dec 2025 00:28:23 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
All machines now use the linuxboot_dma.bin binary, so it's safe to remove the non-DMA version (linuxboot.bin).
after applying this patch:
git grep linuxboot.bin
option_rom[nb_option_roms].bootindex = 0; option_rom[nb_option_roms].name = "linuxboot.bin"; if (fw_cfg_dma_enabled(fw_cfg)) { option_rom[nb_option_roms].name = "linuxboot_dma.bin"; }
perhaps it should be fixed in previous patch
Thanks, I find this change was included in the previous patch (patch 15). And I have a GitLab branch and hopefully it could help apply and review: https://gitlab.com/zhao.liu/qemu/-/commits/remove-2.6-and-2.7-pc-v5-11-26-20... Regards, Zhao
On Thu, 18 Dec 2025 15:45:10 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
On Wed, Dec 17, 2025 at 03:55:30PM +0100, Igor Mammedov wrote:
Date: Wed, 17 Dec 2025 15:55:30 +0100 From: Igor Mammedov <imammedo@redhat.com> Subject: Re: [PATCH v5 16/28] hw/i386: Remove linuxboot.bin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu)
On Wed, 3 Dec 2025 00:28:23 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
All machines now use the linuxboot_dma.bin binary, so it's safe to remove the non-DMA version (linuxboot.bin).
after applying this patch:
git grep linuxboot.bin
option_rom[nb_option_roms].bootindex = 0; option_rom[nb_option_roms].name = "linuxboot.bin"; if (fw_cfg_dma_enabled(fw_cfg)) { option_rom[nb_option_roms].name = "linuxboot_dma.bin"; }
perhaps it should be fixed in previous patch
Thanks, I find this change was included in the previous patch (patch 15).
Yep, sorry for confusion. /I forgot to apply #15, hence it led to a stray linuxboot.bin/
And I have a GitLab branch and hopefully it could help apply and review:
https://gitlab.com/zhao.liu/qemu/-/commits/remove-2.6-and-2.7-pc-v5-11-26-20...
Regards, Zhao
On Wed, Dec 17, 2025 at 03:55:30PM +0100, Igor Mammedov wrote:
Date: Wed, 17 Dec 2025 15:55:30 +0100 From: Igor Mammedov <imammedo@redhat.com> Subject: Re: [PATCH v5 16/28] hw/i386: Remove linuxboot.bin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu)
On Wed, 3 Dec 2025 00:28:23 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
All machines now use the linuxboot_dma.bin binary, so it's safe to remove the non-DMA version (linuxboot.bin).
after applying this patch:
git grep linuxboot.bin
option_rom[nb_option_roms].bootindex = 0; option_rom[nb_option_roms].name = "linuxboot.bin"; if (fw_cfg_dma_enabled(fw_cfg)) { option_rom[nb_option_roms].name = "linuxboot_dma.bin"; }
perhaps it should be fixed in previous patch
Thanks, I find this change was included in the previous patch (patch 15).
Yep, sorry for confusion. /I forgot to apply #15, hence it led to a stray linuxboot.bin/
You're welcome and thanks for your review! Regards, Zhao
From: Philippe Mathieu-Daudé <philmd@linaro.org> The pc_compat_2_6[] array was only used by the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/pc.c | 8 -------- include/hw/i386/pc.h | 3 --- 2 files changed, 11 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2e315414aeaf..85d12f8d0389 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -263,14 +263,6 @@ GlobalProperty pc_compat_2_7[] = { }; const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); -GlobalProperty pc_compat_2_6[] = { - { TYPE_X86_CPU, "cpuid-0xb", "off" }, - { "vmxnet3", "romfile", "" }, - { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, - { "apic-common", "legacy-instance-id", "on", } -}; -const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); - /* * @PC_FW_DATA: * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 698e3fb84af0..f8f317aee197 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -295,9 +295,6 @@ extern const size_t pc_compat_2_8_len; extern GlobalProperty pc_compat_2_7[]; extern const size_t pc_compat_2_7_len; -extern GlobalProperty pc_compat_2_6[]; -extern const size_t pc_compat_2_6_len; - #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, \ const void *data) \ -- 2.34.1
On Wed, 3 Dec 2025 00:28:24 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The pc_compat_2_6[] array was only used by the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/i386/pc.c | 8 -------- include/hw/i386/pc.h | 3 --- 2 files changed, 11 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2e315414aeaf..85d12f8d0389 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -263,14 +263,6 @@ GlobalProperty pc_compat_2_7[] = { }; const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
-GlobalProperty pc_compat_2_6[] = { - { TYPE_X86_CPU, "cpuid-0xb", "off" }, - { "vmxnet3", "romfile", "" }, - { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, - { "apic-common", "legacy-instance-id", "on", } -}; -const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); - /* * @PC_FW_DATA: * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 698e3fb84af0..f8f317aee197 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -295,9 +295,6 @@ extern const size_t pc_compat_2_8_len; extern GlobalProperty pc_compat_2_7[]; extern const size_t pc_compat_2_7_len;
-extern GlobalProperty pc_compat_2_6[]; -extern const size_t pc_compat_2_6_len; - #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, \ const void *data) \
From: Philippe Mathieu-Daudé <philmd@linaro.org> The APICCommonState::legacy_instance_id boolean was only set in the pc_compat_2_6[] array, via the 'legacy-instance-id=on' property. We removed all machines using that array, lets remove that property, simplifying apic_common_realize(). Because instance_id is initialized as initial_apic_id, we can not register vmstate_apic_common directly via dc->vmsd. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/intc/apic_common.c | 5 ----- include/hw/i386/apic_internal.h | 1 - 2 files changed, 6 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index ec9e978b0b40..69a7b1bd5d3e 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -276,9 +276,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp) info->enable_tpr_reporting(s, true); } - if (s->legacy_instance_id) { - instance_id = VMSTATE_INSTANCE_ID_ANY; - } vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, s, -1, 0, NULL); @@ -395,8 +392,6 @@ static const Property apic_properties_common[] = { DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, true), - DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, - false), }; static void apic_common_get_id(Object *obj, Visitor *v, const char *name, diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index 4a62fdceb4ea..0cb06bbc76c9 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -187,7 +187,6 @@ struct APICCommonState { uint32_t vapic_control; DeviceState *vapic; hwaddr vapic_paddr; /* note: persistence via kvmvapic */ - bool legacy_instance_id; uint32_t extended_log_dest; }; -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The hw_compat_2_6[] array was only used by the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/core/machine.c | 8 -------- include/hw/boards.h | 3 --- 2 files changed, 11 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 27372bb01ef4..0b10adb5d538 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -290,14 +290,6 @@ GlobalProperty hw_compat_2_7[] = { }; const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); -GlobalProperty hw_compat_2_6[] = { - { "virtio-mmio", "format_transport_address", "off" }, - /* Optional because not all virtio-pci devices support legacy mode */ - { "virtio-pci", "disable-modern", "on", .optional = true }, - { "virtio-pci", "disable-legacy", "off", .optional = true }, -}; -const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); - MachineState *current_machine; static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/include/hw/boards.h b/include/hw/boards.h index a48ed4f86a35..5ddadbfd8a83 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -882,7 +882,4 @@ extern const size_t hw_compat_2_8_len; extern GlobalProperty hw_compat_2_7[]; extern const size_t hw_compat_2_7_len; -extern GlobalProperty hw_compat_2_6[]; -extern const size_t hw_compat_2_6_len; - #endif -- 2.34.1
On Wed, 3 Dec 2025 00:28:26 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The hw_compat_2_6[] array was only used by the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/core/machine.c | 8 -------- include/hw/boards.h | 3 --- 2 files changed, 11 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c index 27372bb01ef4..0b10adb5d538 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -290,14 +290,6 @@ GlobalProperty hw_compat_2_7[] = { }; const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
-GlobalProperty hw_compat_2_6[] = { - { "virtio-mmio", "format_transport_address", "off" }, - /* Optional because not all virtio-pci devices support legacy mode */ - { "virtio-pci", "disable-modern", "on", .optional = true }, - { "virtio-pci", "disable-legacy", "off", .optional = true }, -}; -const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); - MachineState *current_machine;
static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/include/hw/boards.h b/include/hw/boards.h index a48ed4f86a35..5ddadbfd8a83 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -882,7 +882,4 @@ extern const size_t hw_compat_2_8_len; extern GlobalProperty hw_compat_2_7[]; extern const size_t hw_compat_2_7_len;
-extern GlobalProperty hw_compat_2_6[]; -extern const size_t hw_compat_2_6_len; - #endif
From: Philippe Mathieu-Daudé <philmd@linaro.org> The VirtIOMMIOProxy::format_transport_address boolean was only set in the hw_compat_2_6[] array, via the 'format_transport_address=off' property. We removed all machines using that array, lets remove that property, simplifying virtio_mmio_bus_get_dev_path(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/virtio/virtio-mmio.c | 15 --------------- include/hw/virtio/virtio-mmio.h | 1 - 2 files changed, 16 deletions(-) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index c05c00bcd4a7..c779836201d5 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -764,8 +764,6 @@ static void virtio_mmio_pre_plugged(DeviceState *d, Error **errp) /* virtio-mmio device */ static const Property virtio_mmio_properties[] = { - DEFINE_PROP_BOOL("format_transport_address", VirtIOMMIOProxy, - format_transport_address, true), DEFINE_PROP_BOOL("force-legacy", VirtIOMMIOProxy, legacy, true), DEFINE_PROP_BIT("ioeventfd", VirtIOMMIOProxy, flags, VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD_BIT, true), @@ -827,19 +825,6 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) virtio_mmio_proxy = VIRTIO_MMIO(virtio_mmio_bus->parent); proxy_path = qdev_get_dev_path(DEVICE(virtio_mmio_proxy)); - /* - * If @format_transport_address is false, then we just perform the same as - * virtio_bus_get_dev_path(): we delegate the address formatting for the - * device on the virtio-mmio bus to the bus that the virtio-mmio proxy - * (i.e., the device that implements the virtio-mmio bus) resides on. In - * this case the base address of the virtio-mmio transport will be - * invisible. - */ - if (!virtio_mmio_proxy->format_transport_address) { - return proxy_path; - } - - /* Otherwise, we append the base address of the transport. */ section = memory_region_find(&virtio_mmio_proxy->iomem, 0, 0x200); assert(section.mr); diff --git a/include/hw/virtio/virtio-mmio.h b/include/hw/virtio/virtio-mmio.h index aa492620228d..8b19ec2291ac 100644 --- a/include/hw/virtio/virtio-mmio.h +++ b/include/hw/virtio/virtio-mmio.h @@ -66,7 +66,6 @@ struct VirtIOMMIOProxy { uint32_t guest_page_shift; /* virtio-bus */ VirtioBusState bus; - bool format_transport_address; /* Fields only used for non-legacy (v2) devices */ uint32_t guest_features[2]; VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX]; -- 2.34.1
On Wed, 3 Dec 2025 00:28:27 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The VirtIOMMIOProxy::format_transport_address boolean was only set in the hw_compat_2_6[] array, via the 'format_transport_address=off' property. We removed all machines using that array, lets remove that property, simplifying virtio_mmio_bus_get_dev_path().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/virtio/virtio-mmio.c | 15 --------------- include/hw/virtio/virtio-mmio.h | 1 - 2 files changed, 16 deletions(-)
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index c05c00bcd4a7..c779836201d5 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -764,8 +764,6 @@ static void virtio_mmio_pre_plugged(DeviceState *d, Error **errp) /* virtio-mmio device */
static const Property virtio_mmio_properties[] = { - DEFINE_PROP_BOOL("format_transport_address", VirtIOMMIOProxy, - format_transport_address, true), DEFINE_PROP_BOOL("force-legacy", VirtIOMMIOProxy, legacy, true), DEFINE_PROP_BIT("ioeventfd", VirtIOMMIOProxy, flags, VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD_BIT, true), @@ -827,19 +825,6 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) virtio_mmio_proxy = VIRTIO_MMIO(virtio_mmio_bus->parent); proxy_path = qdev_get_dev_path(DEVICE(virtio_mmio_proxy));
- /* - * If @format_transport_address is false, then we just perform the same as - * virtio_bus_get_dev_path(): we delegate the address formatting for the - * device on the virtio-mmio bus to the bus that the virtio-mmio proxy - * (i.e., the device that implements the virtio-mmio bus) resides on. In - * this case the base address of the virtio-mmio transport will be - * invisible. - */ - if (!virtio_mmio_proxy->format_transport_address) { - return proxy_path; - } - - /* Otherwise, we append the base address of the transport. */ section = memory_region_find(&virtio_mmio_proxy->iomem, 0, 0x200); assert(section.mr);
diff --git a/include/hw/virtio/virtio-mmio.h b/include/hw/virtio/virtio-mmio.h index aa492620228d..8b19ec2291ac 100644 --- a/include/hw/virtio/virtio-mmio.h +++ b/include/hw/virtio/virtio-mmio.h @@ -66,7 +66,6 @@ struct VirtIOMMIOProxy { uint32_t guest_page_shift; /* virtio-bus */ VirtioBusState bus; - bool format_transport_address; /* Fields only used for non-legacy (v2) devices */ uint32_t guest_features[2]; VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX];
From: Philippe Mathieu-Daudé <philmd@linaro.org> These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed. Remove the qtest in test-x86-cpuid-compat.c file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/pc_piix.c | 9 --------- hw/i386/pc_q35.c | 10 ---------- tests/qtest/test-x86-cpuid-compat.c | 11 ----------- 3 files changed, 30 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4628d491d5b5..6b3bfb679a38 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -724,15 +724,6 @@ static void pc_i440fx_machine_2_8_options(MachineClass *m) DEFINE_I440FX_MACHINE(2, 8); -static void pc_i440fx_machine_2_7_options(MachineClass *m) -{ - pc_i440fx_machine_2_8_options(m); - compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); - compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); -} - -DEFINE_I440FX_MACHINE(2, 7); - #ifdef CONFIG_XEN static void xenfv_machine_4_2_options(MachineClass *m) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 0ae19eb9f1e4..0de8305308a1 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -671,13 +671,3 @@ static void pc_q35_machine_2_8_options(MachineClass *m) } DEFINE_Q35_MACHINE(2, 8); - -static void pc_q35_machine_2_7_options(MachineClass *m) -{ - pc_q35_machine_2_8_options(m); - m->max_cpus = 255; - compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); - compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); -} - -DEFINE_Q35_MACHINE(2, 7); diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c index 456e2af66572..5e0547e81b7b 100644 --- a/tests/qtest/test-x86-cpuid-compat.c +++ b/tests/qtest/test-x86-cpuid-compat.c @@ -345,17 +345,6 @@ int main(int argc, char **argv) /* Check compatibility of old machine-types that didn't * auto-increase level/xlevel/xlevel2: */ - if (qtest_has_machine("pc-i440fx-2.7")) { - add_cpuid_test("x86/cpuid/auto-level/pc-2.7", - "486", "arat=on,avx512vbmi=on,xsaveopt=on", - "pc-i440fx-2.7", "level", 1); - add_cpuid_test("x86/cpuid/auto-xlevel/pc-2.7", - "486", "3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on", - "pc-i440fx-2.7", "xlevel", 0); - add_cpuid_test("x86/cpuid/auto-xlevel2/pc-2.7", - "486", "xstore=on", "pc-i440fx-2.7", - "xlevel2", 0); - } if (qtest_has_machine("pc-i440fx-2.9")) { add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.9/off", "Conroe", NULL, "pc-i440fx-2.9", -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The pc_compat_2_7[] array was only used by the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/pc.c | 10 ---------- include/hw/i386/pc.h | 3 --- 2 files changed, 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 85d12f8d0389..b88030bf50d0 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -253,16 +253,6 @@ GlobalProperty pc_compat_2_8[] = { }; const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); -GlobalProperty pc_compat_2_7[] = { - { TYPE_X86_CPU, "l3-cache", "off" }, - { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, - { "isa-pcspk", "migrate", "off" }, -}; -const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); - /* * @PC_FW_DATA: * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f8f317aee197..accd08cb666b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -292,9 +292,6 @@ extern const size_t pc_compat_2_9_len; extern GlobalProperty pc_compat_2_8[]; extern const size_t pc_compat_2_8_len; -extern GlobalProperty pc_compat_2_7[]; -extern const size_t pc_compat_2_7_len; - #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, \ const void *data) \ -- 2.34.1
On Wed, 3 Dec 2025 00:28:29 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The pc_compat_2_7[] array was only used by the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/pc.c | 10 ---------- include/hw/i386/pc.h | 3 --- 2 files changed, 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 85d12f8d0389..b88030bf50d0 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -253,16 +253,6 @@ GlobalProperty pc_compat_2_8[] = { }; const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
-GlobalProperty pc_compat_2_7[] = { - { TYPE_X86_CPU, "l3-cache", "off" }, - { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, - { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, - { "isa-pcspk", "migrate", "off" }, -}; -const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); - /* * @PC_FW_DATA: * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f8f317aee197..accd08cb666b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -292,9 +292,6 @@ extern const size_t pc_compat_2_9_len; extern GlobalProperty pc_compat_2_8[]; extern const size_t pc_compat_2_8_len;
-extern GlobalProperty pc_compat_2_7[]; -extern const size_t pc_compat_2_7_len; - #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, \ const void *data) \
From: Philippe Mathieu-Daudé <philmd@linaro.org> The CPUX86State::full_cpuid_auto_level boolean was only disabled for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Being now always %true, we can remove it and simplify x86_cpu_expand_features(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- Note, although libvirt still uses this property in its test cases, it was confirmed this property is not exposed to user directly [*]. [*]: https://lore.kernel.org/qemu-devel/aDmphSY1MSxu7L9R@orkuz.int.mamuti.net/ --- target/i386/cpu.c | 111 ++++++++++++++++++++++------------------------ target/i386/cpu.h | 3 -- 2 files changed, 54 insertions(+), 60 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 641777578637..72c69ba81c1b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9019,69 +9019,67 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); - if (cpu->full_cpuid_auto_level) { - x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); - x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_SVM); - x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); - - /* Intel Processor Trace requires CPUID[0x14] */ - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { - if (cpu->intel_pt_auto_level) { - x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); - } else if (cpu->env.cpuid_min_level < 0x14) { - mark_unavailable_features(cpu, FEAT_7_0_EBX, - CPUID_7_0_EBX_INTEL_PT, - "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); - } + x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); + x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_SVM); + x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + + /* Intel Processor Trace requires CPUID[0x14] */ + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { + if (cpu->intel_pt_auto_level) { + x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); + } else if (cpu->env.cpuid_min_level < 0x14) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, + CPUID_7_0_EBX_INTEL_PT, + "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); } + } - /* - * Intel CPU topology with multi-dies support requires CPUID[0x1F]. - * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect - * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless - * cpu->vendor_cpuid_only has been unset for compatibility with older - * machine types. - */ - if (x86_has_cpuid_0x1f(cpu) && - (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); - } + /* + * Intel CPU topology with multi-dies support requires CPUID[0x1F]. + * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect + * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless + * cpu->vendor_cpuid_only has been unset for compatibility with older + * machine types. + */ + if (x86_has_cpuid_0x1f(cpu) && + (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); + } - /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ - if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); - } + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); + } - /* SVM requires CPUID[0x8000000A] */ - if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); - } + /* SVM requires CPUID[0x8000000A] */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); + } - /* SEV requires CPUID[0x8000001F] */ - if (sev_enabled()) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); - } + /* SEV requires CPUID[0x8000001F] */ + if (sev_enabled()) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); + } - if (env->features[FEAT_8000_0021_EAX]) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); - } + if (env->features[FEAT_8000_0021_EAX]) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); + } - /* SGX requires CPUID[0x12] for EPC enumeration */ - if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); - } + /* SGX requires CPUID[0x12] for EPC enumeration */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ @@ -10010,7 +10008,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), - DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cee1f692a1c3..8c3eb86fa0c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2292,9 +2292,6 @@ struct ArchCPU { /* Force to enable cpuid 0x1f */ bool force_cpuid_0x1f; - /* Enable auto level-increase for all CPUID leaves */ - bool full_cpuid_auto_level; - /* * Compatibility bits for old machine types (PC machine v6.0 and older). * Only advertise CPUID leaves defined by the vendor. -- 2.34.1
On Wed, 3 Dec 2025 00:28:30 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The CPUX86State::full_cpuid_auto_level boolean was only disabled for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Being now always %true, we can remove it and simplify x86_cpu_expand_features().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- Note, although libvirt still uses this property in its test cases, it was confirmed this property is not exposed to user directly [*].
[*]: https://lore.kernel.org/qemu-devel/aDmphSY1MSxu7L9R@orkuz.int.mamuti.net/ --- target/i386/cpu.c | 111 ++++++++++++++++++++++------------------------ target/i386/cpu.h | 3 -- 2 files changed, 54 insertions(+), 60 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 641777578637..72c69ba81c1b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9019,69 +9019,67 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
/* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); - if (cpu->full_cpuid_auto_level) { - x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); - x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_SVM); - x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); - - /* Intel Processor Trace requires CPUID[0x14] */ - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { - if (cpu->intel_pt_auto_level) { - x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); - } else if (cpu->env.cpuid_min_level < 0x14) { - mark_unavailable_features(cpu, FEAT_7_0_EBX, - CPUID_7_0_EBX_INTEL_PT, - "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); - } + x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); + x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_SVM); + x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + + /* Intel Processor Trace requires CPUID[0x14] */ + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { + if (cpu->intel_pt_auto_level) { + x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); + } else if (cpu->env.cpuid_min_level < 0x14) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, + CPUID_7_0_EBX_INTEL_PT, + "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); } + }
- /* - * Intel CPU topology with multi-dies support requires CPUID[0x1F]. - * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect - * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless - * cpu->vendor_cpuid_only has been unset for compatibility with older - * machine types. - */ - if (x86_has_cpuid_0x1f(cpu) && - (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); - } + /* + * Intel CPU topology with multi-dies support requires CPUID[0x1F]. + * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect + * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless + * cpu->vendor_cpuid_only has been unset for compatibility with older + * machine types. + */ + if (x86_has_cpuid_0x1f(cpu) && + (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); + }
- /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ - if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); - } + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); + }
- /* SVM requires CPUID[0x8000000A] */ - if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); - } + /* SVM requires CPUID[0x8000000A] */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); + }
- /* SEV requires CPUID[0x8000001F] */ - if (sev_enabled()) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); - } + /* SEV requires CPUID[0x8000001F] */ + if (sev_enabled()) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); + }
- if (env->features[FEAT_8000_0021_EAX]) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); - } + if (env->features[FEAT_8000_0021_EAX]) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); + }
- /* SGX requires CPUID[0x12] for EPC enumeration */ - if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); - } + /* SGX requires CPUID[0x12] for EPC enumeration */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); }
/* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ @@ -10010,7 +10008,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), - DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cee1f692a1c3..8c3eb86fa0c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2292,9 +2292,6 @@ struct ArchCPU { /* Force to enable cpuid 0x1f */ bool force_cpuid_0x1f;
- /* Enable auto level-increase for all CPUID leaves */ - bool full_cpuid_auto_level; - /* * Compatibility bits for old machine types (PC machine v6.0 and older). * Only advertise CPUID leaves defined by the vendor.
From: Philippe Mathieu-Daudé <philmd@linaro.org> The PCSpkState::migrate boolean was only set in the pc_compat_2_7[] array, via the 'migrate=off' property. We removed all machines using that array, lets remove that property, simplifying vmstate_spk[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/audio/pcspk.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/audio/pcspk.c b/hw/audio/pcspk.c index 916c56fa4c0a..0b01544941cb 100644 --- a/hw/audio/pcspk.c +++ b/hw/audio/pcspk.c @@ -57,7 +57,6 @@ struct PCSpkState { unsigned int play_pos; uint8_t data_on; uint8_t dummy_refresh_clock; - bool migrate; }; static const char *s_spk = "pcspk"; @@ -202,18 +201,10 @@ static void pcspk_realizefn(DeviceState *dev, Error **errp) } } -static bool migrate_needed(void *opaque) -{ - PCSpkState *s = opaque; - - return s->migrate; -} - static const VMStateDescription vmstate_spk = { .name = "pcspk", .version_id = 1, .minimum_version_id = 1, - .needed = migrate_needed, .fields = (const VMStateField[]) { VMSTATE_UINT8(data_on, PCSpkState), VMSTATE_UINT8(dummy_refresh_clock, PCSpkState), @@ -224,7 +215,6 @@ static const VMStateDescription vmstate_spk = { static const Property pcspk_properties[] = { DEFINE_AUDIO_PROPERTIES(PCSpkState, audio_be), DEFINE_PROP_UINT32("iobase", PCSpkState, iobase, 0x61), - DEFINE_PROP_BOOL("migrate", PCSpkState, migrate, true), DEFINE_PROP_LINK("pit", PCSpkState, pit, TYPE_PIT_COMMON, PITCommonState *), }; -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The hw_compat_2_7[] array was only used by the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/core/machine.c | 9 --------- include/hw/boards.h | 3 --- 2 files changed, 12 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 0b10adb5d538..f3e9346965c3 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -281,15 +281,6 @@ GlobalProperty hw_compat_2_8[] = { }; const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); -GlobalProperty hw_compat_2_7[] = { - { "virtio-pci", "page-per-vq", "on" }, - { "virtio-serial-device", "emergency-write", "off" }, - { "ioapic", "version", "0x11" }, - { "intel-iommu", "x-buggy-eim", "true" }, - { "virtio-pci", "x-ignore-backend-features", "on" }, -}; -const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); - MachineState *current_machine; static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/include/hw/boards.h b/include/hw/boards.h index 5ddadbfd8a83..83b78b35f2bf 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -879,7 +879,4 @@ extern const size_t hw_compat_2_9_len; extern GlobalProperty hw_compat_2_8[]; extern const size_t hw_compat_2_8_len; -extern GlobalProperty hw_compat_2_7[]; -extern const size_t hw_compat_2_7_len; - #endif -- 2.34.1
On Wed, 3 Dec 2025 00:28:32 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The hw_compat_2_7[] array was only used by the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/core/machine.c | 9 --------- include/hw/boards.h | 3 --- 2 files changed, 12 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c index 0b10adb5d538..f3e9346965c3 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -281,15 +281,6 @@ GlobalProperty hw_compat_2_8[] = { }; const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
-GlobalProperty hw_compat_2_7[] = { - { "virtio-pci", "page-per-vq", "on" }, - { "virtio-serial-device", "emergency-write", "off" }, - { "ioapic", "version", "0x11" }, - { "intel-iommu", "x-buggy-eim", "true" }, - { "virtio-pci", "x-ignore-backend-features", "on" }, -}; -const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); - MachineState *current_machine;
static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/include/hw/boards.h b/include/hw/boards.h index 5ddadbfd8a83..83b78b35f2bf 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -879,7 +879,4 @@ extern const size_t hw_compat_2_9_len; extern GlobalProperty hw_compat_2_8[]; extern const size_t hw_compat_2_8_len;
-extern GlobalProperty hw_compat_2_7[]; -extern const size_t hw_compat_2_7_len; - #endif
From: Philippe Mathieu-Daudé <philmd@linaro.org> The IntelIOMMUState::buggy_eim boolean was only set in the hw_compat_2_7[] array, via the 'x-buggy-eim=true' property. We removed all machines using that array, lets remove that property, simplifying vtd_decide_config(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/i386/intel_iommu.c | 5 ++--- include/hw/i386/intel_iommu.h | 1 - 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 78b142cceab3..0113cba32890 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4092,7 +4092,6 @@ static const Property vtd_properties[] = { DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, ON_OFF_AUTO_AUTO), - DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, VTD_HOST_ADDRESS_WIDTH), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), @@ -5359,11 +5358,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) } if (s->intr_eim == ON_OFF_AUTO_AUTO) { - s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim) + s->intr_eim = kvm_irqchip_in_kernel() && x86_iommu_ir_supported(x86_iommu) ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; } - if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) { + if (s->intr_eim == ON_OFF_AUTO_ON) { if (kvm_irqchip_is_split() && !kvm_enable_x2apic()) { error_setg(errp, "eim=on requires support on the KVM side" "(X2APIC_API, first shipped in v4.7)"); diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index ca7f7bb6618a..34ba13ffa8de 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -310,7 +310,6 @@ struct IntelIOMMUState { uint32_t intr_size; /* Number of IR table entries */ bool intr_eime; /* Extended interrupt mode enabled */ OnOffAuto intr_eim; /* Toggle for EIM cabability */ - bool buggy_eim; /* Force buggy EIM unless eim=off */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ bool dma_drain; /* Whether DMA r/w draining enabled */ bool pasid; /* Whether to support PASID */ -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The VirtIOPCIProxy::ignore_backend_features boolean was only set in the hw_compat_2_7[] array, via the 'x-ignore-backend-features=on' property. We removed all machines using that array, lets remove that property, simplify by only using the default version. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/virtio/virtio-pci.c | 5 +---- include/hw/virtio/virtio-pci.h | 1 - 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 99cb30fe595a..266e2b218aa7 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2040,8 +2040,7 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp) * Virtio capabilities present without * VIRTIO_F_VERSION_1 confuses guests */ - if (!proxy->ignore_backend_features && - !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) { + if (!virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) { virtio_pci_disable_modern(proxy); if (!legacy) { @@ -2441,8 +2440,6 @@ static const Property virtio_pci_properties[] = { VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false), DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false), - DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy, - ignore_backend_features, false), DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_ATS_BIT, false), DEFINE_PROP_BIT("x-ats-page-aligned", VirtIOPCIProxy, flags, diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 639752977ee8..581bb830b792 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -150,7 +150,6 @@ struct VirtIOPCIProxy { uint16_t last_pcie_cap_offset; uint32_t flags; bool disable_modern; - bool ignore_backend_features; OnOffAuto disable_legacy; /* Transitional device id */ uint16_t trans_devid; -- 2.34.1
From: Philippe Mathieu-Daudé <philmd@linaro.org> The VIRTIO_CONSOLE_F_EMERG_WRITE feature bit was only set in the hw_compat_2_7[] array, via the 'emergency-write=off' property. We removed all machines using that array, lets remove that property. All instances have this feature bit set and it can not be disabled. VirtIOSerial::host_features mask is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> --- hw/char/virtio-serial-bus.c | 9 +++------ include/hw/virtio/virtio-serial.h | 2 -- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index 673c50f0be08..7abb7b5e31bf 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -557,7 +557,7 @@ static uint64_t get_features(VirtIODevice *vdev, uint64_t features, vser = VIRTIO_SERIAL(vdev); - features |= vser->host_features; + features |= BIT_ULL(VIRTIO_CONSOLE_F_EMERG_WRITE); if (vser->bus.max_nr_ports > 1) { virtio_add_feature(&features, VIRTIO_CONSOLE_F_MULTIPORT); } @@ -587,8 +587,7 @@ static void set_config(VirtIODevice *vdev, const uint8_t *config_data) VirtIOSerialPortClass *vsc; uint8_t emerg_wr_lo; - if (!virtio_has_feature(vser->host_features, - VIRTIO_CONSOLE_F_EMERG_WRITE) || !config->emerg_wr) { + if (!config->emerg_wr) { return; } @@ -1040,7 +1039,7 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) return; } - if (!virtio_has_feature(vser->host_features, + if (!virtio_has_feature(vdev->host_features, VIRTIO_CONSOLE_F_EMERG_WRITE)) { config_size = offsetof(struct virtio_console_config, emerg_wr); } @@ -1156,8 +1155,6 @@ static const VMStateDescription vmstate_virtio_console = { static const Property virtio_serial_properties[] = { DEFINE_PROP_UINT32("max_ports", VirtIOSerial, serial.max_virtserial_ports, 31), - DEFINE_PROP_BIT64("emergency-write", VirtIOSerial, host_features, - VIRTIO_CONSOLE_F_EMERG_WRITE, true), }; static void virtio_serial_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/virtio/virtio-serial.h b/include/hw/virtio/virtio-serial.h index 60641860bf83..da0c91e1a403 100644 --- a/include/hw/virtio/virtio-serial.h +++ b/include/hw/virtio/virtio-serial.h @@ -186,8 +186,6 @@ struct VirtIOSerial { struct VirtIOSerialPostLoad *post_load; virtio_serial_conf serial; - - uint64_t host_features; }; /* Interface to the virtio-serial bus */ -- 2.34.1
On Wed, 3 Dec 2025 00:28:35 +0800 Zhao Liu <zhao1.liu@intel.com> wrote:
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The VIRTIO_CONSOLE_F_EMERG_WRITE feature bit was only set in the hw_compat_2_7[] array, via the 'emergency-write=off' property. We removed all machines using that array, lets remove that property. All instances have this feature bit set and it can not be disabled. VirtIOSerial::host_features mask is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
--- hw/char/virtio-serial-bus.c | 9 +++------ include/hw/virtio/virtio-serial.h | 2 -- 2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index 673c50f0be08..7abb7b5e31bf 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -557,7 +557,7 @@ static uint64_t get_features(VirtIODevice *vdev, uint64_t features,
vser = VIRTIO_SERIAL(vdev);
- features |= vser->host_features; + features |= BIT_ULL(VIRTIO_CONSOLE_F_EMERG_WRITE); if (vser->bus.max_nr_ports > 1) { virtio_add_feature(&features, VIRTIO_CONSOLE_F_MULTIPORT); } @@ -587,8 +587,7 @@ static void set_config(VirtIODevice *vdev, const uint8_t *config_data) VirtIOSerialPortClass *vsc; uint8_t emerg_wr_lo;
- if (!virtio_has_feature(vser->host_features, - VIRTIO_CONSOLE_F_EMERG_WRITE) || !config->emerg_wr) { + if (!config->emerg_wr) { return; }
@@ -1040,7 +1039,7 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) return; }
- if (!virtio_has_feature(vser->host_features, + if (!virtio_has_feature(vdev->host_features, VIRTIO_CONSOLE_F_EMERG_WRITE)) { config_size = offsetof(struct virtio_console_config, emerg_wr); } @@ -1156,8 +1155,6 @@ static const VMStateDescription vmstate_virtio_console = { static const Property virtio_serial_properties[] = { DEFINE_PROP_UINT32("max_ports", VirtIOSerial, serial.max_virtserial_ports, 31), - DEFINE_PROP_BIT64("emergency-write", VirtIOSerial, host_features, - VIRTIO_CONSOLE_F_EMERG_WRITE, true), };
static void virtio_serial_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/virtio/virtio-serial.h b/include/hw/virtio/virtio-serial.h index 60641860bf83..da0c91e1a403 100644 --- a/include/hw/virtio/virtio-serial.h +++ b/include/hw/virtio/virtio-serial.h @@ -186,8 +186,6 @@ struct VirtIOSerial { struct VirtIOSerialPostLoad *post_load;
virtio_serial_conf serial; - - uint64_t host_features; };
/* Interface to the virtio-serial bus */
participants (3)
-
Igor Mammedov -
Philippe Mathieu-Daudé -
Zhao Liu