[libvirt] [PATCHv10 0/2] Add Cascadelake-SP CPU model
Cascadelake-SP is looked as the second generation Intel XEON processor scalable family while Skylake-SP is the first generation. Both Skylake-SP and Cascadelake-SP has the same family (6h) and model (55h), but with difference stepping number. In the process of identifying candidate CPU, the stepping number is not irrelevant any more. The CPU refresh from Skylake-SP to Cascadelake-SP is this kind of example. These two patches firstly introduce the stepping number as another factor to identify future Intel CPU, then introduce the Cascadelake-SP cpu model. Wang Huaqiang (2): cpu: Add x86 stepping number as another factor to find candidate CPU cpu_map: Add Cascadelake Server CPU model src/cpu/cpu_x86.c | 60 +++++++++++++++++++----- src/cpu_map/Makefile.inc.am | 1 + src/cpu_map/index.xml | 1 + src/cpu_map/x86_Cascadelake-Server.xml | 83 ++++++++++++++++++++++++++++++++++ 4 files changed, 133 insertions(+), 12 deletions(-) create mode 100644 src/cpu_map/x86_Cascadelake-Server.xml -- 2.7.4
Cascadelake-SP is looked as the second generation Intel XEON processor scalable family while Skylake-SP is the first generation. Both Skylake-SP and Cascadelake-SP has the same family (6h) and model (55h), but with difference stepping number. In the process of identifying candidate CPU, the stepping number is not irrelevant any more. The CPU refresh from Skylake-SP to Cascadelake-SP is this kind of example. This patch add the stepping number as another factor to identify future Intel CPU. Signed-off-by: Wang Huaqiang <huaqiang.wang@intel.com> --- src/cpu/cpu_x86.c | 60 ++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c index ebfa74f..20b471b 100644 --- a/src/cpu/cpu_x86.c +++ b/src/cpu/cpu_x86.c @@ -615,8 +615,14 @@ x86DataToSignatureFull(const virCPUx86Data *data, } -/* Mask out irrelevant bits (R and Step) from processor signature. */ -#define SIGNATURE_MASK 0x0fff3ff0 +#define SIGNATURE_MASK 0x0fff3fff +#define SIGNATURE_MASK_STEPPING 0x0000000f +#define SIGNATURE_MASK_FAMILYMODEL 0x0fff3ff0 + +#define SIGNATURE(sig) (sig & SIGNATURE_MASK) +#define STEPPING(sig) (sig & SIGNATURE_MASK_STEPPING) +#define FAMILYMODEL(sig) (sig & SIGNATURE_MASK_FAMILYMODEL) + static uint32_t x86DataToSignature(const virCPUx86Data *data) @@ -627,7 +633,7 @@ x86DataToSignature(const virCPUx86Data *data) if (!(cpuid = x86DataCpuid(data, &leaf1))) return 0; - return cpuid->eax & SIGNATURE_MASK; + return SIGNATURE(cpuid->eax); } @@ -1203,6 +1209,7 @@ x86ModelParse(xmlXPathContextPtr ctxt, if (virXPathBoolean("boolean(./signature)", ctxt)) { unsigned int sigFamily = 0; unsigned int sigModel = 0; + unsigned int sigStepping = 0; int rc; rc = virXPathUInt("string(./signature/@family)", ctxt, &sigFamily); @@ -1221,7 +1228,12 @@ x86ModelParse(xmlXPathContextPtr ctxt, goto cleanup; } - model->signature = x86MakeSignature(sigFamily, sigModel, 0); + /* CPU stepping number will be used if './signature/@stepping' is present */ + rc = virXPathUInt("string(./signature/@stepping)", ctxt, &sigStepping); + if (rc < 0) + sigStepping = 0; + + model->signature = x86MakeSignature(sigFamily, sigModel, sigStepping); } if (virXPathBoolean("boolean(./vendor)", ctxt)) { @@ -1675,6 +1687,13 @@ virCPUx86Compare(virCPUDefPtr host, * Checks whether a candidate model is a better fit for the CPU data than the * current model. * + * Using family/model along with an optional stepping number to select candidate + * CPU. If stepping is 0, consider which might be optional. + * + * If not considering the stepping number, we want to select a model with + * family/model equal to family/model of the real CPU. Once we found such + * model, we only consider candidates with matching family/model. + * * Returns 0 if current is better, * 1 if candidate is better, * 2 if candidate is the best one (search should stop now). @@ -1707,12 +1726,22 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current, return 1; } - /* Ideally we want to select a model with family/model equal to - * family/model of the real CPU. Once we found such model, we only - * consider candidates with matching family/model. - */ + if (STEPPING(current->signature) && current->signature != signature) { + VIR_DEBUG("%s is dropped due to signature stepping mismatch, try %s", + cpuCurrent->model, cpuCandidate->model); + return 1; + } + if (signature && - current->signature == signature && + FAMILYMODEL(current->signature) == FAMILYMODEL(signature) && + FAMILYMODEL(candidate->signature) != FAMILYMODEL(signature)) { + VIR_DEBUG("%s differs in signature from matching %s", + cpuCandidate->model, cpuCurrent->model); + return 0; + } + + if (signature && STEPPING(candidate->signature) && + FAMILYMODEL(current->signature) == FAMILYMODEL(signature) && candidate->signature != signature) { VIR_DEBUG("%s differs in signature from matching %s", cpuCandidate->model, cpuCurrent->model); @@ -1725,12 +1754,19 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current, return 1; } + if (signature && STEPPING(candidate->signature) && + FAMILYMODEL(current->signature) == FAMILYMODEL(signature) && + candidate->signature == signature) { + VIR_DEBUG("%s provides matching signature", cpuCandidate->model); + return 1; + } + /* Prefer a candidate with matching signature even though it would * result in longer list of features. */ - if (signature && - candidate->signature == signature && - current->signature != signature) { + if (signature&& + FAMILYMODEL(candidate->signature) == FAMILYMODEL(signature) && + FAMILYMODEL(current->signature) != FAMILYMODEL(signature)) { VIR_DEBUG("%s provides matching signature", cpuCandidate->model); return 1; } -- 2.7.4
Cascadelake Server CPU is introduced in QEMU by commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8, add the CPU model in libvirt accordingly. Signed-off-by: Wang Huaqiang <huaqiang.wang@intel.com> --- src/cpu_map/Makefile.inc.am | 1 + src/cpu_map/index.xml | 1 + src/cpu_map/x86_Cascadelake-Server.xml | 83 ++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 src/cpu_map/x86_Cascadelake-Server.xml diff --git a/src/cpu_map/Makefile.inc.am b/src/cpu_map/Makefile.inc.am index 9eeb33e..c74164c 100644 --- a/src/cpu_map/Makefile.inc.am +++ b/src/cpu_map/Makefile.inc.am @@ -21,6 +21,7 @@ cpumap_DATA = \ cpu_map/x86_coreduo.xml \ cpu_map/x86_cpu64-rhel5.xml \ cpu_map/x86_cpu64-rhel6.xml \ + cpu_map/x86_Cascadelake-Server.xml \ cpu_map/x86_EPYC.xml \ cpu_map/x86_EPYC-IBRS.xml \ cpu_map/x86_Haswell.xml \ diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml index dccda39..8d31a48 100644 --- a/src/cpu_map/index.xml +++ b/src/cpu_map/index.xml @@ -48,6 +48,7 @@ <include filename="x86_Skylake-Server-IBRS.xml"/> <include filename="x86_Icelake-Client.xml"/> <include filename="x86_Icelake-Server.xml"/> + <include filename="x86_Cascadelake-Server.xml"/> <!-- AMD CPUs --> <include filename="x86_athlon.xml"/> diff --git a/src/cpu_map/x86_Cascadelake-Server.xml b/src/cpu_map/x86_Cascadelake-Server.xml new file mode 100644 index 0000000..cbf6ea9 --- /dev/null +++ b/src/cpu_map/x86_Cascadelake-Server.xml @@ -0,0 +1,83 @@ +<cpus> + <model name='Cascadelake-Server'> + <signature family='6' model='85' stepping='6'/> + <vendor name='Intel'/> + <feature name='3dnowprefetch'/> + <feature name='abm'/> + <feature name='adx'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='arat'/> + <feature name='avx'/> + <feature name='avx2'/> + <feature name='avx512bw'/> + <feature name='avx512cd'/> + <feature name='avx512dq'/> + <feature name='avx512f'/> + <feature name='avx512vl'/> + <feature name='avx512vnni'/> + <feature name='bmi1'/> + <feature name='bmi2'/> + <feature name='clflush'/> + <feature name='clflushopt'/> + <feature name='clwb'/> + <feature name='cmov'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='erms'/> + <feature name='f16c'/> + <feature name='fma'/> + <feature name='fpu'/> + <feature name='fsgsbase'/> + <feature name='fxsr'/> + <feature name='hle'/> + <feature name='intel-pt'/> + <feature name='invpcid'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='movbe'/> + <feature name='mpx'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <!-- 'ospke' is a dynamic feature and cannot be enabled manually + see QEMU's commit 9ccb9784b57 for more details --> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pcid'/> + <feature name='pclmuldq'/> + <feature name='pdpe1gb'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='pku'/> + <feature name='rdrand'/> + <feature name='rdseed'/> + <feature name='rdtscp'/> + <feature name='rtm'/> + <feature name='sep'/> + <feature name='smap'/> + <feature name='smep'/> + <feature name='spec-ctrl'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='vme'/> + <feature name='x2apic'/> + <feature name='xgetbv1'/> + <feature name='xsave'/> + <feature name='xsavec'/> + <feature name='xsaveopt'/> + </model> +</cpus> -- 2.7.4
participants (1)
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Wang Huaqiang