[libvirt] [PATCH] cpu: Add cpu definition for Intel Sandy Bridge cpu type

This patch adds support for the new tsc-deadline feature flag and a new model to the supported model list describing the Intel Sandy Bridge platform. --- Patches adding the SandyBridge cpu type in qemu are on review and not upstream yet. Please don't prioritize this patch. I sent it for review as the chance that nothing will change is greater than I'll have to post another version. Qemu upstream review: http://lists.nongnu.org/archive/html/qemu-devel/2012-03/msg00914.html (I'll push this only after qemu will add this functionality upstream) Review help (c&p from the patches): tsc-deadline flag: static const char *ext_feature_name[] = { "fma", "cx16", "xtpr", "pdcm", NULL, NULL, "dca", "sse4.1|sse4_1", "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", - NULL, "aes", "xsave", "osxsave", + "tsc-deadline", "aes", "xsave", "osxsave", "avx", NULL, NULL, "hypervisor", }; SandyBridge model: [cpudef] + name = "SandyBridge" + level = "0xd" + vendor = "GenuineIntel" + family = "6" + model = "42" + stepping = "1" + feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" + feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3" + extfeature_edx = "i64 rdtscp nx syscall " + extfeature_ecx = "lahf_lm" + xlevel = "0x8000000A" + model_id = "Intel Xeon E312xx (Sandy Bridge)" (note that the sse3 flag is in libvirt known as pni and i64 is known as lm) src/cpu/cpu_map.xml | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml index 7ef230e..f79a727 100644 --- a/src/cpu/cpu_map.xml +++ b/src/cpu/cpu_map.xml @@ -160,6 +160,9 @@ <feature name='popcnt'> <!-- CPUID_EXT_POPCNT --> <cpuid function='0x00000001' ecx='0x00800000'/> </feature> + <feature name='tsc-deadline'> + <cpuid function='0x00000001' ecx='0x01000000'/> + </feature> <feature name='aes'> <cpuid function='0x00000001' ecx='0x02000000'/> </feature> @@ -595,6 +598,48 @@ <feature name='aes'/> </model> + <model name='SandyBridge'> + <vendor name='Intel'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='avx'/> + <feature name='clflush'/> + <feature name='cmov'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='fpu'/> + <feature name='fxsr'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pclmuldq'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='rdtscp'/> + <feature name='sep'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='x2apic'/> + <feature name='xsave'/> + </model> + <model name='Opteron_G1'> <vendor name='AMD'/> <feature name='sse2'/> -- 1.7.3.4

On 03/07/2012 02:30 PM, Peter Krempa wrote:
This patch adds support for the new tsc-deadline feature flag and a new model to the supported model list describing the Intel Sandy Bridge platform. --- The Sandy Bridge processor model along with the tsc-deadline feature were just commited to qemu upstream as commits:
commit eaf3f0974ba48e3ebf76b331101ad333957432af Author: Eduardo Habkost <ehabkost@redhat.com> Date: Tue Mar 6 15:11:30 2012 -0300 add "tsc-deadline" flag name to feature_ecx table commit c34ea31416a9631b0a552afa08b99ec29cf44272 Author: Eduardo Habkost <ehabkost@redhat.com> Date: Tue Mar 6 15:11:31 2012 -0300 add SandyBridge CPU model This patches add the definition of a SandyBridge CPU model. Peter

On 03/07/2012 06:30 AM, Peter Krempa wrote:
This patch adds support for the new tsc-deadline feature flag and a new model to the supported model list describing the Intel Sandy Bridge platform. ---
ACK. That promised followup patch that sorts things into bit order would be helpful :) -- Eric Blake eblake@redhat.com +1-919-301-3266 Libvirt virtualization library http://libvirt.org

On 03/13/2012 08:01 PM, Eric Blake wrote:
On 03/07/2012 06:30 AM, Peter Krempa wrote:
This patch adds support for the new tsc-deadline feature flag and a new model to the supported model list describing the Intel Sandy Bridge platform. ---
ACK. That promised followup patch that sorts things into bit order would be helpful :)
Thanks; pushed. Martin told me something of such a cleanup, so I'll notify him. Peter
participants (2)
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Eric Blake
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Peter Krempa