[libvirt PATCH 0/7] Define and enable Snowridge CPU model

This series adds and enables the Snowridge CPU model. Note that qemu currently uses the same model ID for Icelake-Server [1] and Snowridge [2]. The correct ID for Icelake is 106 [3], a mistake that has been fixed in libvirt already [4], but is still missing in qemu [5]. [1] https://git.qemu.org/?p=3Dqemu.git;a=3Dblob;f=3Dtarget/i386/cpu.c;h=3D354= 59a38bb1ce7180c5c28e6e215489ef35d3bfe;hb=3DHEAD#l3409 [2] https://git.qemu.org/?p=3Dqemu.git;a=3Dblob;f=3Dtarget/i386/cpu.c;h=3D354= 59a38bb1ce7180c5c28e6e215489ef35d3bfe;hb=3DHEAD#l3661 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/a= rch/x86/include/asm/intel-family.h#n80 [4] https://gitlab.com/libvirt/libvirt/-/commit/1278ac6265589cd83cc2e661056c8= 60e98105507 [5] https://lists.nongnu.org/archive/html/qemu-devel/2020-12/msg00599.html Tim Wiederhake (7): cputestdata: Add test data for Snowridge cpu_map: Add support for fsrm CPU feature cpu_map: Add support for core-capability CPU feature cputestdata: Snowridge: Update with core-capability CPU feature cpu_map: Add support for split-lock-detect CPU feature cputestdata: Snowridge: Update with split-lock-detect feature cpu_map: Define and enable Snowridge model src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/x86_Snowridge.xml | 71 + src/cpu_map/x86_features.xml | 11 + ...64-cpuid-Atom-P5362-processor-disabled.xml | 9 + ..._64-cpuid-Atom-P5362-processor-enabled.xml | 10 + .../x86_64-cpuid-Atom-P5362-processor.json | 2415 +++++++++++++++++ .../x86_64-cpuid-Atom-P5362-processor.xml | 61 + .../x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + .../x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 25 files changed, 2596 insertions(+) create mode 100644 src/cpu_map/x86_Snowridge.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disab= led.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabl= ed.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.xml --=20 2.26.2

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- ...64-cpuid-Atom-P5362-processor-disabled.xml | 8 + ..._64-cpuid-Atom-P5362-processor-enabled.xml | 10 + .../x86_64-cpuid-Atom-P5362-processor.json | 2415 +++++++++++++++++ .../x86_64-cpuid-Atom-P5362-processor.xml | 61 + 4 files changed, 2494 insertions(+) create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabled.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.xml diff --git a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml new file mode 100644 index 0000000000..842c7b4a2a --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml @@ -0,0 +1,8 @@ +<!-- Features disabled by QEMU --> +<cpudata arch='x86'> + <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x080041dc' edx='0xb0600000'/> + <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x02001000' ecx='0x00000020' edx='0x00000000'/> + <cpuid eax_in='0x0000000f' ecx_in='0x01' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000006'/> + <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/> + <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> +</cpudata> diff --git a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabled.xml b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabled.xml new file mode 100644 index 0000000000..2214d448ef --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabled.xml @@ -0,0 +1,10 @@ +<!-- Features enabled by QEMU --> +<cpudata arch='x86'> + <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0xc7f8a223' edx='0x0f8bfbff'/> + <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x21940283' ecx='0x1a400104' edx='0xac000400'/> + <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x0000000f' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000101' edx='0x28100800'/> + <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x00000000' ebx='0x01009000' ecx='0x00000000' edx='0x00000000'/> + <msr index='0x10a' edx='0x00000000' eax='0x0000006b'/> +</cpudata> diff --git a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json new file mode 100644 index 0000000000..4e5545f177 --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json @@ -0,0 +1,2415 @@ +{ + "return": { + "model": { + "name": "base", + "props": { + "vmx-entry-load-rtit-ctl": false, + "phys-bits": 0, + "core-id": -1, + "xlevel": 2147483656, + "cmov": true, + "ia64": false, + "ssb-no": false, + "aes": true, + "vmx-apicv-xapic": true, + "mmx": true, + "rdpid": true, + "vmx-page-walk-4": true, + "vmx-page-walk-5": false, + "arat": true, + "gfni": true, + "vmx-desc-exit": true, + "ibrs-all": true, + "pause-filter": false, + "xsavec": true, + "intel-pt": false, + "vmx-cr8-store-exit": true, + "hv-frequencies": false, + "tsc-frequency": 0, + "vmx-rdseed-exit": true, + "xd": true, + "x-intel-pt-auto-level": false, + "hv-vendor-id": "", + "vmx-eptp-switching": true, + "kvm-asyncpf": true, + "kvm_asyncpf": true, + "perfctr_core": false, + "perfctr-core": false, + "mpx": false, + "pbe": false, + "decodeassists": false, + "avx512cd": false, + "vmx-exit-load-efer": true, + "vmx-exit-clear-bndcfgs": false, + "sse4_1": true, + "sse4.1": true, + "sse4-1": true, + "family": 6, + "legacy-cache": true, + "vmx-vmwrite-vmexit-fields": true, + "vmx-vnmi": true, + "vmx-true-ctls": true, + "host-phys-bits-limit": 48, + "vmx-ept-execonly": true, + "vmx-exit-save-efer": true, + "vmx-invept-all-context": true, + "vmware-cpuid-freq": true, + "wbnoinvd": false, + "avx512f": false, + "hv-stimer-direct": false, + "msr": true, + "mce": true, + "mca": true, + "hv-runtime": false, + "xcrypt": false, + "thread-id": -1, + "vmx-exit-load-pat": true, + "vmx-intr-exit": true, + "min-level": 27, + "vmx-flexpriority": true, + "xgetbv1": true, + "cid": false, + "hv-relaxed": false, + "hv-crash": false, + "ds": false, + "fxsr": true, + "avx512-bf16": false, + "vmx-cr8-load-exit": true, + "xsaveopt": true, + "vmx-apicv-vid": true, + "vmx-exit-save-pat": true, + "xtpr": false, + "tsx-ctrl": false, + "vmx-ple": false, + "hv-evmcs": false, + "avx512vl": false, + "avx512-vpopcntdq": false, + "phe": false, + "extapic": false, + "3dnowprefetch": true, + "vmx-vmfunc": true, + "vmx-activity-shutdown": false, + "avx512vbmi2": false, + "vmx-encls-exit": false, + "cr8legacy": false, + "vmx-msr-bitmap": true, + "stibp": true, + "cpuid-0xb": true, + "xcrypt-en": false, + "vmx-mwait-exit": true, + "kvm_pv_eoi": true, + "vmx-pml": true, + "apic-id": 4294967295, + "vmx-nmi-exit": true, + "vmx-invept-single-context-noglobals": true, + "rsba": false, + "pn": false, + "dca": false, + "vendor": "GenuineIntel", + "vmx-unrestricted-guest": true, + "hv-ipi": false, + "vmx-cr3-store-noexit": true, + "pku": false, + "smx": false, + "cmp_legacy": false, + "cmp-legacy": false, + "node-id": -1, + "avx512-4fmaps": false, + "vmcb_clean": false, + "vmcb-clean": false, + "3dnowext": false, + "amd-no-ssb": false, + "hle": false, + "npt": false, + "rdctl-no": true, + "vmx-invvpid": true, + "memory": "/machine/unattached/system[0]", + "clwb": true, + "lbrv": false, + "adx": false, + "ss": true, + "pni": true, + "svm_lock": false, + "svm-lock": false, + "pfthreshold": false, + "smep": true, + "smap": true, + "vmx-invpcid-exit": false, + "x2apic": true, + "avx512vbmi": false, + "avx512vnni": false, + "vmx-apicv-x2apic": true, + "kvm-pv-sched-yield": true, + "hv-stimer": false, + "vmx-invlpg-exit": true, + "x-hv-synic-kvm-only": true, + "vmx-invvpid-all-context": true, + "i64": true, + "vmx-activity-hlt": true, + "flushbyasid": false, + "f16c": false, + "vmx-exit-ack-intr": true, + "ace2-en": false, + "pat": true, + "pae": true, + "sse": true, + "die-id": -1, + "vmx-tsc-offset": true, + "phe-en": false, + "kvm_nopiodelay": true, + "kvm-nopiodelay": true, + "tm": false, + "kvmclock-stable-bit": true, + "vmx-rdtsc-exit": true, + "hypervisor": true, + "vmx-rdtscp-exit": true, + "socket-id": -1, + "mds-no": true, + "pcommit": false, + "vmx-vpid": true, + "syscall": true, + "level": 27, + "avx512dq": false, + "x-migrate-smi-count": false, + "svm": false, + "full-cpuid-auto-level": true, + "hv-reset": false, + "invtsc": false, + "vmx-monitor-exit": true, + "sse3": true, + "sse2": true, + "vmx-wbinvd-exit": true, + "ssbd": true, + "est": false, + "kvm-poll-control": true, + "kvm_poll_control": true, + "avx512ifma": false, + "tm2": false, + "kvm-pv-ipi": true, + "kvm-pv-eoi": true, + "cx8": true, + "vmx-invvpid-single-addr": true, + "waitpkg": false, + "cldemote": true, + "vmx-ept": true, + "hv-reenlightenment": false, + "kvm_mmu": false, + "kvm-mmu": false, + "sse4_2": true, + "sse4.2": true, + "sse4-2": true, + "pge": true, + "fill-mtrr-mask": true, + "avx512bitalg": false, + "nodeid_msr": false, + "vmx-entry-load-bndcfgs": false, + "pdcm": true, + "vmx-exit-clear-rtit-ctl": false, + "movbe": true, + "model": 134, + "nrip_save": false, + "nrip-save": false, + "kvm_pv_unhalt": true, + "ssse3": true, + "sse4a": false, + "vmx-pause-exit": true, + "invpcid": false, + "pdpe1gb": false, + "tsc-deadline": true, + "skip-l1dfl-vmentry": true, + "vmx-exit-load-perf-global-ctrl": false, + "fma": false, + "cx16": true, + "de": true, + "enforce": false, + "stepping": 5, + "xsave": true, + "clflush": true, + "skinit": false, + "tsc": true, + "tce": false, + "fpu": true, + "ibs": false, + "ds_cpl": false, + "ds-cpl": false, + "vmx-exit-nosave-debugctl": true, + "host-phys-bits": true, + "fma4": false, + "vmx-invept": true, + "la57": false, + "osvw": false, + "check": true, + "hv-spinlocks": 4294967295, + "vmx-eptad": true, + "pmu": false, + "pmm": false, + "apic": true, + "vmx-entry-noload-debugctl": true, + "spec-ctrl": true, + "vmx-posted-intr": true, + "vmx-apicv-register": true, + "min-xlevel2": 0, + "tsc-adjust": true, + "tsc_adjust": true, + "kvm-steal-time": true, + "kvm_steal_time": true, + "vmx-zero-len-inject": false, + "kvmclock": true, + "pschange-mc-no": true, + "l3-cache": true, + "vmx-rdrand-exit": true, + "lwp": false, + "hv-passthrough": false, + "amd-ssbd": true, + "ibpb": true, + "xop": false, + "avx": false, + "core-capability": false, + "vmx-invept-single-context": true, + "movdiri": true, + "ace2": false, + "avx512bw": false, + "acpi": false, + "hv-vapic": false, + "fsgsbase": true, + "vmx-ept-1gb": true, + "vmx-ept-2mb": true, + "ht": false, + "vmx-io-exit": true, + "nx": true, + "pclmulqdq": true, + "mmxext": false, + "vaes": false, + "popcnt": true, + "xsaves": true, + "movdir64b": true, + "tcg-cpuid": true, + "vmx-shadow-vmcs": true, + "lm": true, + "vmx-exit-save-preemption-timer": true, + "vmx-entry-load-pat": true, + "vmx-entry-load-perf-global-ctrl": false, + "vmx-io-bitmap": true, + "umip": true, + "vmx-store-lma": true, + "vmx-movdr-exit": true, + "pse": true, + "avx2": false, + "sep": true, + "pclmuldq": true, + "virt-ssbd": false, + "vmx-cr3-load-noexit": true, + "x-hv-max-vps": -1, + "nodeid-msr": false, + "md-clear": true, + "split-lock-detect": false, + "kvm": true, + "misalignsse": false, + "min-xlevel": 2147483656, + "kvm-pv-unhalt": true, + "bmi2": false, + "bmi1": false, + "realized": false, + "tsc_scale": false, + "tsc-scale": false, + "topoext": false, + "hv-vpindex": false, + "hv-no-nonarch-coresharing": "off", + "amd-stibp": true, + "vmx-preemption-timer": true, + "ucode-rev": 0, + "xlevel2": 0, + "clflushopt": true, + "vmx-vnmi-pending": true, + "kvm-no-smi-migration": false, + "monitor": false, + "vmx-vintr-pending": true, + "avx512er": false, + "pmm-en": false, + "pcid": false, + "taa-no": false, + "vmx-secondary-ctls": true, + "arch-capabilities": true, + "vmx-xsaves": true, + "clzero": false, + "3dnow": false, + "erms": true, + "vmx-entry-ia32e-mode": true, + "x-force-features": false, + "lahf_lm": true, + "lahf-lm": true, + "vpclmulqdq": false, + "vmx-ins-outs": true, + "fxsr-opt": false, + "hv-synic": false, + "xstore": false, + "fxsr_opt": false, + "kvm-hint-dedicated": false, + "rtm": false, + "lmce": true, + "hv-time": false, + "perfctr-nb": false, + "perfctr_nb": false, + "ffxsr": false, + "hv-tlbflush": false, + "rdrand": true, + "rdseed": true, + "avx512-4vnniw": false, + "vmx": true, + "vme": true, + "dtes64": false, + "mtrr": true, + "rdtscp": true, + "xsaveerptr": false, + "pse36": true, + "kvm-pv-tlb-flush": true, + "vmx-activity-wait-sipi": false, + "tbm": false, + "wdt": false, + "vmx-rdpmc-exit": true, + "level-func7": 0, + "vmx-entry-load-efer": true, + "vmx-mtf": true, + "pause_filter": false, + "sha-ni": true, + "model-id": "Intel Atom(R) P5362 processor", + "abm": false, + "vmx-ept-advanced-exitinfo": false, + "avx512pf": false, + "vmx-hlt-exit": true, + "xstore-en": false + } + } + }, + "id": "model-expansion" +} + +{ + "return": [ + { + "name": "max", + "typename": "max-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": false + }, + { + "name": "host", + "typename": "host-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": false + }, + { + "name": "base", + "typename": "base-x86_64-cpu", + "unavailable-features": [], + "static": true, + "migration-safe": true + }, + { + "name": "qemu64-v1", + "typename": "qemu64-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "qemu64", + "typename": "qemu64-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "qemu32-v1", + "typename": "qemu32-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "qemu32", + "typename": "qemu32-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "phenom-v1", + "typename": "phenom-v1-x86_64-cpu", + "unavailable-features": [ + "mmxext", + "fxsr-opt", + "pdpe1gb", + "3dnowext", + "3dnow", + "abm", + "sse4a" + ], + "static": false, + "migration-safe": true + }, + { + "name": "phenom", + "typename": "phenom-x86_64-cpu", + "unavailable-features": [ + "mmxext", + "fxsr-opt", + "pdpe1gb", + "3dnowext", + "3dnow", + "abm", + "sse4a" + ], + "static": false, + "migration-safe": true + }, + { + "name": "pentium3-v1", + "typename": "pentium3-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "pentium3", + "typename": "pentium3-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "pentium2-v1", + "typename": "pentium2-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "pentium2", + "typename": "pentium2-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "pentium-v1", + "typename": "pentium-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "pentium", + "typename": "pentium-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "n270-v1", + "typename": "n270-v1-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": "n270", + "typename": "n270-x86_64-cpu", + "unavailable-features": [], + "static": false, + "migration-safe": true + }, + { + "name": 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0000000000..4fe97c0866 --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.xml @@ -0,0 +1,61 @@ +<!-- Intel Atom(R) P5362 processor --> +<cpudata arch='x86'> + <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x0000001b' ebx='0x756e6547' ecx='0x6c65746e' edx='0x49656e69'/> + <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00080665' ebx='0x02800800' ecx='0x4ff8ebff' edx='0xbfebfbff'/> + <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x00feff01' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000004' ecx_in='0x00' eax='0xfc000121' ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/> + <cpuid eax_in='0x00000004' ecx_in='0x01' eax='0xfc000122' ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/> + <cpuid eax_in='0x00000004' ecx_in='0x02' eax='0xfc01c143' ebx='0x0440003f' ecx='0x00000fff' edx='0x00000000'/> + <cpuid eax_in='0x00000004' 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edx='0x0000000d'/> + <cpuid eax_in='0x00000010' ecx_in='0x02' eax='0x00000011' ebx='0x00000000' ecx='0x00000004' edx='0x0000000d'/> + <cpuid eax_in='0x00000010' ecx_in='0x03' eax='0x00000059' ebx='0x00000000' ecx='0x00000004' edx='0x0000000d'/> + <cpuid eax_in='0x00000011' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000012' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000013' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000014' ecx_in='0x00' eax='0x00000001' ebx='0x0000007f' ecx='0x80000007' edx='0x00000000'/> + <cpuid eax_in='0x00000014' ecx_in='0x01' eax='0x02490002' ebx='0x003fffff' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000015' ecx_in='0x00' eax='0x00000002' ebx='0x000000b0' ecx='0x017d7840' edx='0x00000000'/> + <cpuid eax_in='0x00000016' ecx_in='0x00' eax='0x00000898' ebx='0x00000898' ecx='0x00000064' edx='0x00000000'/> + <cpuid eax_in='0x00000017' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000018' ecx_in='0x00' eax='0x00000005' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000018' ecx_in='0x01' eax='0x00000000' ebx='0x00300001' ecx='0x00000001' edx='0x00000121'/> + <cpuid eax_in='0x00000018' ecx_in='0x02' eax='0x00000000' ebx='0x00040001' ecx='0x00000100' edx='0x00000043'/> + <cpuid eax_in='0x00000018' ecx_in='0x03' eax='0x00000000' ebx='0x00040006' ecx='0x00000010' edx='0x00000043'/> + <cpuid eax_in='0x00000018' ecx_in='0x04' eax='0x00000000' ebx='0x00300001' ecx='0x00000001' edx='0x00000122'/> + <cpuid eax_in='0x00000018' ecx_in='0x05' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x00000019' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x0000001a' ecx_in='0x00' eax='0x20000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x0000001b' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x20000000' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x80000008' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000101' edx='0x28100800'/> + <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x65746e49' ebx='0x7441206c' ecx='0x52286d6f' edx='0x35502029'/> + <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x20323633' ebx='0x636f7270' ecx='0x6f737365' edx='0x00000072'/> + <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x12008040' edx='0x00000000'/> + <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/> + <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x0000302a' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/> + <msr index='0xcf' edx='0x00000000' eax='0x00000060'/> + <msr index='0x10a' edx='0x001a8c7f' eax='0xa080036b'/> +</cpudata> -- 2.26.2

On Wed, Jan 06, 2021 at 11:05:05 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- ...64-cpuid-Atom-P5362-processor-disabled.xml | 8 + ..._64-cpuid-Atom-P5362-processor-enabled.xml | 10 + .../x86_64-cpuid-Atom-P5362-processor.json | 2415 +++++++++++++++++ .../x86_64-cpuid-Atom-P5362-processor.xml | 61 +
We should remove the "-processor" part of the file names as it's redundant. I'll send a patch for cpu-gather.py script to do that automatically next time we parse data from such CPU.
4 files changed, 2494 insertions(+) create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-enabled.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.json create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-P5362-processor.xml
The new test files are not used anywhere. The cputest.c file should be updated to start testing this CPU: DO_TEST_CPUID(VIR_ARCH_X86_64, "Atom-P5362", JSON_MODELS_REQUIRED); and once done, you can run VIR_TEST_REGENERATE_OUTPUT=1 tests/cputest to generate the test results. And of course they should be manually checked whether they make sense. This will show the CPU detection completely fails on this CPU as it is detected as either IvyBridge or Westmere three different CPU models depending on where the CPU model is supposed to be used (capabilities vs. domain capabilities). Jirka

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + 3 files changed, 5 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a55f52b16c..b0bf22d916 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -339,6 +339,9 @@ <feature name='avx512-4fmaps'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000008'/> </feature> + <feature name='fsrm'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000010'/> + </feature> <feature name='md-clear'> <!-- md_clear --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000400'/> </feature> diff --git a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml index 9b75ace710..3a71b28cfb 100644 --- a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml +++ b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml @@ -24,6 +24,7 @@ <feature policy='require' name='sha-ni'/> <feature policy='require' name='ospke'/> <feature policy='require' name='rdpid'/> + <feature policy='require' name='fsrm'/> <feature policy='require' name='stibp'/> <feature policy='require' name='arch-capabilities'/> <feature policy='require' name='xsaves'/> diff --git a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml index efbf9d363b..1582de0422 100644 --- a/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml +++ b/tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml @@ -25,6 +25,7 @@ <feature name='sha-ni'/> <feature name='ospke'/> <feature name='rdpid'/> + <feature name='fsrm'/> <feature name='stibp'/> <feature name='arch-capabilities'/> <feature name='xsaves'/> -- 2.26.2

On Wed, Jan 06, 2021 at 11:05:06 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 + tests/cputestdata/x86_64-cpuid-Ice-Lake-Server-host.xml | 1 + 3 files changed, 5 insertions(+)
While not always required, it's a good idea to run tests/cputestdata/cpu-gather.py diff \ tests/cputestdata/x86_64-cpuid-*.json after adding new features to the CPU map (as mentioned at the top of x86_features.xml file). Jirka

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index b0bf22d916..a5a987deba 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -357,6 +357,9 @@ <feature name='arch-capabilities'> <!-- arch_capabilities, arch-facilities --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x20000000'/> </feature> + <feature name='core-capability'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x40000000'/> + </feature> <feature name='ssbd'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x80000000'/> </feature> -- 2.26.2

On Wed, Jan 06, 2021 at 11:05:07 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index b0bf22d916..a5a987deba 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -357,6 +357,9 @@ <feature name='arch-capabilities'> <!-- arch_capabilities, arch-facilities --> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x20000000'/> </feature> + <feature name='core-capability'> + <cpuid eax_in='0x07' ecx_in='0x00' edx='0x40000000'/> + </feature> <feature name='ssbd'> <cpuid eax_in='0x07' ecx_in='0x00' edx='0x80000000'/> </feature>
The following patch has to be squashed in this one once Atom-P5362 test case is added to cputest in patch 1/7 and cputest output files need to be regenerated here to show core-capability was properly detected in Atom-P5362's CPUID data. Jirka

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- .../cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml index 842c7b4a2a..50e8084140 100644 --- a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml @@ -1,7 +1,7 @@ <!-- Features disabled by QEMU --> <cpudata arch='x86'> <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x080041dc' edx='0xb0600000'/> - <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x02001000' ecx='0x00000020' edx='0x00000000'/> + <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x02001000' ecx='0x00000020' edx='0x40000000'/> <cpuid eax_in='0x0000000f' ecx_in='0x01' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000006'/> <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> -- 2.26.2

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus> -- 2.26.2

On Wed, Jan 06, 2021 at 11:05:09 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/x86_features.xml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index a5a987deba..4836595a8c 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -581,4 +581,9 @@ <feature name='taa-no'> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </feature> + + <!-- IA32_CORE_CAPABILITIES features --> + <feature name='split-lock-detect'> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> + </feature> </cpus>
The exact same comment I made for patch 4/7 applies here. Jirka

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml index 50e8084140..81ffa7bfd3 100644 --- a/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml +++ b/tests/cputestdata/x86_64-cpuid-Atom-P5362-processor-disabled.xml @@ -4,5 +4,6 @@ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000' ebx='0x02001000' ecx='0x00000020' edx='0x40000000'/> <cpuid eax_in='0x0000000f' ecx_in='0x01' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000006'/> <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000' ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/> + <msr index='0xcf' edx='0x00000000' eax='0x00000020'/> <msr index='0x10a' edx='0x00000000' eax='0x00000100'/> </cpudata> -- 2.26.2

Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/x86_Snowridge.xml | 71 +++++++++++++++++++ .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 18 files changed, 88 insertions(+) create mode 100644 src/cpu_map/x86_Snowridge.xml diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml index 065d9aede0..2e0685df68 100644 --- a/src/cpu_map/index.xml +++ b/src/cpu_map/index.xml @@ -55,6 +55,7 @@ <include filename='x86_Icelake-Server.xml'/> <include filename='x86_Icelake-Server-noTSX.xml'/> <include filename='x86_Cooperlake.xml'/> + <include filename='x86_Snowridge.xml'/> <!-- AMD CPUs --> <include filename='x86_athlon.xml'/> diff --git a/src/cpu_map/meson.build b/src/cpu_map/meson.build index 8efa9207a2..48f69f623c 100644 --- a/src/cpu_map/meson.build +++ b/src/cpu_map/meson.build @@ -72,6 +72,7 @@ cpumap_data = [ 'x86_Skylake-Server-IBRS.xml', 'x86_Skylake-Server-noTSX-IBRS.xml', 'x86_Skylake-Server.xml', + 'x86_Snowridge.xml', 'x86_vendors.xml', 'x86_Westmere-IBRS.xml', 'x86_Westmere.xml', diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml new file mode 100644 index 0000000000..c0b94834ce --- /dev/null +++ b/src/cpu_map/x86_Snowridge.xml @@ -0,0 +1,71 @@ +<cpus> + <model name='Snowridge'> + <decode host='on' guest='on'/> + <signature family='6' model='134'/> + <vendor name='Intel'/> + <feature name='3dnowprefetch'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='arat'/> + <feature name='arch-capabilities'/> + <feature name='cldemote'/> + <feature name='clflush'/> + <feature name='clflushopt'/> + <feature name='clwb'/> + <feature name='cmov'/> + <feature name='core-capability'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='erms'/> + <feature name='fpu'/> + <feature name='fsgsbase'/> + <feature name='fxsr'/> + <feature name='gfni'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='movbe'/> + <feature name='movdir64b'/> + <feature name='movdiri'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pclmuldq'/> + <feature name='pdpe1gb'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='rdrand'/> + <feature name='rdseed'/> + <feature name='rdtscp'/> + <feature name='sep'/> + <feature name='sha-ni'/> + <feature name='smap'/> + <feature name='smep'/> + <feature name='spec-ctrl'/> + <feature name='split-lock-detect'/> + <feature name='ssbd'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='umip'/> + <feature name='vme'/> + <feature name='x2apic'/> + <feature name='xgetbv1'/> + <feature name='xsave'/> + <feature name='xsavec'/> + <feature name='xsaveopt'/> + </model> +</cpus> diff --git a/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml index 3a7e01c809..39050a2b7d 100644 --- a/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0-q35.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='yes'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml index 64bbef0a42..dd2b28fe43 100644 --- a/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0-tcg.x86_64.xml @@ -76,6 +76,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='no'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='no'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.1.0.x86_64.xml b/tests/domaincapsdata/qemu_4.1.0.x86_64.xml index 577b7f439d..1fc14a7dd6 100644 --- a/tests/domaincapsdata/qemu_4.1.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.1.0.x86_64.xml @@ -67,6 +67,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> <model usable='yes'>Skylake-Client-IBRS</model> diff --git a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml index 1a65f6e727..a57529ee03 100644 --- a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml index 43d6d27e98..e19f59b9d2 100644 --- a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml @@ -76,6 +76,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='no'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml index da9cf56ba5..6013d01e54 100644 --- a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml index a42bec4d87..4a30b558c0 100644 --- a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml index df562b5383..18516adb71 100644 --- a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml @@ -75,6 +75,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml index 57638696f8..abaa54d493 100644 --- a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml @@ -68,6 +68,7 @@ <model usable='no'>athlon</model> <model usable='yes'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml index 9fba7f33ab..39452be343 100644 --- a/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0-q35.x86_64.xml @@ -70,6 +70,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml index 0069c912dc..cbecc55a77 100644 --- a/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0-tcg.x86_64.xml @@ -75,6 +75,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.1.0.x86_64.xml b/tests/domaincapsdata/qemu_5.1.0.x86_64.xml index 1984ed2e07..d7477951b6 100644 --- a/tests/domaincapsdata/qemu_5.1.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.1.0.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml index 5a3777f6f8..7111bdf2c5 100644 --- a/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0-q35.x86_64.xml @@ -70,6 +70,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml index 1b9f986a95..9d2e870b1c 100644 --- a/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0-tcg.x86_64.xml @@ -75,6 +75,7 @@ <model usable='yes'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> diff --git a/tests/domaincapsdata/qemu_5.2.0.x86_64.xml b/tests/domaincapsdata/qemu_5.2.0.x86_64.xml index ab6455c3fc..d8113c4e92 100644 --- a/tests/domaincapsdata/qemu_5.2.0.x86_64.xml +++ b/tests/domaincapsdata/qemu_5.2.0.x86_64.xml @@ -69,6 +69,7 @@ <model usable='no'>athlon</model> <model usable='no'>Westmere-IBRS</model> <model usable='yes'>Westmere</model> + <model usable='no'>Snowridge</model> <model usable='no'>Skylake-Server-noTSX-IBRS</model> <model usable='no'>Skylake-Server-IBRS</model> <model usable='no'>Skylake-Server</model> -- 2.26.2

On Wed, Jan 06, 2021 at 11:05:11 +0100, Tim Wiederhake wrote:
Signed-off-by: Tim Wiederhake <twiederh@redhat.com> --- src/cpu_map/index.xml | 1 + src/cpu_map/meson.build | 1 + src/cpu_map/x86_Snowridge.xml | 71 +++++++++++++++++++ .../domaincapsdata/qemu_4.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 1 + .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 1 + tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 1 + 18 files changed, 88 insertions(+) create mode 100644 src/cpu_map/x86_Snowridge.xml
By adding the new test case to cputest in 1/7 and updating the test results here, we could see the CPU starts to be properly detected as Snowridge. Even though capabilities XML would still report it as Westmere-IBRS because the host CPU does not support pdpe1gb feature included in Snowridge CPU model. Jirka

On Wed, Jan 06, 2021 at 11:05:04 +0100, Tim Wiederhake wrote:
This series adds and enables the Snowridge CPU model.
Note that qemu currently uses the same model ID for Icelake-Server [1] and Snowridge [2]. The correct ID for Icelake is 106 [3], a mistake that has been fixed in libvirt already [4], but is still missing in qemu [5].
[1] https://git.qemu.org/?p=3Dqemu.git;a=3Dblob;f=3Dtarget/i386/cpu.c;h=3D354= 59a38bb1ce7180c5c28e6e215489ef35d3bfe;hb=3DHEAD#l3409 [2] https://git.qemu.org/?p=3Dqemu.git;a=3Dblob;f=3Dtarget/i386/cpu.c;h=3D354= 59a38bb1ce7180c5c28e6e215489ef35d3bfe;hb=3DHEAD#l3661 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/a= rch/x86/include/asm/intel-family.h#n80 [4] https://gitlab.com/libvirt/libvirt/-/commit/1278ac6265589cd83cc2e661056c8= 60e98105507 [5] https://lists.nongnu.org/archive/html/qemu-devel/2020-12/msg00599.html
Tim Wiederhake (7): cputestdata: Add test data for Snowridge cpu_map: Add support for fsrm CPU feature cpu_map: Add support for core-capability CPU feature cputestdata: Snowridge: Update with core-capability CPU feature cpu_map: Add support for split-lock-detect CPU feature cputestdata: Snowridge: Update with split-lock-detect feature cpu_map: Define and enable Snowridge model
Since I already made the suggested changes while reviewing the series to check everything is correct and working as expected, I squashed them into your patches and pushed the result. The required changes were fairly minor: removing "-processor" from the test file names and adding a new test case to cputest.c to make use of the new data in patch 1. So really nothing to require a new version of this series. The rest was just making sure the new test results are updated in each commit to make sure cputest passes. Reviewed-by: Jiri Denemark <jdenemar@redhat.com> And pushed, thanks.
participants (2)
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Jiri Denemark
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Tim Wiederhake