[PATCH v3 0/3] qemu: Support vCMDQ
Hi, This is a follow up to the previous RFC patchset [0] for supporting Tegra241 vCMDQ. This patchset is tested with Shameer's qemu series for vCMDQ support. The accelerated SMMUv3 series for qemu and Libvirt are pre-requisites for vCMDQ support, as accelerated SMMUv3 must be enabled alongside vCMDQ. A new 'cmdqv' <iommu> driver attribute is introduced to toggle enabling vCMDQ support. For instance, specifying hostdevs associated with multiple accelerated SMMUs + CMDQV enabled, configured to be routed to pcie-expander-bus controllers in a way where VFIO device to SMMUv3 associations are matched with the host: <devices> ... <controller type='pci' index='1' model='pcie-expander-bus'> <model name='pxb-pcie'/> <target busNr='252'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/> </controller> <controller type='pci' index='2' model='pcie-expander-bus'> <model name='pxb-pcie'/> <target busNr='248'/> <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/> </controller> ... <controller type='pci' index='21' model='pcie-root-port'> <model name='pcie-root-port'/> <target chassis='21' port='0x0'/> <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> </controller> <controller type='pci' index='22' model='pcie-root-port'> <model name='pcie-root-port'/> <target chassis='22' port='0xa8'/> <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/> </controller> ... <hostdev mode='subsystem' type='pci' managed='no'> <source> <address domain='0x0009' bus='0x01' slot='0x00' function='0x0'/> </source> <address type='pci' domain='0x0000' bus='0x15' slot='0x00' function='0x0'/> </hostdev> <hostdev mode='subsystem' type='pci' managed='no'> <source> <address domain='0x0019' bus='0x01' slot='0x00' function='0x0'/> </source> <address type='pci' domain='0x0000' bus='0x16' slot='0x00' function='0x0'/> </hostdev> <iommu model='smmuv3'> <driver pciBus='1' accel='on' ats='on' ril='on' ssidsize='20' oas='44' cmdqv='on'/> </iommu> <iommu model='smmuv3'> <driver pciBus='2' accel='on' ats='on' ril='on' ssidsize='20' oas='44' cmdqv='on'/> </iommu> </devices> This would get translated to a qemu command line with the arguments below: -device '{"driver":"pxb-pcie","bus_nr":252,"id":"pci.1","bus":"pcie.0","addr":"0x1"}' \ -device '{"driver":"pxb-pcie","bus_nr":248,"id":"pci.2","bus":"pcie.0","addr":"0x2"}' \ -device '{"driver":"pcie-root-port","port":0,"chassis":21,"id":"pci.21","bus":"pci.1","addr":"0x0"}' \ -device '{"driver":"pcie-root-port","port":168,"chassis":22,"id":"pci.22","bus":"pci.2","addr":"0x0"}' \ -device '{"driver":"arm-smmuv3","primary-bus":"pci.1","id":"iommu0","accel":true,"ats":true,"cmdqv":"on","ril":true,"pasid":true,"oas":44}' \ -device '{"driver":"arm-smmuv3","primary-bus":"pci.2","id":"iommu1","accel":true,"ats":true,"cmdqv":"on","ril":true,"pasid":true,"oas":44}' \ -device '{"driver":"vfio-pci","host":"0009:01:00.0","id":"hostdev0","bus":"pci.21","addr":"0x0"}' \ -device '{"driver":"vfio-pci","host":"0019:01:00.0","id":"hostdev1","bus":"pci.22","addr":"0x0"}' \ This series is on Github: https://github.com/NathanChenNVIDIA/libvirt/tree/cmdqv-v3/ Thanks, Nathan Changes from v2: - Add QEMU capabilities support for cmdqv - Change QEMU command line parameter to expect OnOffAuto string Changes from v1: - Remove 'identifier' attribute for SMMUv3 - Change QEMU command line property from 'tegra241-cmdqv' to 'cmdqv' - Support QEMU OnOffAuto CMDQV property instead of expecting a bool [0] https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/CE6U4... Nathan Chen (3): qemu: introduce QEMU_CAPS_ARM_SMMUV3_CMDQV qemu: add IOMMU attribute "cmdqv" for smmuv3 tests: qemuxmlconfdata: provide cmdqv sample XML and CLI args docs/formatdomain.rst | 6 ++ src/conf/domain_conf.c | 15 +++++ src/conf/domain_conf.h | 1 + src/conf/domain_validate.c | 6 +- src/conf/schemas/domaincommon.rng | 5 ++ src/qemu/qemu_capabilities.c | 4 ++ src/qemu/qemu_capabilities.h | 3 + src/qemu/qemu_command.c | 1 + src/qemu/qemu_validate.c | 8 +++ .../caps_11.1.0_aarch64.xml | 1 + ...v3-pci-bus-accel-cmdqv.aarch64-latest.args | 40 +++++++++++++ ...uv3-pci-bus-accel-cmdqv.aarch64-latest.xml | 59 +++++++++++++++++++ .../iommu-smmuv3-pci-bus-accel-cmdqv.xml | 49 +++++++++++++++ tests/qemuxmlconftest.c | 1 + 14 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.args create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.xml create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.xml -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Probe the arm-smmuv3 cmdqv device property via device-list-properties, gated on QEMU_CAPS_DEVICE_ARM_SMMUV3. Reject domain configs that set cmdqv when the QEMU binary lacks the property. Signed-off-by: Nathan Chen <nathanc@nvidia.com> --- src/qemu/qemu_capabilities.c | 4 ++++ src/qemu/qemu_capabilities.h | 3 +++ src/qemu/qemu_validate.c | 9 +++++++++ tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml | 1 + 4 files changed, 17 insertions(+) diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c index 6abb179951..a0fe9b36a6 100644 --- a/src/qemu/qemu_capabilities.c +++ b/src/qemu/qemu_capabilities.c @@ -771,6 +771,9 @@ VIR_ENUM_IMPL(virQEMUCaps, "arm-smmuv3", /* QEMU_CAPS_DEVICE_ARM_SMMUV3 */ "arm-smmuv3.smmu_per_bus", /* QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS */ "arm-smmuv3.accel", /* QEMU_CAPS_ARM_SMMUV3_ACCEL */ + + /* 500 */ + "arm-smmuv3.cmdqv", /* QEMU_CAPS_ARM_SMMUV3_CMDQV */ ); @@ -1651,6 +1654,7 @@ static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsAMDIOMMU[] = { static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsArmSmmuv3[] = { { "smmu_per_bus", QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, NULL }, { "accel", QEMU_CAPS_ARM_SMMUV3_ACCEL, NULL }, + { "cmdqv", QEMU_CAPS_ARM_SMMUV3_CMDQV, NULL }, }; /* see documentation for virQEMUQAPISchemaPathGet for the query format */ diff --git a/src/qemu/qemu_capabilities.h b/src/qemu/qemu_capabilities.h index 4563e15156..91c4852ea7 100644 --- a/src/qemu/qemu_capabilities.h +++ b/src/qemu/qemu_capabilities.h @@ -746,6 +746,9 @@ typedef enum { /* virQEMUCapsFlags grouping marker for syntax-check */ QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, /* arm-smmuv3.smmu_per_bus */ QEMU_CAPS_ARM_SMMUV3_ACCEL, /* arm-smmuv3.accel */ + /* 500 */ + QEMU_CAPS_ARM_SMMUV3_CMDQV, /* arm-smmuv3.cmdqv */ + QEMU_CAPS_LAST /* this must always be the last item */ } virQEMUCapsFlags; diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index 61f3bd3278..25527ca2cc 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5829,6 +5829,15 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMMUDef *iommu, return -1; } + /* cmdqv was added after accel; do not treat ACCEL as a proxy for it. */ + if (iommu->model == VIR_DOMAIN_IOMMU_MODEL_SMMUV3 && + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT && + !virQEMUCapsGet(qemuCaps, QEMU_CAPS_ARM_SMMUV3_CMDQV)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("iommu: cmdqv is not supported with this QEMU binary")); + return -1; + } + if (iommu->granule > 0) { /* QEMU supports only 4KiB, 8KiB, 16KiB and 64KiB granule size */ if (!(iommu->granule == 4 || diff --git a/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml b/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml index e53ad1d461..a7398c39cf 100644 --- a/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml +++ b/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml @@ -191,6 +191,7 @@ <flag name='arm-smmuv3'/> <flag name='arm-smmuv3.smmu_per_bus'/> <flag name='arm-smmuv3.accel'/> + <flag name='arm-smmuv3.cmdqv'/> <version>11000090</version> <microcodeVersion>61700287</microcodeVersion> <package>v11.1.0-rc0</package> -- 2.43.0
On Tue, Aug 11, 2026 at 11:50:44AM -0700, Nathan Chen via Devel wrote:
From: Nathan Chen <nathanc@nvidia.com>
Probe the arm-smmuv3 cmdqv device property via device-list-properties, gated on QEMU_CAPS_DEVICE_ARM_SMMUV3. Reject domain configs that set cmdqv when the QEMU binary lacks the property.
Signed-off-by: Nathan Chen <nathanc@nvidia.com> --- src/qemu/qemu_capabilities.c | 4 ++++ src/qemu/qemu_capabilities.h | 3 +++ src/qemu/qemu_validate.c | 9 +++++++++ tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml | 1 + 4 files changed, 17 insertions(+)
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c index 6abb179951..a0fe9b36a6 100644 --- a/src/qemu/qemu_capabilities.c +++ b/src/qemu/qemu_capabilities.c @@ -771,6 +771,9 @@ VIR_ENUM_IMPL(virQEMUCaps, "arm-smmuv3", /* QEMU_CAPS_DEVICE_ARM_SMMUV3 */ "arm-smmuv3.smmu_per_bus", /* QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS */ "arm-smmuv3.accel", /* QEMU_CAPS_ARM_SMMUV3_ACCEL */ + + /* 500 */ + "arm-smmuv3.cmdqv", /* QEMU_CAPS_ARM_SMMUV3_CMDQV */ );
@@ -1651,6 +1654,7 @@ static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsAMDIOMMU[] = { static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsArmSmmuv3[] = { { "smmu_per_bus", QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, NULL }, { "accel", QEMU_CAPS_ARM_SMMUV3_ACCEL, NULL }, + { "cmdqv", QEMU_CAPS_ARM_SMMUV3_CMDQV, NULL }, };
/* see documentation for virQEMUQAPISchemaPathGet for the query format */ diff --git a/src/qemu/qemu_capabilities.h b/src/qemu/qemu_capabilities.h index 4563e15156..91c4852ea7 100644 --- a/src/qemu/qemu_capabilities.h +++ b/src/qemu/qemu_capabilities.h @@ -746,6 +746,9 @@ typedef enum { /* virQEMUCapsFlags grouping marker for syntax-check */ QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, /* arm-smmuv3.smmu_per_bus */ QEMU_CAPS_ARM_SMMUV3_ACCEL, /* arm-smmuv3.accel */
+ /* 500 */ + QEMU_CAPS_ARM_SMMUV3_CMDQV, /* arm-smmuv3.cmdqv */ + QEMU_CAPS_LAST /* this must always be the last item */ } virQEMUCapsFlags;
diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index 61f3bd3278..25527ca2cc 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5829,6 +5829,15 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMMUDef *iommu, return -1; }
+ /* cmdqv was added after accel; do not treat ACCEL as a proxy for it. */ + if (iommu->model == VIR_DOMAIN_IOMMU_MODEL_SMMUV3 && + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT && + !virQEMUCapsGet(qemuCaps, QEMU_CAPS_ARM_SMMUV3_CMDQV)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("iommu: cmdqv is not supported with this QEMU binary")); + return -1; + } + if (iommu->granule > 0) { /* QEMU supports only 4KiB, 8KiB, 16KiB and 64KiB granule size */ if (!(iommu->granule == 4 ||
This check needs to be moved to PATCH 02, otherwise compilation of this patch fails because iommu->cmdqv is not defined.
diff --git a/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml b/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml index e53ad1d461..a7398c39cf 100644 --- a/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml +++ b/tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml @@ -191,6 +191,7 @@ <flag name='arm-smmuv3'/> <flag name='arm-smmuv3.smmu_per_bus'/> <flag name='arm-smmuv3.accel'/> + <flag name='arm-smmuv3.cmdqv'/> <version>11000090</version> <microcodeVersion>61700287</microcodeVersion> <package>v11.1.0-rc0</package> -- 2.43.0
Hi Pavel, On 8/18/2026 1:42 AM, Pavel Hrdina wrote:
From: Nathan Chen<nathanc@nvidia.com>
Probe the arm-smmuv3 cmdqv device property via device-list-properties, gated on QEMU_CAPS_DEVICE_ARM_SMMUV3. Reject domain configs that set cmdqv when the QEMU binary lacks the property.
Signed-off-by: Nathan Chen<nathanc@nvidia.com> --- src/qemu/qemu_capabilities.c | 4 ++++ src/qemu/qemu_capabilities.h | 3 +++ src/qemu/qemu_validate.c | 9 +++++++++ tests/qemucapabilitiesdata/caps_11.1.0_aarch64.xml | 1 + 4 files changed, 17 insertions(+)
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c index 6abb179951..a0fe9b36a6 100644 --- a/src/qemu/qemu_capabilities.c +++ b/src/qemu/qemu_capabilities.c @@ -771,6 +771,9 @@ VIR_ENUM_IMPL(virQEMUCaps, "arm-smmuv3", /* QEMU_CAPS_DEVICE_ARM_SMMUV3 */ "arm-smmuv3.smmu_per_bus", /* QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS */ "arm-smmuv3.accel", /* QEMU_CAPS_ARM_SMMUV3_ACCEL */ + + /* 500 */ + "arm-smmuv3.cmdqv", /* QEMU_CAPS_ARM_SMMUV3_CMDQV */ );
@@ -1651,6 +1654,7 @@ static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsAMDIOMMU[] = { static struct virQEMUCapsDevicePropsFlags virQEMUCapsDevicePropsArmSmmuv3[] = { { "smmu_per_bus", QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, NULL }, { "accel", QEMU_CAPS_ARM_SMMUV3_ACCEL, NULL }, + { "cmdqv", QEMU_CAPS_ARM_SMMUV3_CMDQV, NULL }, };
/* see documentation for virQEMUQAPISchemaPathGet for the query format */ diff --git a/src/qemu/qemu_capabilities.h b/src/qemu/qemu_capabilities.h index 4563e15156..91c4852ea7 100644 --- a/src/qemu/qemu_capabilities.h +++ b/src/qemu/qemu_capabilities.h @@ -746,6 +746,9 @@ typedef enum { /* virQEMUCapsFlags grouping marker for syntax-check */ QEMU_CAPS_ARM_SMMUV3_SMMU_PER_BUS, /* arm-smmuv3.smmu_per_bus */ QEMU_CAPS_ARM_SMMUV3_ACCEL, /* arm-smmuv3.accel */
+ /* 500 */ + QEMU_CAPS_ARM_SMMUV3_CMDQV, /* arm-smmuv3.cmdqv */ + QEMU_CAPS_LAST /* this must always be the last item */ } virQEMUCapsFlags;
diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index 61f3bd3278..25527ca2cc 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5829,6 +5829,15 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMMUDef *iommu, return -1; }
+ /* cmdqv was added after accel; do not treat ACCEL as a proxy for it. */ + if (iommu->model == VIR_DOMAIN_IOMMU_MODEL_SMMUV3 && + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT && + !virQEMUCapsGet(qemuCaps, QEMU_CAPS_ARM_SMMUV3_CMDQV)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("iommu: cmdqv is not supported with this QEMU binary")); + return -1; + } + if (iommu->granule > 0) { /* QEMU supports only 4KiB, 8KiB, 16KiB and 64KiB granule size */ if (!(iommu->granule == 4 || This check needs to be moved to PATCH 02, otherwise compilation of this
On Tue, Aug 11, 2026 at 11:50:44AM -0700, Nathan Chen via Devel wrote: patch fails because iommu->cmdqv is not defined. Got it, I will make this fix.
Thanks, Nathan
From: Nathan Chen <nathanc@nvidia.com> Introduce support for "cmdqv" IOMMU attribute, which enables NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3. It supports passthroughs of physical SMMU-CMDQ linked command queue from host space to a VM. Signed-off-by: Nathan Chen <nathanc@nvidia.com> --- docs/formatdomain.rst | 6 ++++++ src/conf/domain_conf.c | 15 +++++++++++++++ src/conf/domain_conf.h | 1 + src/conf/domain_validate.c | 6 +++++- src/conf/schemas/domaincommon.rng | 5 +++++ src/qemu/qemu_command.c | 1 + src/qemu/qemu_validate.c | 1 - 7 files changed, 33 insertions(+), 2 deletions(-) diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index 0b346a0952..2d5a34cb35 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -9436,6 +9436,12 @@ Examples: devices. :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only) + ``cmdqv`` + The ``cmdqv`` attribute with possible values ``on`` and ``off`` can be used + to enable NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3 that supports + passthrough of physical SMMU-CMDQ linked command queue from host space to VM. + :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only) + ``ats`` The ``ats`` attribute with possible values ``on`` and ``off`` can be used to enable reporting Address Translation Services capability to diff --git a/src/conf/domain_conf.c b/src/conf/domain_conf.c index 9880339e42..42a0faca88 100644 --- a/src/conf/domain_conf.c +++ b/src/conf/domain_conf.c @@ -14758,6 +14758,10 @@ virDomainIOMMUDefParseXML(virDomainXMLOption *xmlopt, &iommu->accel) < 0) return NULL; + if (virXMLPropTristateSwitch(driver, "cmdqv", VIR_XML_PROP_NONE, + &iommu->cmdqv) < 0) + return NULL; + if (virXMLPropTristateSwitch(driver, "ats", VIR_XML_PROP_NONE, &iommu->ats) < 0) return NULL; @@ -16879,6 +16883,7 @@ virDomainIOMMUDefEquals(const virDomainIOMMUDef *a, a->dma_translation != b->dma_translation || a->pci_bus != b->pci_bus || a->accel != b->accel || + a->cmdqv != b->cmdqv || a->ats != b->ats || a->ril != b->ril || a->ssid_size != b->ssid_size || @@ -22773,6 +22778,12 @@ virDomainIOMMUDefCheckABIStability(virDomainIOMMUDef *src, dst->accel, src->accel); return false; } + if (src->cmdqv != dst->cmdqv) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device cmdqv value '%1$d' does not match source '%2$d'"), + dst->cmdqv, src->cmdqv); + return false; + } if (src->ats != dst->ats) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, _("Target domain IOMMU device ATS value '%1$d' does not match source '%2$d'"), @@ -29271,6 +29282,10 @@ virDomainIOMMUDefFormat(virBuffer *buf, virBufferAsprintf(&driverAttrBuf, " accel='%s'", virTristateSwitchTypeToString(iommu->accel)); } + if (iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT) { + virBufferAsprintf(&driverAttrBuf, " cmdqv='%s'", + virTristateSwitchTypeToString(iommu->cmdqv)); + } if (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT) { virBufferAsprintf(&driverAttrBuf, " ats='%s'", virTristateSwitchTypeToString(iommu->ats)); diff --git a/src/conf/domain_conf.h b/src/conf/domain_conf.h index 2c017738e3..0c79bea015 100644 --- a/src/conf/domain_conf.h +++ b/src/conf/domain_conf.h @@ -3106,6 +3106,7 @@ struct _virDomainIOMMUDef { virTristateSwitch pt; int granule; /* -1 means 'host', 0 unset, page size in KiB otherwise */ virTristateSwitch accel; + virTristateSwitch cmdqv; virTristateSwitch ats; virTristateSwitch ril; int ssid_size; diff --git a/src/conf/domain_validate.c b/src/conf/domain_validate.c index 710a891904..59b6c5f6d7 100644 --- a/src/conf/domain_validate.c +++ b/src/conf/domain_validate.c @@ -3207,7 +3207,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || - iommu->oas >= 0)) { + iommu->oas >= 0 || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT)) { virReportError(VIR_ERR_XML_ERROR, _("accel must be enabled for iommu model '%1$s' when setting ats, ril, ssidsize, or oas"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3222,6 +3223,7 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) iommu->dma_translation != VIR_TRISTATE_SWITCH_ABSENT || iommu->pci_bus >= 0 || iommu->accel != VIR_TRISTATE_SWITCH_ABSENT || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT || iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || @@ -3249,6 +3251,7 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) iommu->dma_translation != VIR_TRISTATE_SWITCH_ABSENT || iommu->pci_bus >= 0 || iommu->accel != VIR_TRISTATE_SWITCH_ABSENT || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT || iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || @@ -3266,6 +3269,7 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) iommu->xtsup != VIR_TRISTATE_SWITCH_ABSENT || iommu->pci_bus >= 0 || iommu->accel != VIR_TRISTATE_SWITCH_ABSENT || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT || iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || diff --git a/src/conf/schemas/domaincommon.rng b/src/conf/schemas/domaincommon.rng index c8f1fe5547..cb773ad319 100644 --- a/src/conf/schemas/domaincommon.rng +++ b/src/conf/schemas/domaincommon.rng @@ -6481,6 +6481,11 @@ <data type="int"/> </attribute> </optional> + <optional> + <attribute name="cmdqv"> + <ref name="virOnOff"/> + </attribute> + </optional> </element> </optional> <optional> diff --git a/src/qemu/qemu_command.c b/src/qemu/qemu_command.c index 980f0495b1..87427b86da 100644 --- a/src/qemu/qemu_command.c +++ b/src/qemu/qemu_command.c @@ -6311,6 +6311,7 @@ qemuBuildPCINestedSmmuv3DevProps(const virDomainDef *def, "S:ril", qemuOnOffAuto(iommu->ril), "S:ssidsize", ssidsizeStr, "S:oas", oasStr, + "S:cmdqv", qemuOnOffAuto(iommu->cmdqv), NULL) < 0) return NULL; diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index 25527ca2cc..0e860a286c 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5829,7 +5829,6 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMMUDef *iommu, return -1; } - /* cmdqv was added after accel; do not treat ACCEL as a proxy for it. */ if (iommu->model == VIR_DOMAIN_IOMMU_MODEL_SMMUV3 && iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT && !virQEMUCapsGet(qemuCaps, QEMU_CAPS_ARM_SMMUV3_CMDQV)) { -- 2.43.0
On Tue, Aug 11, 2026 at 11:50:45AM -0700, Nathan Chen via Devel wrote:
From: Nathan Chen <nathanc@nvidia.com>
Introduce support for "cmdqv" IOMMU attribute, which enables NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3. It supports passthroughs of physical SMMU-CMDQ linked command queue from host space to a VM.
Signed-off-by: Nathan Chen <nathanc@nvidia.com> --- docs/formatdomain.rst | 6 ++++++ src/conf/domain_conf.c | 15 +++++++++++++++ src/conf/domain_conf.h | 1 + src/conf/domain_validate.c | 6 +++++- src/conf/schemas/domaincommon.rng | 5 +++++ src/qemu/qemu_command.c | 1 + src/qemu/qemu_validate.c | 1 - 7 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index 0b346a0952..2d5a34cb35 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -9436,6 +9436,12 @@ Examples: devices. :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only)
+ ``cmdqv`` + The ``cmdqv`` attribute with possible values ``on`` and ``off`` can be used + to enable NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3 that supports + passthrough of physical SMMU-CMDQ linked command queue from host space to VM. + :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only) +
It should mention the default value if accel is enabled like the other attributes.
``ats`` The ``ats`` attribute with possible values ``on`` and ``off`` can be used to enable reporting Address Translation Services capability to diff --git a/src/conf/domain_conf.c b/src/conf/domain_conf.c index 9880339e42..42a0faca88 100644 --- a/src/conf/domain_conf.c +++ b/src/conf/domain_conf.c @@ -14758,6 +14758,10 @@ virDomainIOMMUDefParseXML(virDomainXMLOption *xmlopt, &iommu->accel) < 0) return NULL;
+ if (virXMLPropTristateSwitch(driver, "cmdqv", VIR_XML_PROP_NONE, + &iommu->cmdqv) < 0) + return NULL; + if (virXMLPropTristateSwitch(driver, "ats", VIR_XML_PROP_NONE, &iommu->ats) < 0) return NULL; @@ -16879,6 +16883,7 @@ virDomainIOMMUDefEquals(const virDomainIOMMUDef *a, a->dma_translation != b->dma_translation || a->pci_bus != b->pci_bus || a->accel != b->accel || + a->cmdqv != b->cmdqv || a->ats != b->ats || a->ril != b->ril || a->ssid_size != b->ssid_size || @@ -22773,6 +22778,12 @@ virDomainIOMMUDefCheckABIStability(virDomainIOMMUDef *src, dst->accel, src->accel); return false; } + if (src->cmdqv != dst->cmdqv) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device cmdqv value '%1$d' does not match source '%2$d'"), + dst->cmdqv, src->cmdqv); + return false; + } if (src->ats != dst->ats) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, _("Target domain IOMMU device ATS value '%1$d' does not match source '%2$d'"), @@ -29271,6 +29282,10 @@ virDomainIOMMUDefFormat(virBuffer *buf, virBufferAsprintf(&driverAttrBuf, " accel='%s'", virTristateSwitchTypeToString(iommu->accel)); } + if (iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT) { + virBufferAsprintf(&driverAttrBuf, " cmdqv='%s'", + virTristateSwitchTypeToString(iommu->cmdqv)); + } if (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT) { virBufferAsprintf(&driverAttrBuf, " ats='%s'", virTristateSwitchTypeToString(iommu->ats)); diff --git a/src/conf/domain_conf.h b/src/conf/domain_conf.h index 2c017738e3..0c79bea015 100644 --- a/src/conf/domain_conf.h +++ b/src/conf/domain_conf.h @@ -3106,6 +3106,7 @@ struct _virDomainIOMMUDef { virTristateSwitch pt; int granule; /* -1 means 'host', 0 unset, page size in KiB otherwise */ virTristateSwitch accel; + virTristateSwitch cmdqv; virTristateSwitch ats; virTristateSwitch ril; int ssid_size; diff --git a/src/conf/domain_validate.c b/src/conf/domain_validate.c index 710a891904..59b6c5f6d7 100644 --- a/src/conf/domain_validate.c +++ b/src/conf/domain_validate.c @@ -3207,7 +3207,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || - iommu->oas >= 0)) { + iommu->oas >= 0 || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT)) {
For consistency with the other conditions I would move the check between accel and ats. Otherwise looks good. Pavel
Hi Pavel, On 8/18/2026 1:50 AM, Pavel Hrdina wrote:
On Tue, Aug 11, 2026 at 11:50:45AM -0700, Nathan Chen via Devel wrote:
From: Nathan Chen<nathanc@nvidia.com>
Introduce support for "cmdqv" IOMMU attribute, which enables NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3. It supports passthroughs of physical SMMU-CMDQ linked command queue from host space to a VM.
Signed-off-by: Nathan Chen<nathanc@nvidia.com> --- docs/formatdomain.rst | 6 ++++++ src/conf/domain_conf.c | 15 +++++++++++++++ src/conf/domain_conf.h | 1 + src/conf/domain_validate.c | 6 +++++- src/conf/schemas/domaincommon.rng | 5 +++++ src/qemu/qemu_command.c | 1 + src/qemu/qemu_validate.c | 1 - 7 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index 0b346a0952..2d5a34cb35 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -9436,6 +9436,12 @@ Examples: devices. :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only)
+ ``cmdqv`` + The ``cmdqv`` attribute with possible values ``on`` and ``off`` can be used + to enable NVIDIA Tegra241 CMDQV, an extension for ARM SMMUv3 that supports + passthrough of physical SMMU-CMDQ linked command queue from host space to VM. + :since:`Since 12.7.0` (QEMU/KVM and ``smmuv3`` model only) + It should mention the default value if accel is enabled like the other attributes.
Right, I will include that line to match the other attributes.>> ``ats``
The ``ats`` attribute with possible values ``on`` and ``off`` can be used to enable reporting Address Translation Services capability to diff --git a/src/conf/domain_conf.c b/src/conf/domain_conf.c index 9880339e42..42a0faca88 100644 --- a/src/conf/domain_conf.c +++ b/src/conf/domain_conf.c @@ -14758,6 +14758,10 @@ virDomainIOMMUDefParseXML(virDomainXMLOption *xmlopt, &iommu->accel) < 0) return NULL;
+ if (virXMLPropTristateSwitch(driver, "cmdqv", VIR_XML_PROP_NONE, + &iommu->cmdqv) < 0) + return NULL; + if (virXMLPropTristateSwitch(driver, "ats", VIR_XML_PROP_NONE, &iommu->ats) < 0) return NULL; @@ -16879,6 +16883,7 @@ virDomainIOMMUDefEquals(const virDomainIOMMUDef *a, a->dma_translation != b->dma_translation || a->pci_bus != b->pci_bus || a->accel != b->accel || + a->cmdqv != b->cmdqv || a->ats != b->ats || a->ril != b->ril || a->ssid_size != b->ssid_size || @@ -22773,6 +22778,12 @@ virDomainIOMMUDefCheckABIStability(virDomainIOMMUDef *src, dst->accel, src->accel); return false; } + if (src->cmdqv != dst->cmdqv) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device cmdqv value '%1$d' does not match source '%2$d'"), + dst->cmdqv, src->cmdqv); + return false; + } if (src->ats != dst->ats) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, _("Target domain IOMMU device ATS value '%1$d' does not match source '%2$d'"), @@ -29271,6 +29282,10 @@ virDomainIOMMUDefFormat(virBuffer *buf, virBufferAsprintf(&driverAttrBuf, " accel='%s'", virTristateSwitchTypeToString(iommu->accel)); } + if (iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT) { + virBufferAsprintf(&driverAttrBuf, " cmdqv='%s'", + virTristateSwitchTypeToString(iommu->cmdqv)); + } if (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT) { virBufferAsprintf(&driverAttrBuf, " ats='%s'", virTristateSwitchTypeToString(iommu->ats)); diff --git a/src/conf/domain_conf.h b/src/conf/domain_conf.h index 2c017738e3..0c79bea015 100644 --- a/src/conf/domain_conf.h +++ b/src/conf/domain_conf.h @@ -3106,6 +3106,7 @@ struct _virDomainIOMMUDef { virTristateSwitch pt; int granule; /* -1 means 'host', 0 unset, page size in KiB otherwise */ virTristateSwitch accel; + virTristateSwitch cmdqv; virTristateSwitch ats; virTristateSwitch ril; int ssid_size; diff --git a/src/conf/domain_validate.c b/src/conf/domain_validate.c index 710a891904..59b6c5f6d7 100644 --- a/src/conf/domain_validate.c +++ b/src/conf/domain_validate.c @@ -3207,7 +3207,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *iommu) (iommu->ats != VIR_TRISTATE_SWITCH_ABSENT || iommu->ril != VIR_TRISTATE_SWITCH_ABSENT || iommu->ssid_size >= 0 || - iommu->oas >= 0)) { + iommu->oas >= 0 || + iommu->cmdqv != VIR_TRISTATE_SWITCH_ABSENT)) {
For consistency with the other conditions I would move the check between accel and ats.
Otherwise looks good. I will move this up in the next refresh.
Thanks, Nathan
From: Nathan Chen <nathanc@nvidia.com> Provide sample XML and CLI args for the cmdqv XML schema Signed-off-by: Nathan Chen <nathanc@nvidia.com> --- ...v3-pci-bus-accel-cmdqv.aarch64-latest.args | 40 +++++++++++++ ...uv3-pci-bus-accel-cmdqv.aarch64-latest.xml | 59 +++++++++++++++++++ .../iommu-smmuv3-pci-bus-accel-cmdqv.xml | 49 +++++++++++++++ tests/qemuxmlconftest.c | 1 + 4 files changed, 149 insertions(+) create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.args create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.xml create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.xml diff --git a/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.args b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.args new file mode 100644 index 0000000000..0ced2f41a8 --- /dev/null +++ b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.args @@ -0,0 +1,40 @@ +LC_ALL=C \ +PATH=/bin \ +HOME=/var/lib/libvirt/qemu/domain--1-guest \ +USER=test \ +LOGNAME=test \ +XDG_DATA_HOME=/var/lib/libvirt/qemu/domain--1-guest/.local/share \ +XDG_CACHE_HOME=/var/lib/libvirt/qemu/domain--1-guest/.cache \ +XDG_CONFIG_HOME=/var/lib/libvirt/qemu/domain--1-guest/.config \ +/usr/bin/qemu-system-aarch64 \ +-name guest=guest,debug-threads=on \ +-S \ +-object '{"qom-type":"secret","id":"masterKey0","format":"raw","file":"/var/lib/libvirt/qemu/domain--1-guest/master-key.aes"}' \ +-machine virt,usb=off,gic-version=2,dump-guest-core=off,memory-backend=mach-virt.ram,acpi=off \ +-accel tcg \ +-m size=1048576k \ +-object '{"qom-type":"memory-backend-ram","id":"mach-virt.ram","size":1073741824}' \ +-overcommit mem-lock=off \ +-smp 1,sockets=1,cores=1,threads=1 \ +-uuid 1ccfd97d-5eb4-478a-bbe6-88d254c16db7 \ +-display none \ +-no-user-config \ +-nodefaults \ +-chardev socket,id=charmonitor,fd=@mon-fd@,server=on,wait=off \ +-object '{"qom-type":"monitor-qmp","id":"monitor","chardev":"charmonitor"}' \ +-rtc base=utc \ +-no-shutdown \ +-boot strict=on \ +-device '{"driver":"pxb-pcie","bus_nr":252,"id":"pci.1","bus":"pcie.0","addr":"0x1"}' \ +-device '{"driver":"pxb-pcie","bus_nr":248,"id":"pci.2","bus":"pcie.0","addr":"0x2"}' \ +-device '{"driver":"pcie-root-port","port":0,"chassis":21,"id":"pci.3","bus":"pci.1","addr":"0x0"}' \ +-device '{"driver":"pcie-root-port","port":168,"chassis":22,"id":"pci.4","bus":"pci.2","addr":"0x0"}' \ +-device '{"driver":"arm-smmuv3","primary-bus":"pci.1","id":"iommu0","accel":true,"ats":"on","ril":"on","ssidsize":"20","oas":"44","cmdqv":"on"}' \ +-device '{"driver":"arm-smmuv3","primary-bus":"pci.2","id":"iommu1","accel":true,"ats":"on","ril":"on","ssidsize":"20","oas":"44","cmdqv":"on"}' \ +-audiodev '{"id":"audio1","driver":"none"}' \ +-object '{"qom-type":"rng-random","id":"objrng0","filename":"/dev/urandom"}' \ +-device '{"driver":"virtio-rng-pci","rng":"objrng0","id":"rng0","bus":"pci.3","addr":"0x0"}' \ +-object '{"qom-type":"rng-random","id":"objrng1","filename":"/dev/urandom"}' \ +-device '{"driver":"virtio-rng-pci","rng":"objrng1","id":"rng1","bus":"pci.4","addr":"0x0"}' \ +-sandbox on,obsolete=deny,elevateprivileges=deny,spawn=deny,resourcecontrol=deny \ +-msg timestamp=on diff --git a/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.xml b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.xml new file mode 100644 index 0000000000..445fb44ee8 --- /dev/null +++ b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.aarch64-latest.xml @@ -0,0 +1,59 @@ +<domain type='qemu'> + <name>guest</name> + <uuid>1ccfd97d-5eb4-478a-bbe6-88d254c16db7</uuid> + <memory unit='KiB'>1048576</memory> + <currentMemory unit='KiB'>1048576</currentMemory> + <vcpu placement='static'>1</vcpu> + <os> + <type arch='aarch64' machine='virt'>hvm</type> + <boot dev='hd'/> + </os> + <features> + <gic version='2'/> + </features> + <clock offset='utc'/> + <on_poweroff>destroy</on_poweroff> + <on_reboot>restart</on_reboot> + <on_crash>destroy</on_crash> + <devices> + <emulator>/usr/bin/qemu-system-aarch64</emulator> + <controller type='usb' index='0' model='none'/> + <controller type='pci' index='0' model='pcie-root'/> + <controller type='pci' index='1' model='pcie-expander-bus'> + <model name='pxb-pcie'/> + <target busNr='252'/> + <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/> + </controller> + <controller type='pci' index='2' model='pcie-expander-bus'> + <model name='pxb-pcie'/> + <target busNr='248'/> + <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/> + </controller> + <controller type='pci' index='3' model='pcie-root-port'> + <model name='pcie-root-port'/> + <target chassis='21' port='0x0'/> + <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> + </controller> + <controller type='pci' index='4' model='pcie-root-port'> + <model name='pcie-root-port'/> + <target chassis='22' port='0xa8'/> + <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/> + </controller> + <audio id='1' type='none'/> + <memballoon model='none'/> + <rng model='virtio'> + <backend model='random'>/dev/urandom</backend> + <address type='pci' domain='0x0000' bus='0x03' slot='0x00' function='0x0'/> + </rng> + <rng model='virtio'> + <backend model='random'>/dev/urandom</backend> + <address type='pci' domain='0x0000' bus='0x04' slot='0x00' function='0x0'/> + </rng> + <iommu model='smmuv3'> + <driver pciBus='1' accel='on' cmdqv='on' ats='on' ril='on' ssidsize='20' oas='44'/> + </iommu> + <iommu model='smmuv3'> + <driver pciBus='2' accel='on' cmdqv='on' ats='on' ril='on' ssidsize='20' oas='44'/> + </iommu> + </devices> +</domain> diff --git a/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.xml b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.xml new file mode 100644 index 0000000000..6d91755b93 --- /dev/null +++ b/tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel-cmdqv.xml @@ -0,0 +1,49 @@ +<domain type='qemu'> + <name>guest</name> + <uuid>1ccfd97d-5eb4-478a-bbe6-88d254c16db7</uuid> + <memory unit='KiB'>1048576</memory> + <vcpu placement='static'>1</vcpu> + <os> + <type arch='aarch64' machine='virt'>hvm</type> + </os> + <devices> + <emulator>/usr/bin/qemu-system-aarch64</emulator> + <controller type='usb' model='none'/> + <memballoon model='none'/> + <controller type='pci' index='0' model='pcie-root'/> + <controller type='pci' index='1' model='pcie-expander-bus'> + <model name='pxb-pcie'/> + <target busNr='252'/> + <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/> + </controller> + <controller type='pci' index='2' model='pcie-expander-bus'> + <model name='pxb-pcie'/> + <target busNr='248'/> + <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/> + </controller> + <controller type='pci' index='3' model='pcie-root-port'> + <model name='pcie-root-port'/> + <target chassis='21' port='0x0'/> + <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/> + </controller> + <controller type='pci' index='4' model='pcie-root-port'> + <model name='pcie-root-port'/> + <target chassis='22' port='0xa8'/> + <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/> + </controller> + <rng model='virtio'> + <backend model='random'>/dev/urandom</backend> + <address type='pci' domain='0x0000' bus='0x03' slot='0x00' function='0x0'/> + </rng> + <rng model='virtio'> + <backend model='random'>/dev/urandom</backend> + <address type='pci' domain='0x0000' bus='0x04' slot='0x00' function='0x0'/> + </rng> + <iommu model='smmuv3'> + <driver pciBus='1' accel='on' cmdqv='on' ats='on' ril='on' ssidsize='20' oas='44'/> + </iommu> + <iommu model='smmuv3'> + <driver pciBus='2' accel='on' cmdqv='on' ats='on' ril='on' ssidsize='20' oas='44'/> + </iommu> + </devices> +</domain> diff --git a/tests/qemuxmlconftest.c b/tests/qemuxmlconftest.c index e0e64c6c38..6ea54dd115 100644 --- a/tests/qemuxmlconftest.c +++ b/tests/qemuxmlconftest.c @@ -2994,6 +2994,7 @@ mymain(void) DO_TEST_CAPS_ARCH_LATEST("iommu-smmuv3-pci-bus-single", "aarch64"); DO_TEST_CAPS_ARCH_LATEST("iommu-smmuv3-pci-bus-accel", "aarch64"); DO_TEST_CAPS_ARCH_LATEST("iommu-smmuv3-pci-bus-accel-auto", "aarch64"); + DO_TEST_CAPS_ARCH_LATEST("iommu-smmuv3-pci-bus-accel-cmdqv", "aarch64"); DO_TEST_CAPS_LATEST("virtio-iommu-x86_64"); DO_TEST_CAPS_ARCH_LATEST("virtio-iommu-aarch64", "aarch64"); DO_TEST_CAPS_LATEST_PARSE_ERROR("virtio-iommu-wrong-machine"); -- 2.43.0
It takes more than just fast reflexes to dominate the slopes in Snow Rider 3D; a thorough grasp of the game's fundamental principles and sled physics is necessary. https://snowrider-2.io
participants (3)
-
cooingtrapped＠atomicmail.io -
Nathan Chen -
Pavel Hrdina