9:28 p.m.
CPU signatures in the cpu_map serve as a hint for CPUID to CPU model
matching algorithm. If the CPU signatures matches any CPU model in the
cpu_map, this model will be the preferred one.
This works out well and solved several mismatches, but in real world
CPUs which should match a single CPU model may be produced with several
different signatures. For example, low voltage Broadwell CPUs for
laptops and Broadwell CPUs for servers differ in CPU model numbers while
we should detect them all as Broadwell CPU model.
This patch adds support for storing several signatures for a single CPU
model to make this hint useful for more CPUs. Later commits will provide
additional signatures for existing CPU models, which will correct some
results in our CPU test suite.
The list of signatures corresponding to each CPU model were generated by
consulting the following sites:
https://en.wikichip.org/wiki/intel/cpuid
http://www.cpu-world.com/cgi-bin/CPUID.pl
https://ark.intel.com/content/www/us/en/ark.html
Jiri Denemark (26):
cputest: Make sure generated files pass syntax-check
cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4
cputest: Add data for Intel(R) Core(TM) i7-7600U
cputest: Add data for Intel(R) Xeon(R) CPU E7540
cputest: Add data for Intel(R) Xeon(R) CPU E5-2650
cpu_x86: Separate ancestor model parsing from x86ModelParse
cpu_x86: Separate signature parsing from x86ModelParse
cpu_x86: Separate vendor parsing from x86ModelParse
cpu_x86: Separate feature list parsing from x86ModelParse
cpu_x86: Make sure CPU model names are unique in cpu_map
cpu_x86: Allow multiple signatures for a CPU model
qemu_capabilities: Inroduce virQEMUCapsGetCPUModelX86Data
qemu_capabilities: Introduce virQEMUCapsGetCPUModelInfo
qemu_capabilities: Use virQEMUCapsGetCPUModelInfo
cpu_x86: Add virCPUx86DataGetSignature for tests
cpu_map: Add hex representation of signatures
cputest: Test CPU signatures
cpu_map: Add more signatures for Conroe CPU model
cpu_map: Add more signatures for Penryn CPU model
cpu_map: Add more signatures for Nehalem CPU models
cpu_map: Add more signatures for Westmere CPU model
cpu_map: Add more signatures for SandyBridge CPU models
cpu_map: Add more signatures for IvyBridge CPU models
cpu_map: Add more signatures for Haswell CPU models
cpu_map: Add more signatures for Broadwell CPU models
cpu_map: Add more signatures for Skylake-Client CPU models
src/cpu/cpu_x86.c | 345 +++--
src/cpu/cpu_x86.h | 5 +
src/cpu_map/x86_Broadwell-IBRS.xml | 5 +-
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 5 +-
src/cpu_map/x86_Broadwell-noTSX.xml | 5 +-
src/cpu_map/x86_Broadwell.xml | 5 +-
src/cpu_map/x86_Conroe.xml | 3 +-
src/cpu_map/x86_EPYC-IBRS.xml | 2 +-
src/cpu_map/x86_EPYC.xml | 2 +-
src/cpu_map/x86_Haswell-IBRS.xml | 5 +-
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 5 +-
src/cpu_map/x86_Haswell-noTSX.xml | 5 +-
src/cpu_map/x86_Haswell.xml | 5 +-
src/cpu_map/x86_Icelake-Client.xml | 2 +-
src/cpu_map/x86_Icelake-Server.xml | 2 +-
src/cpu_map/x86_IvyBridge-IBRS.xml | 3 +-
src/cpu_map/x86_IvyBridge.xml | 3 +-
src/cpu_map/x86_Nehalem-IBRS.xml | 5 +-
src/cpu_map/x86_Nehalem.xml | 5 +-
src/cpu_map/x86_Opteron_G1.xml | 2 +-
src/cpu_map/x86_Opteron_G2.xml | 2 +-
src/cpu_map/x86_Opteron_G3.xml | 2 +-
src/cpu_map/x86_Opteron_G4.xml | 2 +-
src/cpu_map/x86_Opteron_G5.xml | 2 +-
src/cpu_map/x86_Penryn.xml | 3 +-
src/cpu_map/x86_SandyBridge-IBRS.xml | 3 +-
src/cpu_map/x86_SandyBridge.xml | 3 +-
src/cpu_map/x86_Skylake-Client-IBRS.xml | 7 +-
src/cpu_map/x86_Skylake-Client.xml | 7 +-
src/cpu_map/x86_Skylake-Server-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Server.xml | 2 +-
src/cpu_map/x86_Westmere-IBRS.xml | 2 +-
src/cpu_map/x86_Westmere.xml | 4 +-
src/libvirt_private.syms | 1 +
src/qemu/qemu_capabilities.c | 91 +-
src/qemu/qemu_capspriv.h | 8 +
tests/cputest.c | 96 ++
tests/cputestdata/cpu-reformat.py | 2 +-
tests/cputestdata/x86_64-cpuid-A10-5800K.sig | 4 +
tests/cputestdata/x86_64-cpuid-Atom-D510.sig | 4 +
tests/cputestdata/x86_64-cpuid-Atom-N450.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i5-2500.sig | 4 +
.../x86_64-cpuid-Core-i5-2540M.sig | 4 +
.../x86_64-cpuid-Core-i5-4670T.sig | 4 +
.../x86_64-cpuid-Core-i5-650-json.xml | 9 +-
.../cputestdata/x86_64-cpuid-Core-i5-650.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i5-6600.sig | 4 +
.../x86_64-cpuid-Core-i7-2600-xsaveopt.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i7-2600.sig | 4 +
.../x86_64-cpuid-Core-i7-3520M.sig | 4 +
.../x86_64-cpuid-Core-i7-3740QM.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i7-3770.sig | 4 +
.../x86_64-cpuid-Core-i7-4510U.sig | 4 +
.../x86_64-cpuid-Core-i7-4600U.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U-arat.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U-ibrs.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U.sig | 4 +
.../x86_64-cpuid-Core-i7-7600U-disabled.xml | 6 +
.../x86_64-cpuid-Core-i7-7600U-enabled.xml | 8 +
.../x86_64-cpuid-Core-i7-7600U-guest.xml | 28 +
.../x86_64-cpuid-Core-i7-7600U-host.xml | 29 +
.../x86_64-cpuid-Core-i7-7600U-json.xml | 13 +
.../x86_64-cpuid-Core-i7-7600U.json | 755 +++++++++++
.../x86_64-cpuid-Core-i7-7600U.sig | 4 +
.../x86_64-cpuid-Core-i7-7600U.xml | 47 +
.../cputestdata/x86_64-cpuid-Core-i7-7700.sig | 4 +
.../cputestdata/x86_64-cpuid-Core2-E6850.sig | 4 +
.../cputestdata/x86_64-cpuid-Core2-Q9500.sig | 4 +
.../x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig | 4 +
.../x86_64-cpuid-EPYC-7601-32-Core.sig | 4 +
tests/cputestdata/x86_64-cpuid-FX-8150.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-1352.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-2350.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-6234.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-6282.sig | 4 +
.../x86_64-cpuid-Pentium-P6100-guest.xml | 10 +-
.../x86_64-cpuid-Pentium-P6100.sig | 4 +
tests/cputestdata/x86_64-cpuid-Phenom-B95.sig | 4 +
.../x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-5110.sig | 4 +
.../x86_64-cpuid-Xeon-E3-1245-v5.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2609-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2623-v4-guest.xml | 11 +-
.../x86_64-cpuid-Xeon-E5-2623-v4-json.xml | 11 +-
.../x86_64-cpuid-Xeon-E5-2623-v4.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2630-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml | 7 +
.../x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 34 +
.../x86_64-cpuid-Xeon-E5-2630-v4-host.xml | 35 +
.../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 14 +
.../x86_64-cpuid-Xeon-E5-2630-v4.json | 596 +++++++++
.../x86_64-cpuid-Xeon-E5-2630-v4.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2630-v4.xml | 43 +
.../x86_64-cpuid-Xeon-E5-2650-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E5-2650-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2650-guest.xml | 29 +
.../x86_64-cpuid-Xeon-E5-2650-host.xml | 30 +
.../x86_64-cpuid-Xeon-E5-2650-json.xml | 14 +
.../x86_64-cpuid-Xeon-E5-2650-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2650-v4-guest.xml | 11 +-
.../x86_64-cpuid-Xeon-E5-2650-v4-json.xml | 11 +-
.../x86_64-cpuid-Xeon-E5-2650-v4.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2650.json | 931 ++++++++++++++
.../cputestdata/x86_64-cpuid-Xeon-E5-2650.sig | 4 +
.../cputestdata/x86_64-cpuid-Xeon-E5-2650.xml | 34 +
.../x86_64-cpuid-Xeon-E7-4820-guest.xml | 8 +-
.../x86_64-cpuid-Xeon-E7-4820-json.xml | 8 +-
.../cputestdata/x86_64-cpuid-Xeon-E7-4820.sig | 4 +
.../x86_64-cpuid-Xeon-E7-4830-json.xml | 9 +-
.../cputestdata/x86_64-cpuid-Xeon-E7-4830.sig | 4 +
.../x86_64-cpuid-Xeon-E7-8890-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E7540-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E7540-enabled.xml | 7 +
.../x86_64-cpuid-Xeon-E7540-guest.xml | 25 +
.../x86_64-cpuid-Xeon-E7540-host.xml | 26 +
.../x86_64-cpuid-Xeon-E7540-json.xml | 14 +
.../cputestdata/x86_64-cpuid-Xeon-E7540.json | 1117 +++++++++++++++++
tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml | 30 +
.../x86_64-cpuid-Xeon-Gold-5115.sig | 4 +
.../x86_64-cpuid-Xeon-Gold-6148.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig | 4 +
124 files changed, 4634 insertions(+), 206 deletions(-)
create mode 100644 tests/cputestdata/x86_64-cpuid-A10-5800K.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-D510.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-N450.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-2500.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-2540M.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-4670T.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-650.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-6600.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-2600-xsaveopt.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-2600.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3520M.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3740QM.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3770.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-4510U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-4600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U-arat.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U-ibrs.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7700.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core2-E6850.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core2-Q9500.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-FX-8150.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-1352.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-2350.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-6234.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-6282.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Pentium-P6100.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Phenom-B95.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-5110.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E3-1245-v5.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-4820.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-4830.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-Gold-5115.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-Gold-6148.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
--
2.21.0
9:28 p.m.
New subject: [libvirt] [PATCH 01/26] cputest: Make sure generated files pass syntax-check
The tests/cputestdata/cpu-parse.sh would produce JSON files with QEMU
replies which wouldn't pass syntax-check. Let's fix this by not emitting
an extra new line after reformatting the JSON file.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputestdata/cpu-reformat.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/cputestdata/cpu-reformat.py b/tests/cputestdata/cpu-reformat.py
index 2c7bbde262..fcc6b8ab41 100755
--- a/tests/cputestdata/cpu-reformat.py
+++ b/tests/cputestdata/cpu-reformat.py
@@ -6,4 +6,4 @@ import json
dec = json.JSONDecoder()
data, pos = dec.raw_decode(sys.stdin.read())
json.dump(data, sys.stdout, indent=2, separators=(',', ': '))
-print("\n")
+print("")
--
2.21.0
10:03 p.m.
New subject: [libvirt] [PATCH 01/26] cputest: Make sure generated files pass syntax-check
On Wed, Feb 27, 2019 at 02:28:51PM +0100, Jiri Denemark wrote:
The tests/cputestdata/cpu-parse.sh would produce JSON files with QEMU
replies which wouldn't pass syntax-check. Let's fix this by not emitting
an extra new line after reformatting the JSON file.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputestdata/cpu-reformat.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 02/26] cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml | 7 +
.../x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 31 +
.../x86_64-cpuid-Xeon-E5-2630-v4-host.xml | 35 +
.../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 +
.../x86_64-cpuid-Xeon-E5-2630-v4.json | 596 ++++++++++++++++++
.../x86_64-cpuid-Xeon-E5-2630-v4.xml | 43 ++
8 files changed, 732 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
diff --git a/tests/cputest.c b/tests/cputest.c
index b75d864d8e..323b662bc3 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -1188,6 +1188,7 @@ mymain(void)
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2609-v3", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2623-v4", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v3", JSON_HOST);
+ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v4", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v3", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v4", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST);
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
new file mode 100644
index 0000000000..3ffb246167
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
@@ -0,0 +1,7 @@
+<!-- Features disabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x0804c1fc' edx='0xb0600000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x02001000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000f' ecx_in='0x01' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000006'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
new file mode 100644
index 0000000000..f2d4f2826d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
@@ -0,0 +1,8 @@
+<!-- Features enabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0xf7fa3203' edx='0x0f8bfbff'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x001c0fbb' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000001'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000121' edx='0x2c100800'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
new file mode 100644
index 0000000000..cd7e25b52a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
@@ -0,0 +1,31 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Skylake-Client</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='ds'/>
+ <feature policy='require' name='acpi'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='ht'/>
+ <feature policy='require' name='tm'/>
+ <feature policy='require' name='pbe'/>
+ <feature policy='require' name='dtes64'/>
+ <feature policy='require' name='monitor'/>
+ <feature policy='require' name='ds_cpl'/>
+ <feature policy='require' name='vmx'/>
+ <feature policy='require' name='smx'/>
+ <feature policy='require' name='est'/>
+ <feature policy='require' name='tm2'/>
+ <feature policy='require' name='xtpr'/>
+ <feature policy='require' name='pdcm'/>
+ <feature policy='require' name='dca'/>
+ <feature policy='require' name='osxsave'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='cmt'/>
+ <feature policy='require' name='intel-pt'/>
+ <feature policy='require' name='mbm_total'/>
+ <feature policy='require' name='mbm_local'/>
+ <feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='invtsc'/>
+ <feature policy='disable' name='mpx'/>
+ <feature policy='disable' name='xsavec'/>
+ <feature policy='disable' name='xgetbv1'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
new file mode 100644
index 0000000000..5dd8d749de
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
@@ -0,0 +1,35 @@
+<cpu>
+ <arch>x86_64</arch>
+ <model>Broadwell</model>
+ <vendor>Intel</vendor>
+ <feature name='vme'/>
+ <feature name='ds'/>
+ <feature name='acpi'/>
+ <feature name='ss'/>
+ <feature name='ht'/>
+ <feature name='tm'/>
+ <feature name='pbe'/>
+ <feature name='dtes64'/>
+ <feature name='monitor'/>
+ <feature name='ds_cpl'/>
+ <feature name='vmx'/>
+ <feature name='smx'/>
+ <feature name='est'/>
+ <feature name='tm2'/>
+ <feature name='xtpr'/>
+ <feature name='pdcm'/>
+ <feature name='dca'/>
+ <feature name='osxsave'/>
+ <feature name='f16c'/>
+ <feature name='rdrand'/>
+ <feature name='arat'/>
+ <feature name='tsc_adjust'/>
+ <feature name='cmt'/>
+ <feature name='intel-pt'/>
+ <feature name='xsaveopt'/>
+ <feature name='mbm_total'/>
+ <feature name='mbm_local'/>
+ <feature name='pdpe1gb'/>
+ <feature name='abm'/>
+ <feature name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
new file mode 100644
index 0000000000..5dfce947b2
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
@@ -0,0 +1,11 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Skylake-Client</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='pdpe1gb'/>
+ <feature policy='disable' name='mpx'/>
+ <feature policy='disable' name='xsavec'/>
+ <feature policy='disable' name='xgetbv1'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
new file mode 100644
index 0000000000..ee09950fce
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
@@ -0,0 +1,596 @@
+{
+ "return": {
+ "model": {
+ "name": "base",
+ "props": {
+ "phys-bits": 0,
+ "core-id": -1,
+ "xlevel": 2147483656,
+ "cmov": true,
+ "ia64": false,
+ "aes": true,
+ "mmx": true,
+ "arat": true,
+ "rdpid": false,
+ "pause-filter": false,
+ "xsavec": false,
+ "osxsave": false,
+ "tsc-frequency": 0,
+ "xd": true,
+ "hv-vendor-id": "",
+ "kvm-asyncpf": true,
+ "kvm_asyncpf": true,
+ "perfctr_core": false,
+ "perfctr-core": false,
+ "mpx": false,
+ "decodeassists": false,
+ "avx512cd": false,
+ "pbe": false,
+ "sse4_1": true,
+ "sse4.1": true,
+ "sse4-1": true,
+ "family": 6,
+ "vmware-cpuid-freq": true,
+ "avx512f": false,
+ "xcrypt": false,
+ "msr": true,
+ "mce": true,
+ "mca": true,
+ "thread-id": -1,
+ "min-level": 13,
+ "xgetbv1": false,
+ "cid": false,
+ "hv-relaxed": false,
+ "fxsr": true,
+ "ds": false,
+ "hv-crash": false,
+ "xsaveopt": true,
+ "xtpr": false,
+ "avx512-vpopcntdq": false,
+ "phe": false,
+ "avx512vl": false,
+ "extapic": false,
+ "3dnowprefetch": true,
+ "cr8legacy": false,
+ "stibp": false,
+ "cpuid-0xb": true,
+ "xcrypt-en": false,
+ "kvm_pv_eoi": true,
+ "apic-id": 4294967295,
+ "pn": false,
+ "dca": false,
+ "vendor": "GenuineIntel",
+ "pku": false,
+ "smx": false,
+ "cmp-legacy": false,
+ "cmp_legacy": false,
+ "avx512-4fmaps": false,
+ "vmcb-clean": false,
+ "vmcb_clean": false,
+ "3dnowext": false,
+ "hle": true,
+ "npt": false,
+ "memory": "/machine/unattached/system[0]",
+ "clwb": false,
+ "lbrv": false,
+ "adx": true,
+ "ss": true,
+ "pni": true,
+ "svm_lock": false,
+ "svm-lock": false,
+ "smep": true,
+ "pfthreshold": false,
+ "smap": true,
+ "x2apic": true,
+ "avx512vbmi": false,
+ "i64": true,
+ "flushbyasid": false,
+ "f16c": true,
+ "ace2-en": false,
+ "pat": true,
+ "pae": true,
+ "sse": true,
+ "phe-en": false,
+ "kvm-nopiodelay": true,
+ "kvm_nopiodelay": true,
+ "tm": false,
+ "kvmclock-stable-bit": true,
+ "hypervisor": true,
+ "socket-id": -1,
+ "pcommit": false,
+ "syscall": true,
+ "level": 13,
+ "avx512dq": false,
+ "svm": false,
+ "full-cpuid-auto-level": true,
+ "invtsc": false,
+ "sse3": true,
+ "sse2": true,
+ "est": false,
+ "avx512ifma": false,
+ "tm2": false,
+ "kvm-pv-eoi": true,
+ "cx8": true,
+ "kvm-mmu": false,
+ "kvm_mmu": false,
+ "sse4_2": true,
+ "sse4.2": true,
+ "sse4-2": true,
+ "pge": true,
+ "fill-mtrr-mask": true,
+ "pdcm": false,
+ "nodeid_msr": false,
+ "model": 79,
+ "movbe": true,
+ "nrip-save": false,
+ "nrip_save": false,
+ "sse4a": false,
+ "ssse3": true,
+ "kvm_pv_unhalt": true,
+ "invpcid": true,
+ "pdpe1gb": true,
+ "tsc-deadline": true,
+ "fma": true,
+ "cx16": true,
+ "de": true,
+ "enforce": false,
+ "stepping": 1,
+ "xsave": true,
+ "clflush": true,
+ "arch-facilities": false,
+ "skinit": false,
+ "tce": false,
+ "tsc": true,
+ "fpu": true,
+ "ds-cpl": false,
+ "ds_cpl": false,
+ "ibs": false,
+ "host-phys-bits": true,
+ "fma4": false,
+ "la57": false,
+ "osvw": false,
+ "check": true,
+ "hv-spinlocks": -1,
+ "pmm": false,
+ "apic": true,
+ "pmu": false,
+ "spec-ctrl": false,
+ "min-xlevel2": 0,
+ "tsc-adjust": true,
+ "tsc_adjust": true,
+ "kvm-steal-time": true,
+ "kvm_steal_time": true,
+ "kvmclock": true,
+ "l3-cache": true,
+ "lwp": false,
+ "xop": false,
+ "ibpb": false,
+ "avx": true,
+ "ospke": false,
+ "ace2": false,
+ "acpi": false,
+ "avx512bw": false,
+ "hv-vapic": false,
+ "fsgsbase": true,
+ "ht": false,
+ "nx": true,
+ "pclmulqdq": true,
+ "mmxext": false,
+ "popcnt": true,
+ "xsaves": false,
+ "lm": true,
+ "umip": false,
+ "avx2": true,
+ "pse": true,
+ "sep": true,
+ "pclmuldq": true,
+ "nodeid-msr": false,
+ "kvm": true,
+ "misalignsse": false,
+ "min-xlevel": 2147483656,
+ "bmi2": true,
+ "bmi1": true,
+ "kvm-pv-unhalt": true,
+ "realized": false,
+ "tsc-scale": false,
+ "tsc_scale": false,
+ "topoext": false,
+ "xlevel2": 0,
+ "clflushopt": false,
+ "kvm-no-smi-migration": false,
+ "monitor": false,
+ "avx512er": false,
+ "pmm-en": false,
+ "pcid": true,
+ "3dnow": false,
+ "erms": true,
+ "lahf-lm": true,
+ "lahf_lm": true,
+ "xstore": false,
+ "fxsr-opt": false,
+ "fxsr_opt": false,
+ "rtm": true,
+ "lmce": true,
+ "hv-time": false,
+ "perfctr-nb": false,
+ "perfctr_nb": false,
+ "ffxsr": false,
+ "rdrand": true,
+ "rdseed": true,
+ "avx512-4vnniw": false,
+ "vme": true,
+ "vmx": false,
+ "dtes64": false,
+ "mtrr": true,
+ "rdtscp": true,
+ "pse36": true,
+ "tbm": false,
+ "wdt": false,
+ "pause_filter": false,
+ "model-id": "Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz",
+ "sha-ni": false,
+ "abm": true,
+ "avx512pf": false,
+ "xstore-en": false
+ }
+ }
+ },
+ "id": "model-expansion"
+}
+
+
+{
+ "return": [
+ {
+ "name": "max",
+ "typename": "max-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "host",
+ "typename": "host-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "base",
+ "typename": "base-x86_64-cpu",
+ "unavailable-features": [],
+ "static": true,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64",
+ "typename": "qemu64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32",
+ "typename": "qemu32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom",
+ "typename": "phenom-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "fxsr-opt",
+ "3dnowext",
+ "3dnow",
+ "sse4a",
+ "npt"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3",
+ "typename": "pentium3-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2",
+ "typename": "pentium2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium",
+ "typename": "pentium-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "n270",
+ "typename": "n270-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm64",
+ "typename": "kvm64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm32",
+ "typename": "kvm32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "cpu64-rhel6",
+ "typename": "cpu64-rhel6-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "coreduo",
+ "typename": "coreduo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "core2duo",
+ "typename": "core2duo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "athlon",
+ "typename": "athlon-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "3dnowext",
+ "3dnow"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere",
+ "typename": "Westmere-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere-IBRS",
+ "typename": "Westmere-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client",
+ "typename": "Skylake-Client-x86_64-cpu",
+ "unavailable-features": [
+ "mpx",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client-IBRS",
+ "typename": "Skylake-Client-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "mpx",
+ "spec-ctrl",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge",
+ "typename": "SandyBridge-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge-IBRS",
+ "typename": "SandyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Penryn",
+ "typename": "Penryn-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G5",
+ "typename": "Opteron_G5-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse",
+ "xop",
+ "fma4",
+ "tbm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G4",
+ "typename": "Opteron_G4-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse",
+ "xop",
+ "fma4"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G3",
+ "typename": "Opteron_G3-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G2",
+ "typename": "Opteron_G2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G1",
+ "typename": "Opteron_G1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem",
+ "typename": "Nehalem-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem-IBRS",
+ "typename": "Nehalem-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge",
+ "typename": "IvyBridge-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge-IBRS",
+ "typename": "IvyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell",
+ "typename": "Haswell-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX",
+ "typename": "Haswell-noTSX-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX-IBRS",
+ "typename": "Haswell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-IBRS",
+ "typename": "Haswell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe",
+ "typename": "Conroe-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell",
+ "typename": "Broadwell-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX",
+ "typename": "Broadwell-noTSX-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX-IBRS",
+ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-IBRS",
+ "typename": "Broadwell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "spec-ctrl"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486",
+ "typename": "486-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ }
+ ],
+ "id": "definitions"
+}
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
new file mode 100644
index 0000000000..d74c207104
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
@@ -0,0 +1,43 @@
+<!-- Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x00000014'
ebx='0x756e6547' ecx='0x6c65746e' edx='0x49656e69'/>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x000406f1'
ebx='0x01200800' ecx='0x7ffefbff' edx='0xbfebfbff'/>
+ <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x76036301'
ebx='0x00f0b5ff' ecx='0x00000000' edx='0x00c30000'/>
+ <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x00' eax='0x3c004121'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x01' eax='0x3c004122'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x02' eax='0x3c004143'
ebx='0x01c0003f' ecx='0x000001ff' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x03' eax='0x3c07c163'
ebx='0x04c0003f' ecx='0x00004fff' edx='0x00000006'/>
+ <cpuid eax_in='0x00000005' ecx_in='0x00' eax='0x00000040'
ebx='0x00000040' ecx='0x00000003' edx='0x00002120'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000077'
ebx='0x00000002' ecx='0x00000009' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x021cbfbb' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000008' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000009' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000a' ecx_in='0x00' eax='0x07300403'
ebx='0x00000000' ecx='0x00000000' edx='0x00000603'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000001'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x01' eax='0x00000005'
ebx='0x00000014' ecx='0x00000201' edx='0x00000001'/>
+ <cpuid eax_in='0x0000000c' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x00' eax='0x00000007'
ebx='0x00000340' ecx='0x00000340' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000001'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x02' eax='0x00000100'
ebx='0x00000240' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000e' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000f' ecx_in='0x00' eax='0x00000000'
ebx='0x0000004f' ecx='0x00000000' edx='0x00000002'/>
+ <cpuid eax_in='0x0000000f' ecx_in='0x01' eax='0x00000000'
ebx='0x0000a000' ecx='0x0000004f' edx='0x00000007'/>
+ <cpuid eax_in='0x00000010' ecx_in='0x00' eax='0x00000000'
ebx='0x00000002' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000010' ecx_in='0x01' eax='0x00000013'
ebx='0x000c0000' ecx='0x00000004' edx='0x0000000f'/>
+ <cpuid eax_in='0x00000011' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000012' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000013' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000014' ecx_in='0x00' eax='0x00000000'
ebx='0x00000001' ecx='0x00000001' edx='0x00000000'/>
+ <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x80000008'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000121' edx='0x2c100800'/>
+ <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x65746e49'
ebx='0x2952286c' ecx='0x6f655820' edx='0x2952286e'/>
+ <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x55504320'
ebx='0x2d354520' ecx='0x30333632' edx='0x20347620'/>
+ <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x2e322040'
ebx='0x48473032' ecx='0x0000007a' edx='0x00000000'/>
+ <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x01006040' edx='0x00000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x0000302e'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000000'
ebx='0x00000001' ecx='0x00000001' edx='0x00000000'/>
+ <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000000'
ebx='0x00000001' ecx='0x00000001' edx='0x00000000'/>
+</cpudata>
--
2.21.0
10:29 p.m.
New subject: [libvirt] [PATCH 02/26] cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4
On Wed, Feb 27, 2019 at 02:28:52PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml | 7 +
.../x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 31 +
.../x86_64-cpuid-Xeon-E5-2630-v4-host.xml | 35 +
.../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 +
.../x86_64-cpuid-Xeon-E5-2630-v4.json | 596 ++++++++++++++++++
.../x86_64-cpuid-Xeon-E5-2630-v4.xml | 43 ++
8 files changed, 732 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 03/26] cputest: Add data for Intel(R) Core(TM) i7-7600U
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Core-i7-7600U-disabled.xml | 6 +
.../x86_64-cpuid-Core-i7-7600U-enabled.xml | 8 +
.../x86_64-cpuid-Core-i7-7600U-guest.xml | 28 +
.../x86_64-cpuid-Core-i7-7600U-host.xml | 29 +
.../x86_64-cpuid-Core-i7-7600U-json.xml | 13 +
.../x86_64-cpuid-Core-i7-7600U.json | 755 ++++++++++++++++++
.../x86_64-cpuid-Core-i7-7600U.xml | 47 ++
8 files changed, 887 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
diff --git a/tests/cputest.c b/tests/cputest.c
index 323b662bc3..e1c913b3f3 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -1170,6 +1170,7 @@ mymain(void)
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U-arat", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U-ibrs", JSON_HOST);
+ DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7600U", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7700", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-E6850", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-Q9500", JSON_NONE);
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
new file mode 100644
index 0000000000..0a567bbfae
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
@@ -0,0 +1,6 @@
+<!-- Features disabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x0800c1dc' edx='0xb0600000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x02000000' ecx='0x00000000' edx='0x08000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
new file mode 100644
index 0000000000..b1cdaa802a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
@@ -0,0 +1,8 @@
+<!-- Features enabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0xf7fa3223' edx='0x0f8bfbff'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x009c4fbb' ecx='0x00000004' edx='0x84000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x0000000f'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000121' edx='0x2c100800'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
new file mode 100644
index 0000000000..70a0fc3286
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
@@ -0,0 +1,28 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='ds'/>
+ <feature policy='require' name='acpi'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='ht'/>
+ <feature policy='require' name='tm'/>
+ <feature policy='require' name='pbe'/>
+ <feature policy='require' name='dtes64'/>
+ <feature policy='require' name='monitor'/>
+ <feature policy='require' name='ds_cpl'/>
+ <feature policy='require' name='vmx'/>
+ <feature policy='require' name='smx'/>
+ <feature policy='require' name='est'/>
+ <feature policy='require' name='tm2'/>
+ <feature policy='require' name='xtpr'/>
+ <feature policy='require' name='pdcm'/>
+ <feature policy='require' name='osxsave'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='clflushopt'/>
+ <feature policy='require' name='intel-pt'/>
+ <feature policy='require' name='stibp'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='xsaves'/>
+ <feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
new file mode 100644
index 0000000000..bbdfb6aa61
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
@@ -0,0 +1,29 @@
+<cpu>
+ <arch>x86_64</arch>
+ <model>Skylake-Client-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature name='ds'/>
+ <feature name='acpi'/>
+ <feature name='ss'/>
+ <feature name='ht'/>
+ <feature name='tm'/>
+ <feature name='pbe'/>
+ <feature name='dtes64'/>
+ <feature name='monitor'/>
+ <feature name='ds_cpl'/>
+ <feature name='vmx'/>
+ <feature name='smx'/>
+ <feature name='est'/>
+ <feature name='tm2'/>
+ <feature name='xtpr'/>
+ <feature name='pdcm'/>
+ <feature name='osxsave'/>
+ <feature name='tsc_adjust'/>
+ <feature name='clflushopt'/>
+ <feature name='intel-pt'/>
+ <feature name='stibp'/>
+ <feature name='ssbd'/>
+ <feature name='xsaves'/>
+ <feature name='pdpe1gb'/>
+ <feature name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
new file mode 100644
index 0000000000..48089c6003
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
@@ -0,0 +1,13 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='vmx'/>
+ <feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='clflushopt'/>
+ <feature policy='require' name='umip'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='xsaves'/>
+ <feature policy='require' name='pdpe1gb'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
new file mode 100644
index 0000000000..9a258e6be3
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
@@ -0,0 +1,755 @@
+{
+ "return": {
+ "model": {
+ "name": "base",
+ "props": {
+ "phys-bits": 0,
+ "core-id": -1,
+ "xlevel": 2147483656,
+ "cmov": true,
+ "ia64": false,
+ "ssb-no": false,
+ "aes": true,
+ "mmx": true,
+ "rdpid": false,
+ "arat": true,
+ "gfni": false,
+ "ibrs-all": false,
+ "pause-filter": false,
+ "xsavec": true,
+ "intel-pt": false,
+ "hv-frequencies": false,
+ "tsc-frequency": 0,
+ "xd": true,
+ "hv-vendor-id": "",
+ "kvm-asyncpf": true,
+ "kvm_asyncpf": true,
+ "perfctr_core": false,
+ "perfctr-core": false,
+ "mpx": true,
+ "pbe": false,
+ "decodeassists": false,
+ "avx512cd": false,
+ "sse4_1": true,
+ "sse4.1": true,
+ "sse4-1": true,
+ "family": 6,
+ "legacy-cache": true,
+ "vmware-cpuid-freq": true,
+ "wbnoinvd": false,
+ "avx512f": false,
+ "msr": true,
+ "mce": true,
+ "mca": true,
+ "hv-runtime": false,
+ "xcrypt": false,
+ "thread-id": -1,
+ "min-level": 13,
+ "xgetbv1": true,
+ "cid": false,
+ "hv-relaxed": false,
+ "hv-crash": false,
+ "ds": false,
+ "fxsr": true,
+ "xsaveopt": true,
+ "xtpr": false,
+ "hv-evmcs": false,
+ "avx512vl": false,
+ "avx512-vpopcntdq": false,
+ "phe": false,
+ "extapic": false,
+ "3dnowprefetch": true,
+ "avx512vbmi2": false,
+ "cr8legacy": false,
+ "cpuid-0xb": true,
+ "xcrypt-en": false,
+ "kvm_pv_eoi": true,
+ "apic-id": 4294967295,
+ "rsba": false,
+ "pn": false,
+ "dca": false,
+ "vendor": "GenuineIntel",
+ "hv-ipi": false,
+ "pku": false,
+ "smx": false,
+ "cmp_legacy": false,
+ "cmp-legacy": false,
+ "node-id": -1,
+ "avx512-4fmaps": false,
+ "vmcb_clean": false,
+ "vmcb-clean": false,
+ "3dnowext": false,
+ "amd-no-ssb": false,
+ "hle": true,
+ "npt": false,
+ "rdctl-no": false,
+ "memory": "/machine/unattached/system[0]",
+ "clwb": false,
+ "lbrv": false,
+ "adx": true,
+ "ss": true,
+ "pni": true,
+ "svm_lock": false,
+ "svm-lock": false,
+ "pfthreshold": false,
+ "smep": true,
+ "smap": true,
+ "x2apic": true,
+ "avx512vbmi": false,
+ "avx512vnni": false,
+ "hv-stimer": false,
+ "x-hv-synic-kvm-only": false,
+ "i64": true,
+ "flushbyasid": false,
+ "f16c": true,
+ "ace2-en": false,
+ "pat": true,
+ "pae": true,
+ "sse": true,
+ "phe-en": false,
+ "kvm_nopiodelay": true,
+ "kvm-nopiodelay": true,
+ "tm": false,
+ "kvmclock-stable-bit": true,
+ "hypervisor": true,
+ "socket-id": -1,
+ "pcommit": false,
+ "syscall": true,
+ "level": 13,
+ "avx512dq": false,
+ "x-migrate-smi-count": true,
+ "svm": false,
+ "full-cpuid-auto-level": true,
+ "hv-reset": false,
+ "invtsc": false,
+ "sse3": true,
+ "sse2": true,
+ "ssbd": true,
+ "est": false,
+ "avx512ifma": false,
+ "tm2": false,
+ "kvm-pv-ipi": true,
+ "kvm-pv-eoi": true,
+ "cx8": true,
+ "cldemote": false,
+ "hv-reenlightenment": false,
+ "kvm_mmu": false,
+ "kvm-mmu": false,
+ "sse4_2": true,
+ "sse4.2": true,
+ "sse4-2": true,
+ "pge": true,
+ "fill-mtrr-mask": true,
+ "avx512bitalg": false,
+ "nodeid_msr": false,
+ "pdcm": false,
+ "movbe": true,
+ "model": 142,
+ "nrip_save": false,
+ "nrip-save": false,
+ "kvm_pv_unhalt": true,
+ "ssse3": true,
+ "sse4a": false,
+ "invpcid": true,
+ "pdpe1gb": true,
+ "tsc-deadline": true,
+ "skip-l1dfl-vmentry": true,
+ "fma": true,
+ "cx16": true,
+ "de": true,
+ "pconfig": false,
+ "enforce": false,
+ "stepping": 9,
+ "xsave": true,
+ "clflush": true,
+ "skinit": false,
+ "tsc": true,
+ "tce": false,
+ "fpu": true,
+ "ibs": false,
+ "ds_cpl": false,
+ "ds-cpl": false,
+ "host-phys-bits": false,
+ "fma4": false,
+ "la57": false,
+ "osvw": false,
+ "check": true,
+ "hv-spinlocks": -1,
+ "pmu": false,
+ "pmm": false,
+ "apic": true,
+ "spec-ctrl": true,
+ "min-xlevel2": 0,
+ "tsc-adjust": true,
+ "tsc_adjust": true,
+ "kvm-steal-time": true,
+ "kvm_steal_time": true,
+ "kvmclock": true,
+ "l3-cache": true,
+ "lwp": false,
+ "amd-ssbd": false,
+ "ibpb": false,
+ "xop": false,
+ "avx": true,
+ "ace2": false,
+ "avx512bw": false,
+ "acpi": false,
+ "hv-vapic": false,
+ "fsgsbase": true,
+ "ht": false,
+ "nx": true,
+ "pclmulqdq": true,
+ "mmxext": false,
+ "vaes": false,
+ "popcnt": true,
+ "xsaves": true,
+ "tcg-cpuid": true,
+ "lm": true,
+ "umip": true,
+ "pse": true,
+ "avx2": true,
+ "sep": true,
+ "pclmuldq": true,
+ "virt-ssbd": false,
+ "x-hv-max-vps": -1,
+ "nodeid-msr": false,
+ "kvm": true,
+ "misalignsse": false,
+ "min-xlevel": 2147483656,
+ "kvm-pv-unhalt": true,
+ "bmi2": true,
+ "bmi1": true,
+ "realized": false,
+ "tsc_scale": false,
+ "tsc-scale": false,
+ "topoext": false,
+ "hv-vpindex": false,
+ "xlevel2": 0,
+ "clflushopt": true,
+ "kvm-no-smi-migration": false,
+ "monitor": false,
+ "avx512er": false,
+ "pmm-en": false,
+ "pcid": true,
+ "arch-capabilities": false,
+ "3dnow": false,
+ "erms": true,
+ "lahf-lm": true,
+ "lahf_lm": true,
+ "vpclmulqdq": false,
+ "fxsr-opt": false,
+ "hv-synic": false,
+ "xstore": false,
+ "fxsr_opt": false,
+ "kvm-hint-dedicated": false,
+ "rtm": true,
+ "lmce": true,
+ "hv-time": false,
+ "perfctr-nb": false,
+ "perfctr_nb": false,
+ "ffxsr": false,
+ "hv-tlbflush": false,
+ "rdrand": true,
+ "rdseed": true,
+ "avx512-4vnniw": false,
+ "vmx": true,
+ "vme": true,
+ "dtes64": false,
+ "mtrr": true,
+ "rdtscp": true,
+ "pse36": true,
+ "kvm-pv-tlb-flush": true,
+ "tbm": false,
+ "wdt": false,
+ "pause_filter": false,
+ "sha-ni": false,
+ "model-id": "Intel(R) Core(TM) i7-7600U CPU @ 2.80GHz",
+ "abm": true,
+ "avx512pf": false,
+ "xstore-en": false
+ }
+ }
+ },
+ "id": "model-expansion"
+}
+
+
+{
+ "return": [
+ {
+ "name": "max",
+ "typename": "max-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "host",
+ "typename": "host-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "base",
+ "typename": "base-x86_64-cpu",
+ "unavailable-features": [],
+ "static": true,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64",
+ "typename": "qemu64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32",
+ "typename": "qemu32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom",
+ "typename": "phenom-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "fxsr-opt",
+ "3dnowext",
+ "3dnow",
+ "sse4a",
+ "npt"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3",
+ "typename": "pentium3-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2",
+ "typename": "pentium2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium",
+ "typename": "pentium-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "n270",
+ "typename": "n270-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm64",
+ "typename": "kvm64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm32",
+ "typename": "kvm32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "coreduo",
+ "typename": "coreduo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "core2duo",
+ "typename": "core2duo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "athlon",
+ "typename": "athlon-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "3dnowext",
+ "3dnow"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere-IBRS",
+ "typename": "Westmere-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere",
+ "typename": "Westmere-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server-IBRS",
+ "typename": "Skylake-Server-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server",
+ "typename": "Skylake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client-IBRS",
+ "typename": "Skylake-Client-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client",
+ "typename": "Skylake-Client-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge-IBRS",
+ "typename": "SandyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge",
+ "typename": "SandyBridge-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Penryn",
+ "typename": "Penryn-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G5",
+ "typename": "Opteron_G5-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse",
+ "xop",
+ "fma4",
+ "tbm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G4",
+ "typename": "Opteron_G4-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse",
+ "xop",
+ "fma4"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G3",
+ "typename": "Opteron_G3-x86_64-cpu",
+ "unavailable-features": [
+ "sse4a",
+ "misalignsse"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G2",
+ "typename": "Opteron_G2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G1",
+ "typename": "Opteron_G1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem-IBRS",
+ "typename": "Nehalem-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem",
+ "typename": "Nehalem-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "KnightsMill",
+ "typename": "KnightsMill-x86_64-cpu",
+ "unavailable-features": [
+ "avx512f",
+ "avx512pf",
+ "avx512er",
+ "avx512cd",
+ "avx512-vpopcntdq",
+ "avx512-4vnniw",
+ "avx512-4fmaps",
+ "avx512f",
+ "avx512f",
+ "avx512f"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge-IBRS",
+ "typename": "IvyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge",
+ "typename": "IvyBridge-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Icelake-Server",
+ "typename": "Icelake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "intel-pt",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "avx512vbmi",
+ "pku",
+ "",
+ "avx512vbmi2",
+ "gfni",
+ "vaes",
+ "vpclmulqdq",
+ "avx512vnni",
+ "avx512bitalg",
+ "avx512-vpopcntdq",
+ "la57",
+ "pconfig",
+ "wbnoinvd",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Icelake-Client",
+ "typename": "Icelake-Client-x86_64-cpu",
+ "unavailable-features": [
+ "intel-pt",
+ "avx512vbmi",
+ "pku",
+ "",
+ "avx512vbmi2",
+ "gfni",
+ "vaes",
+ "vpclmulqdq",
+ "avx512vnni",
+ "avx512bitalg",
+ "avx512-vpopcntdq",
+ "wbnoinvd",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX-IBRS",
+ "typename": "Haswell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX",
+ "typename": "Haswell-noTSX-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-IBRS",
+ "typename": "Haswell-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell",
+ "typename": "Haswell-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-IBPB",
+ "typename": "EPYC-IBPB-x86_64-cpu",
+ "unavailable-features": [
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "cr8legacy",
+ "sse4a",
+ "misalignsse",
+ "osvw",
+ "ibpb"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC",
+ "typename": "EPYC-x86_64-cpu",
+ "unavailable-features": [
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "cr8legacy",
+ "sse4a",
+ "misalignsse",
+ "osvw"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe",
+ "typename": "Conroe-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Cascadelake-Server",
+ "typename": "Cascadelake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "avx512f",
+ "avx512dq",
+ "clwb",
+ "intel-pt",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pku",
+ "",
+ "avx512vnni",
+ "avx512f",
+ "avx512f",
+ "avx512f",
+ "pku"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX-IBRS",
+ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX",
+ "typename": "Broadwell-noTSX-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-IBRS",
+ "typename": "Broadwell-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell",
+ "typename": "Broadwell-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486",
+ "typename": "486-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ }
+ ],
+ "id": "definitions"
+}
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
new file mode 100644
index 0000000000..d46811e3d3
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
@@ -0,0 +1,47 @@
+<!-- Intel(R) Core(TM) i7-7600U CPU @ 2.80GHz -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x00000016'
ebx='0x756e6547' ecx='0x6c65746e' edx='0x49656e69'/>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x000806e9'
ebx='0x03100800' ecx='0x7ffafbff' edx='0xbfebfbff'/>
+ <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x76036301'
ebx='0x00f0b5ff' ecx='0x00000000' edx='0x00c30000'/>
+ <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x00' eax='0x1c004121'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x01' eax='0x1c004122'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x02' eax='0x1c004143'
ebx='0x00c0003f' ecx='0x000003ff' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x03' eax='0x1c03c163'
ebx='0x03c0003f' ecx='0x00000fff' edx='0x00000006'/>
+ <cpuid eax_in='0x00000005' ecx_in='0x00' eax='0x00000040'
ebx='0x00000040' ecx='0x00000003' edx='0x11142120'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x000027f7'
ebx='0x00000002' ecx='0x00000009' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x029c6fbf' ecx='0x00000000' edx='0x9c000000'/>
+ <cpuid eax_in='0x00000008' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000009' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000a' ecx_in='0x00' eax='0x07300404'
ebx='0x00000000' ecx='0x00000000' edx='0x00000603'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000003'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x01' eax='0x00000004'
ebx='0x00000004' ecx='0x00000201' edx='0x00000003'/>
+ <cpuid eax_in='0x0000000c' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x00' eax='0x0000001f'
ebx='0x00000440' ecx='0x00000440' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x0000000f'
ebx='0x000003c0' ecx='0x00000100' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x02' eax='0x00000100'
ebx='0x00000240' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x03' eax='0x00000040'
ebx='0x000003c0' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x04' eax='0x00000040'
ebx='0x00000400' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x08' eax='0x00000080'
ebx='0x00000000' ecx='0x00000001' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000e' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000f' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000010' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000011' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000012' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000013' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000014' ecx_in='0x00' eax='0x00000001'
ebx='0x0000000f' ecx='0x00000007' edx='0x00000000'/>
+ <cpuid eax_in='0x00000014' ecx_in='0x01' eax='0x02490002'
ebx='0x003f3fff' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000015' ecx_in='0x00' eax='0x00000002'
ebx='0x000000f2' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000016' ecx_in='0x00' eax='0x00000b54'
ebx='0x00000f3c' ecx='0x00000064' edx='0x00000000'/>
+ <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x80000008'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000121' edx='0x2c100800'/>
+ <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x65746e49'
ebx='0x2952286c' ecx='0x726f4320' edx='0x4d542865'/>
+ <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x37692029'
ebx='0x3036372d' ecx='0x43205530' edx='0x40205550'/>
+ <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x382e3220'
ebx='0x7a484730' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x01006040' edx='0x00000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x00003027'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000b54'
ebx='0x00000f3c' ecx='0x00000064' edx='0x00000000'/>
+ <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000b54'
ebx='0x00000f3c' ecx='0x00000064' edx='0x00000000'/>
+</cpudata>
--
2.21.0
10:30 p.m.
New subject: [libvirt] [PATCH 03/26] cputest: Add data for Intel(R) Core(TM) i7-7600U
On Wed, Feb 27, 2019 at 02:28:53PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Core-i7-7600U-disabled.xml | 6 +
.../x86_64-cpuid-Core-i7-7600U-enabled.xml | 8 +
.../x86_64-cpuid-Core-i7-7600U-guest.xml | 28 +
.../x86_64-cpuid-Core-i7-7600U-host.xml | 29 +
.../x86_64-cpuid-Core-i7-7600U-json.xml | 13 +
.../x86_64-cpuid-Core-i7-7600U.json | 755 ++++++++++++++++++
.../x86_64-cpuid-Core-i7-7600U.xml | 47 ++
8 files changed, 887 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 04/26] cputest: Add data for Intel(R) Xeon(R) CPU E7540
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E7540-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E7540-enabled.xml | 7 +
.../x86_64-cpuid-Xeon-E7540-guest.xml | 25 +
.../x86_64-cpuid-Xeon-E7540-host.xml | 26 +
.../x86_64-cpuid-Xeon-E7540-json.xml | 14 +
.../cputestdata/x86_64-cpuid-Xeon-E7540.json | 1117 +++++++++++++++++
tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml | 30 +
8 files changed, 1225 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
diff --git a/tests/cputest.c b/tests/cputest.c
index e1c913b3f3..e4d58b8f7d 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -1195,6 +1195,7 @@ mymain(void)
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4830", JSON_MODELS_REQUIRED);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-8890-v3", JSON_MODELS);
+ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7540", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-Gold-5115", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-Gold-6148", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-W3520", JSON_HOST);
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
new file mode 100644
index 0000000000..49737fbdb1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
@@ -0,0 +1,5 @@
+<!-- Features disabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x0004c1bc' edx='0xb0600000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
new file mode 100644
index 0000000000..8149ac04f0
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
@@ -0,0 +1,7 @@
+<!-- Features enabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x81b82201' edx='0x0f8bfbff'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000002' ecx='0x00000000' edx='0x8c000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000001' edx='0x28100800'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
new file mode 100644
index 0000000000..fc3e95253b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
@@ -0,0 +1,25 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Nehalem-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
+ <feature policy='require' name='ds'/>
+ <feature policy='require' name='acpi'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='ht'/>
+ <feature policy='require' name='tm'/>
+ <feature policy='require' name='pbe'/>
+ <feature policy='require' name='dtes64'/>
+ <feature policy='require' name='monitor'/>
+ <feature policy='require' name='ds_cpl'/>
+ <feature policy='require' name='vmx'/>
+ <feature policy='require' name='est'/>
+ <feature policy='require' name='tm2'/>
+ <feature policy='require' name='xtpr'/>
+ <feature policy='require' name='pdcm'/>
+ <feature policy='require' name='dca'/>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='stibp'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='rdtscp'/>
+ <feature policy='require' name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
new file mode 100644
index 0000000000..42b43116bd
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
@@ -0,0 +1,26 @@
+<cpu>
+ <arch>x86_64</arch>
+ <model>Nehalem-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature name='vme'/>
+ <feature name='ds'/>
+ <feature name='acpi'/>
+ <feature name='ss'/>
+ <feature name='ht'/>
+ <feature name='tm'/>
+ <feature name='pbe'/>
+ <feature name='dtes64'/>
+ <feature name='monitor'/>
+ <feature name='ds_cpl'/>
+ <feature name='vmx'/>
+ <feature name='est'/>
+ <feature name='tm2'/>
+ <feature name='xtpr'/>
+ <feature name='pdcm'/>
+ <feature name='dca'/>
+ <feature name='x2apic'/>
+ <feature name='stibp'/>
+ <feature name='ssbd'/>
+ <feature name='rdtscp'/>
+ <feature name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
new file mode 100644
index 0000000000..32cd1000c8
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
@@ -0,0 +1,14 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>Nehalem-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='tsc-deadline'/>
+ <feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='arat'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='stibp'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='rdtscp'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
new file mode 100644
index 0000000000..ac8452509d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
@@ -0,0 +1,1117 @@
+{
+ "return": {
+ "model": {
+ "name": "base",
+ "props": {
+ "phys-bits": 0,
+ "core-id": -1,
+ "xlevel": 2147483656,
+ "cmov": true,
+ "ia64": false,
+ "aes": false,
+ "mmx": true,
+ "rdpid": false,
+ "arat": true,
+ "gfni": false,
+ "pause-filter": false,
+ "xsavec": false,
+ "intel-pt": false,
+ "osxsave": false,
+ "hv-frequencies": false,
+ "tsc-frequency": 0,
+ "xd": true,
+ "hv-vendor-id": "",
+ "kvm-asyncpf": true,
+ "kvm_asyncpf": true,
+ "perfctr_core": false,
+ "perfctr-core": false,
+ "mpx": false,
+ "pbe": false,
+ "decodeassists": false,
+ "avx512cd": false,
+ "sse4_1": true,
+ "sse4.1": true,
+ "sse4-1": true,
+ "family": 6,
+ "legacy-cache": true,
+ "vmware-cpuid-freq": true,
+ "avx512f": false,
+ "msr": true,
+ "mce": true,
+ "mca": true,
+ "hv-runtime": false,
+ "xcrypt": false,
+ "thread-id": -1,
+ "min-level": 11,
+ "xgetbv1": false,
+ "cid": false,
+ "hv-relaxed": false,
+ "hv-crash": false,
+ "ds": false,
+ "fxsr": true,
+ "xsaveopt": false,
+ "xtpr": false,
+ "avx512vl": false,
+ "avx512-vpopcntdq": false,
+ "phe": false,
+ "extapic": false,
+ "3dnowprefetch": false,
+ "avx512vbmi2": false,
+ "cr8legacy": false,
+ "stibp": true,
+ "cpuid-0xb": true,
+ "xcrypt-en": false,
+ "kvm_pv_eoi": true,
+ "apic-id": 4294967295,
+ "pn": false,
+ "dca": false,
+ "vendor": "GenuineIntel",
+ "pku": false,
+ "smx": false,
+ "cmp_legacy": false,
+ "cmp-legacy": false,
+ "node-id": -1,
+ "avx512-4fmaps": false,
+ "vmcb_clean": false,
+ "vmcb-clean": false,
+ "3dnowext": false,
+ "hle": false,
+ "npt": false,
+ "memory": "/machine/unattached/system[0]",
+ "clwb": false,
+ "lbrv": false,
+ "adx": false,
+ "ss": true,
+ "pni": true,
+ "svm_lock": false,
+ "svm-lock": false,
+ "pfthreshold": false,
+ "smep": false,
+ "smap": false,
+ "x2apic": true,
+ "avx512vbmi": false,
+ "avx512vnni": false,
+ "hv-stimer": false,
+ "i64": true,
+ "flushbyasid": false,
+ "f16c": false,
+ "ace2-en": false,
+ "pat": true,
+ "pae": true,
+ "sse": true,
+ "phe-en": false,
+ "kvm_nopiodelay": true,
+ "kvm-nopiodelay": true,
+ "tm": false,
+ "kvmclock-stable-bit": true,
+ "hypervisor": true,
+ "socket-id": -1,
+ "pcommit": false,
+ "syscall": true,
+ "level": 11,
+ "avx512dq": false,
+ "svm": false,
+ "full-cpuid-auto-level": true,
+ "hv-reset": false,
+ "invtsc": false,
+ "sse3": true,
+ "sse2": true,
+ "ssbd": true,
+ "est": false,
+ "avx512ifma": false,
+ "tm2": false,
+ "kvm-pv-eoi": true,
+ "cx8": true,
+ "kvm_mmu": false,
+ "kvm-mmu": false,
+ "sse4_2": true,
+ "sse4.2": true,
+ "sse4-2": true,
+ "pge": true,
+ "fill-mtrr-mask": true,
+ "avx512bitalg": false,
+ "nodeid_msr": false,
+ "pdcm": false,
+ "movbe": false,
+ "model": 46,
+ "nrip_save": false,
+ "nrip-save": false,
+ "kvm_pv_unhalt": true,
+ "ssse3": true,
+ "sse4a": false,
+ "invpcid": false,
+ "pdpe1gb": false,
+ "tsc-deadline": true,
+ "fma": false,
+ "cx16": true,
+ "de": true,
+ "enforce": false,
+ "stepping": 6,
+ "xsave": false,
+ "clflush": true,
+ "skinit": false,
+ "tsc": true,
+ "tce": false,
+ "fpu": true,
+ "ibs": false,
+ "ds_cpl": false,
+ "ds-cpl": false,
+ "host-phys-bits": true,
+ "fma4": false,
+ "la57": false,
+ "osvw": false,
+ "check": true,
+ "hv-spinlocks": -1,
+ "pmu": false,
+ "pmm": false,
+ "apic": true,
+ "spec-ctrl": true,
+ "min-xlevel2": 0,
+ "tsc-adjust": true,
+ "tsc_adjust": true,
+ "kvm-steal-time": true,
+ "kvm_steal_time": true,
+ "kvmclock": true,
+ "l3-cache": true,
+ "lwp": false,
+ "ibpb": false,
+ "xop": false,
+ "avx": false,
+ "ospke": false,
+ "ace2": false,
+ "avx512bw": false,
+ "acpi": false,
+ "hv-vapic": false,
+ "fsgsbase": false,
+ "ht": false,
+ "nx": true,
+ "pclmulqdq": false,
+ "mmxext": false,
+ "vaes": false,
+ "popcnt": true,
+ "xsaves": false,
+ "tcg-cpuid": true,
+ "lm": true,
+ "umip": false,
+ "pse": true,
+ "avx2": false,
+ "sep": true,
+ "pclmuldq": false,
+ "virt-ssbd": false,
+ "x-hv-max-vps": -1,
+ "nodeid-msr": false,
+ "kvm": true,
+ "misalignsse": false,
+ "min-xlevel": 2147483656,
+ "kvm-pv-unhalt": true,
+ "bmi2": false,
+ "bmi1": false,
+ "realized": false,
+ "tsc_scale": false,
+ "tsc-scale": false,
+ "topoext": false,
+ "hv-vpindex": false,
+ "xlevel2": 0,
+ "clflushopt": false,
+ "kvm-no-smi-migration": false,
+ "monitor": false,
+ "avx512er": false,
+ "pmm-en": false,
+ "pcid": false,
+ "3dnow": false,
+ "erms": false,
+ "lahf-lm": true,
+ "lahf_lm": true,
+ "vpclmulqdq": false,
+ "fxsr-opt": false,
+ "hv-synic": false,
+ "xstore": false,
+ "fxsr_opt": false,
+ "kvm-hint-dedicated": false,
+ "rtm": false,
+ "lmce": true,
+ "hv-time": false,
+ "perfctr-nb": false,
+ "perfctr_nb": false,
+ "ffxsr": false,
+ "rdrand": false,
+ "rdseed": false,
+ "avx512-4vnniw": false,
+ "vmx": false,
+ "vme": true,
+ "dtes64": false,
+ "mtrr": true,
+ "rdtscp": true,
+ "pse36": true,
+ "kvm-pv-tlb-flush": false,
+ "tbm": false,
+ "wdt": false,
+ "pause_filter": false,
+ "sha-ni": false,
+ "model-id": "Intel(R) Xeon(R) CPU E7540 @
2.00GHz",
+ "abm": false,
+ "avx512pf": false,
+ "xstore-en": false
+ }
+ }
+ },
+ "id": "model-expansion"
+}
+
+
+{
+ "return": [
+ {
+ "name": "max",
+ "typename": "max-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "host",
+ "typename": "host-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "base",
+ "typename": "base-x86_64-cpu",
+ "unavailable-features": [],
+ "static": true,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64",
+ "typename": "qemu64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32",
+ "typename": "qemu32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom",
+ "typename": "phenom-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "fxsr-opt",
+ "pdpe1gb",
+ "3dnowext",
+ "3dnow",
+ "abm",
+ "sse4a",
+ "npt"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3",
+ "typename": "pentium3-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2",
+ "typename": "pentium2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium",
+ "typename": "pentium-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "n270",
+ "typename": "n270-x86_64-cpu",
+ "unavailable-features": [
+ "movbe"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm64",
+ "typename": "kvm64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm32",
+ "typename": "kvm32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "cpu64-rhel6",
+ "typename": "cpu64-rhel6-x86_64-cpu",
+ "unavailable-features": [
+ "abm",
+ "sse4a"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "coreduo",
+ "typename": "coreduo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "core2duo",
+ "typename": "core2duo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "athlon",
+ "typename": "athlon-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "3dnowext",
+ "3dnow"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere",
+ "typename": "Westmere-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere-IBRS",
+ "typename": "Westmere-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server",
+ "typename": "Skylake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "avx512f",
+ "avx512dq",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pdpe1gb",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx",
+ "mpx",
+ "mpx",
+ "avx512f",
+ "avx512f",
+ "avx512f"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server-IBRS",
+ "typename": "Skylake-Server-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "avx512f",
+ "avx512dq",
+ "rdseed",
+ "adx",
+ "smap",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "pdpe1gb",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx",
+ "mpx",
+ "mpx",
+ "avx512f",
+ "avx512f",
+ "avx512f"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client",
+ "typename": "Skylake-Client-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client-IBRS",
+ "typename": "Skylake-Client-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge",
+ "typename": "SandyBridge-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "xsave",
+ "avx",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge-IBRS",
+ "typename": "SandyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "xsave",
+ "avx",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Penryn",
+ "typename": "Penryn-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G5",
+ "typename": "Opteron_G5-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "pdpe1gb",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "xop",
+ "fma4",
+ "tbm",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G4",
+ "typename": "Opteron_G4-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "xsave",
+ "avx",
+ "pdpe1gb",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "xop",
+ "fma4",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G3",
+ "typename": "Opteron_G3-x86_64-cpu",
+ "unavailable-features": [
+ "abm",
+ "sse4a",
+ "misalignsse"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G2",
+ "typename": "Opteron_G2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G1",
+ "typename": "Opteron_G1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem",
+ "typename": "Nehalem-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem-IBRS",
+ "typename": "Nehalem-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge",
+ "typename": "IvyBridge-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "smep",
+ "erms",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge-IBRS",
+ "typename": "IvyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "smep",
+ "erms",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell",
+ "typename": "Haswell-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "abm",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX",
+ "typename": "Haswell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "abm",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX-IBRS",
+ "typename": "Haswell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "abm",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-IBRS",
+ "typename": "Haswell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "abm",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC",
+ "typename": "EPYC-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "pdpe1gb",
+ "cr8legacy",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "osvw",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-IBPB",
+ "typename": "EPYC-IBPB-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "pdpe1gb",
+ "cr8legacy",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "osvw",
+ "ibpb",
+ "xsaveopt",
+ "xsavec",
+ "xgetbv1",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe",
+ "typename": "Conroe-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell",
+ "typename": "Broadwell-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX",
+ "typename": "Broadwell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX-IBRS",
+ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-IBRS",
+ "typename": "Broadwell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "pclmulqdq",
+ "fma",
+ "pcid",
+ "movbe",
+ "aes",
+ "xsave",
+ "avx",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsaveopt",
+ "xsave",
+ "xsave",
+ "avx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486",
+ "typename": "486-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ }
+ ],
+ "id": "definitions"
+}
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
new file mode 100644
index 0000000000..e80694b5e0
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
@@ -0,0 +1,30 @@
+<!-- Intel(R) Xeon(R) CPU E7540 @ 2.00GHz -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x0000000b'
ebx='0x756e6547' ecx='0x6c65746e' edx='0x49656e69'/>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x000206e6'
ebx='0x05200800' ecx='0x00bce3bd' edx='0xbfebfbff'/>
+ <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x55035a01'
ebx='0x00f0b2eb' ecx='0x00000000' edx='0x09ca212c'/>
+ <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x00' eax='0x3c004121'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x01' eax='0x3c004122'
ebx='0x00c0003f' ecx='0x0000007f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x02' eax='0x3c004143'
ebx='0x01c0003f' ecx='0x000001ff' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x03' eax='0x3c07c163'
ebx='0x05c0003f' ecx='0x00002fff' edx='0x00000006'/>
+ <cpuid eax_in='0x00000005' ecx_in='0x00' eax='0x00000040'
ebx='0x00000040' ecx='0x00000003' edx='0x00000120'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000003'
ebx='0x00000001' ecx='0x00000001' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x9c000000'/>
+ <cpuid eax_in='0x00000008' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000009' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000a' ecx_in='0x00' eax='0x07300403'
ebx='0x00000044' ecx='0x00000000' edx='0x00000603'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000005'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x01' eax='0x00000005'
ebx='0x0000000c' ecx='0x00000201' edx='0x00000005'/>
+ <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x80000008'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000001' edx='0x28100800'/>
+ <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x65746e49'
ebx='0x2952286c' ecx='0x6f655820' edx='0x2952286e'/>
+ <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x55504320'
ebx='0x20202020' ecx='0x20202020' edx='0x45202020'/>
+ <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x30343537'
ebx='0x20402020' ecx='0x30302e32' edx='0x007a4847'/>
+ <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x01006040' edx='0x00000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x0000302c'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000005'/>
+ <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000005'/>
+</cpudata>
--
2.21.0
10:38 p.m.
New subject: [libvirt] [PATCH 04/26] cputest: Add data for Intel(R) Xeon(R) CPU E7540
On Wed, Feb 27, 2019 at 02:28:54PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E7540-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E7540-enabled.xml | 7 +
.../x86_64-cpuid-Xeon-E7540-guest.xml | 25 +
.../x86_64-cpuid-Xeon-E7540-host.xml | 26 +
.../x86_64-cpuid-Xeon-E7540-json.xml | 14 +
.../cputestdata/x86_64-cpuid-Xeon-E7540.json | 1117 +++++++++++++++++
tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml | 30 +
8 files changed, 1225 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 05/26] cputest: Add data for Intel(R) Xeon(R) CPU E5-2650
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E5-2650-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E5-2650-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2650-guest.xml | 29 +
.../x86_64-cpuid-Xeon-E5-2650-host.xml | 30 +
.../x86_64-cpuid-Xeon-E5-2650-json.xml | 14 +
.../x86_64-cpuid-Xeon-E5-2650.json | 931 ++++++++++++++++++
.../cputestdata/x86_64-cpuid-Xeon-E5-2650.xml | 34 +
8 files changed, 1052 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
diff --git a/tests/cputest.c b/tests/cputest.c
index e4d58b8f7d..19caf41bf3 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -1190,6 +1190,7 @@ mymain(void)
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2623-v4", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v3", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v4", JSON_MODELS);
+ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v3", JSON_HOST);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v4", JSON_MODELS);
DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST);
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
new file mode 100644
index 0000000000..d9538892eb
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
@@ -0,0 +1,5 @@
+<!-- Features disabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x0804c1fc' edx='0xb0600000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
new file mode 100644
index 0000000000..fcc1e84686
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
@@ -0,0 +1,8 @@
+<!-- Features enabled by QEMU -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x97ba2203' edx='0x0f8bfbff'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000004'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000002' ecx='0x00000000' edx='0x8c000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000001'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000001' edx='0x2c100800'/>
+</cpudata>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
new file mode 100644
index 0000000000..e507642df1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
@@ -0,0 +1,29 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>SandyBridge-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
+ <feature policy='require' name='ds'/>
+ <feature policy='require' name='acpi'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='ht'/>
+ <feature policy='require' name='tm'/>
+ <feature policy='require' name='pbe'/>
+ <feature policy='require' name='dtes64'/>
+ <feature policy='require' name='monitor'/>
+ <feature policy='require' name='ds_cpl'/>
+ <feature policy='require' name='vmx'/>
+ <feature policy='require' name='smx'/>
+ <feature policy='require' name='est'/>
+ <feature policy='require' name='tm2'/>
+ <feature policy='require' name='xtpr'/>
+ <feature policy='require' name='pdcm'/>
+ <feature policy='require' name='pcid'/>
+ <feature policy='require' name='dca'/>
+ <feature policy='require' name='osxsave'/>
+ <feature policy='require' name='arat'/>
+ <feature policy='require' name='stibp'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='xsaveopt'/>
+ <feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
new file mode 100644
index 0000000000..80ca6c343f
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
@@ -0,0 +1,30 @@
+<cpu>
+ <arch>x86_64</arch>
+ <model>SandyBridge-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature name='vme'/>
+ <feature name='ds'/>
+ <feature name='acpi'/>
+ <feature name='ss'/>
+ <feature name='ht'/>
+ <feature name='tm'/>
+ <feature name='pbe'/>
+ <feature name='dtes64'/>
+ <feature name='monitor'/>
+ <feature name='ds_cpl'/>
+ <feature name='vmx'/>
+ <feature name='smx'/>
+ <feature name='est'/>
+ <feature name='tm2'/>
+ <feature name='xtpr'/>
+ <feature name='pdcm'/>
+ <feature name='pcid'/>
+ <feature name='dca'/>
+ <feature name='osxsave'/>
+ <feature name='arat'/>
+ <feature name='stibp'/>
+ <feature name='ssbd'/>
+ <feature name='xsaveopt'/>
+ <feature name='pdpe1gb'/>
+ <feature name='invtsc'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
new file mode 100644
index 0000000000..bf587d3ffc
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
@@ -0,0 +1,14 @@
+<cpu mode='custom' match='exact'>
+ <model fallback='forbid'>SandyBridge-IBRS</model>
+ <vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
+ <feature policy='require' name='ss'/>
+ <feature policy='require' name='pcid'/>
+ <feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='arat'/>
+ <feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='stibp'/>
+ <feature policy='require' name='ssbd'/>
+ <feature policy='require' name='xsaveopt'/>
+ <feature policy='require' name='pdpe1gb'/>
+</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
new file mode 100644
index 0000000000..a7a8542203
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
@@ -0,0 +1,931 @@
+{
+ "return": {
+ "model": {
+ "name": "base",
+ "props": {
+ "phys-bits": 0,
+ "core-id": -1,
+ "xlevel": 2147483656,
+ "cmov": true,
+ "ia64": false,
+ "aes": true,
+ "mmx": true,
+ "rdpid": false,
+ "arat": true,
+ "gfni": false,
+ "pause-filter": false,
+ "xsavec": false,
+ "intel-pt": false,
+ "osxsave": false,
+ "hv-frequencies": false,
+ "tsc-frequency": 0,
+ "xd": true,
+ "hv-vendor-id": "",
+ "kvm-asyncpf": true,
+ "kvm_asyncpf": true,
+ "perfctr_core": false,
+ "perfctr-core": false,
+ "mpx": false,
+ "pbe": false,
+ "decodeassists": false,
+ "avx512cd": false,
+ "sse4_1": true,
+ "sse4.1": true,
+ "sse4-1": true,
+ "family": 6,
+ "legacy-cache": true,
+ "vmware-cpuid-freq": true,
+ "avx512f": false,
+ "msr": true,
+ "mce": true,
+ "mca": true,
+ "hv-runtime": false,
+ "xcrypt": false,
+ "thread-id": -1,
+ "min-level": 13,
+ "xgetbv1": false,
+ "cid": false,
+ "hv-relaxed": false,
+ "hv-crash": false,
+ "ds": false,
+ "fxsr": true,
+ "xsaveopt": true,
+ "xtpr": false,
+ "avx512vl": false,
+ "avx512-vpopcntdq": false,
+ "phe": false,
+ "extapic": false,
+ "3dnowprefetch": false,
+ "avx512vbmi2": false,
+ "cr8legacy": false,
+ "stibp": true,
+ "cpuid-0xb": true,
+ "xcrypt-en": false,
+ "kvm_pv_eoi": true,
+ "apic-id": 4294967295,
+ "pn": false,
+ "dca": false,
+ "vendor": "GenuineIntel",
+ "pku": false,
+ "smx": false,
+ "cmp_legacy": false,
+ "cmp-legacy": false,
+ "node-id": -1,
+ "avx512-4fmaps": false,
+ "vmcb_clean": false,
+ "vmcb-clean": false,
+ "3dnowext": false,
+ "hle": false,
+ "npt": false,
+ "memory": "/machine/unattached/system[0]",
+ "clwb": false,
+ "lbrv": false,
+ "adx": false,
+ "ss": true,
+ "pni": true,
+ "svm_lock": false,
+ "svm-lock": false,
+ "pfthreshold": false,
+ "smep": false,
+ "smap": false,
+ "x2apic": true,
+ "avx512vbmi": false,
+ "avx512vnni": false,
+ "hv-stimer": false,
+ "i64": true,
+ "flushbyasid": false,
+ "f16c": false,
+ "ace2-en": false,
+ "pat": true,
+ "pae": true,
+ "sse": true,
+ "phe-en": false,
+ "kvm_nopiodelay": true,
+ "kvm-nopiodelay": true,
+ "tm": false,
+ "kvmclock-stable-bit": true,
+ "hypervisor": true,
+ "socket-id": -1,
+ "pcommit": false,
+ "syscall": true,
+ "level": 13,
+ "avx512dq": false,
+ "svm": false,
+ "full-cpuid-auto-level": true,
+ "hv-reset": false,
+ "invtsc": false,
+ "sse3": true,
+ "sse2": true,
+ "ssbd": true,
+ "est": false,
+ "avx512ifma": false,
+ "tm2": false,
+ "kvm-pv-eoi": true,
+ "cx8": true,
+ "kvm_mmu": false,
+ "kvm-mmu": false,
+ "sse4_2": true,
+ "sse4.2": true,
+ "sse4-2": true,
+ "pge": true,
+ "fill-mtrr-mask": true,
+ "avx512bitalg": false,
+ "nodeid_msr": false,
+ "pdcm": false,
+ "movbe": false,
+ "model": 45,
+ "nrip_save": false,
+ "nrip-save": false,
+ "kvm_pv_unhalt": true,
+ "ssse3": true,
+ "sse4a": false,
+ "invpcid": false,
+ "pdpe1gb": true,
+ "tsc-deadline": true,
+ "fma": false,
+ "cx16": true,
+ "de": true,
+ "enforce": false,
+ "stepping": 7,
+ "xsave": true,
+ "clflush": true,
+ "skinit": false,
+ "tsc": true,
+ "tce": false,
+ "fpu": true,
+ "ibs": false,
+ "ds_cpl": false,
+ "ds-cpl": false,
+ "host-phys-bits": true,
+ "fma4": false,
+ "la57": false,
+ "osvw": false,
+ "check": true,
+ "hv-spinlocks": -1,
+ "pmu": false,
+ "pmm": false,
+ "apic": true,
+ "spec-ctrl": true,
+ "min-xlevel2": 0,
+ "tsc-adjust": true,
+ "tsc_adjust": true,
+ "kvm-steal-time": true,
+ "kvm_steal_time": true,
+ "kvmclock": true,
+ "l3-cache": true,
+ "lwp": false,
+ "ibpb": false,
+ "xop": false,
+ "avx": true,
+ "ospke": false,
+ "ace2": false,
+ "avx512bw": false,
+ "acpi": false,
+ "hv-vapic": false,
+ "fsgsbase": false,
+ "ht": false,
+ "nx": true,
+ "pclmulqdq": true,
+ "mmxext": false,
+ "vaes": false,
+ "popcnt": true,
+ "xsaves": false,
+ "tcg-cpuid": true,
+ "lm": true,
+ "umip": false,
+ "pse": true,
+ "avx2": false,
+ "sep": true,
+ "pclmuldq": true,
+ "virt-ssbd": false,
+ "x-hv-max-vps": -1,
+ "nodeid-msr": false,
+ "kvm": true,
+ "misalignsse": false,
+ "min-xlevel": 2147483656,
+ "kvm-pv-unhalt": true,
+ "bmi2": false,
+ "bmi1": false,
+ "realized": false,
+ "tsc_scale": false,
+ "tsc-scale": false,
+ "topoext": false,
+ "hv-vpindex": false,
+ "xlevel2": 0,
+ "clflushopt": false,
+ "kvm-no-smi-migration": false,
+ "monitor": false,
+ "avx512er": false,
+ "pmm-en": false,
+ "pcid": true,
+ "3dnow": false,
+ "erms": false,
+ "lahf-lm": true,
+ "lahf_lm": true,
+ "vpclmulqdq": false,
+ "fxsr-opt": false,
+ "hv-synic": false,
+ "xstore": false,
+ "fxsr_opt": false,
+ "kvm-hint-dedicated": false,
+ "rtm": false,
+ "lmce": true,
+ "hv-time": false,
+ "perfctr-nb": false,
+ "perfctr_nb": false,
+ "ffxsr": false,
+ "rdrand": false,
+ "rdseed": false,
+ "avx512-4vnniw": false,
+ "vmx": false,
+ "vme": true,
+ "dtes64": false,
+ "mtrr": true,
+ "rdtscp": true,
+ "pse36": true,
+ "kvm-pv-tlb-flush": false,
+ "tbm": false,
+ "wdt": false,
+ "pause_filter": false,
+ "sha-ni": false,
+ "model-id": " Intel(R) Xeon(R) CPU E5-2650 0 @
2.00GHz",
+ "abm": false,
+ "avx512pf": false,
+ "xstore-en": false
+ }
+ }
+ },
+ "id": "model-expansion"
+}
+
+{
+ "return": [
+ {
+ "name": "max",
+ "typename": "max-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "host",
+ "typename": "host-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": false
+ },
+ {
+ "name": "base",
+ "typename": "base-x86_64-cpu",
+ "unavailable-features": [],
+ "static": true,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu64",
+ "typename": "qemu64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "qemu32",
+ "typename": "qemu32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "phenom",
+ "typename": "phenom-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "fxsr-opt",
+ "3dnowext",
+ "3dnow",
+ "abm",
+ "sse4a",
+ "npt"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium3",
+ "typename": "pentium3-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium2",
+ "typename": "pentium2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "pentium",
+ "typename": "pentium-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "n270",
+ "typename": "n270-x86_64-cpu",
+ "unavailable-features": [
+ "movbe"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm64",
+ "typename": "kvm64-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "kvm32",
+ "typename": "kvm32-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "cpu64-rhel6",
+ "typename": "cpu64-rhel6-x86_64-cpu",
+ "unavailable-features": [
+ "abm",
+ "sse4a"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "coreduo",
+ "typename": "coreduo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "core2duo",
+ "typename": "core2duo-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "athlon",
+ "typename": "athlon-x86_64-cpu",
+ "unavailable-features": [
+ "mmxext",
+ "3dnowext",
+ "3dnow"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere",
+ "typename": "Westmere-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Westmere-IBRS",
+ "typename": "Westmere-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server",
+ "typename": "Skylake-Server-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "avx512f",
+ "avx512dq",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "abm",
+ "3dnowprefetch",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx",
+ "avx512f",
+ "avx512f",
+ "avx512f"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Server-IBRS",
+ "typename": "Skylake-Server-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "avx512f",
+ "avx512dq",
+ "rdseed",
+ "adx",
+ "smap",
+ "clwb",
+ "avx512cd",
+ "avx512bw",
+ "avx512vl",
+ "abm",
+ "3dnowprefetch",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx",
+ "avx512f",
+ "avx512f",
+ "avx512f"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client",
+ "typename": "Skylake-Client-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Skylake-Client-IBRS",
+ "typename": "Skylake-Client-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "mpx",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch",
+ "xsavec",
+ "xgetbv1",
+ "mpx",
+ "mpx"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge",
+ "typename": "SandyBridge-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "SandyBridge-IBRS",
+ "typename": "SandyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Penryn",
+ "typename": "Penryn-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G5",
+ "typename": "Opteron_G5-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "f16c",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "xop",
+ "fma4",
+ "tbm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G4",
+ "typename": "Opteron_G4-x86_64-cpu",
+ "unavailable-features": [
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "xop",
+ "fma4"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G3",
+ "typename": "Opteron_G3-x86_64-cpu",
+ "unavailable-features": [
+ "abm",
+ "sse4a",
+ "misalignsse"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G2",
+ "typename": "Opteron_G2-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Opteron_G1",
+ "typename": "Opteron_G1-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem",
+ "typename": "Nehalem-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Nehalem-IBRS",
+ "typename": "Nehalem-IBRS-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge",
+ "typename": "IvyBridge-x86_64-cpu",
+ "unavailable-features": [
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "smep",
+ "erms"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "IvyBridge-IBRS",
+ "typename": "IvyBridge-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "smep",
+ "erms"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell",
+ "typename": "Haswell-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "abm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX",
+ "typename": "Haswell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "abm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-noTSX-IBRS",
+ "typename": "Haswell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "abm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Haswell-IBRS",
+ "typename": "Haswell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "abm"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC",
+ "typename": "EPYC-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "cr8legacy",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "osvw",
+ "xsavec",
+ "xgetbv1"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "EPYC-IBPB",
+ "typename": "EPYC-IBPB-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "rdseed",
+ "adx",
+ "smap",
+ "clflushopt",
+ "sha-ni",
+ "mmxext",
+ "fxsr-opt",
+ "cr8legacy",
+ "abm",
+ "sse4a",
+ "misalignsse",
+ "3dnowprefetch",
+ "osvw",
+ "ibpb",
+ "xsavec",
+ "xgetbv1"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Conroe",
+ "typename": "Conroe-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell",
+ "typename": "Broadwell-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX",
+ "typename": "Broadwell-noTSX-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-noTSX-IBRS",
+ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "Broadwell-IBRS",
+ "typename": "Broadwell-IBRS-x86_64-cpu",
+ "unavailable-features": [
+ "fma",
+ "movbe",
+ "f16c",
+ "rdrand",
+ "fsgsbase",
+ "bmi1",
+ "hle",
+ "avx2",
+ "smep",
+ "bmi2",
+ "erms",
+ "invpcid",
+ "rtm",
+ "rdseed",
+ "adx",
+ "smap",
+ "abm",
+ "3dnowprefetch"
+ ],
+ "static": false,
+ "migration-safe": true
+ },
+ {
+ "name": "486",
+ "typename": "486-x86_64-cpu",
+ "unavailable-features": [],
+ "static": false,
+ "migration-safe": true
+ }
+ ],
+ "id": "definitions"
+}
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
new file mode 100644
index 0000000000..b7ce0631ca
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
@@ -0,0 +1,34 @@
+<!-- Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz -->
+<cpudata arch='x86'>
+ <cpuid eax_in='0x00000000' ecx_in='0x00' eax='0x0000000d'
ebx='0x756e6547' ecx='0x6c65746e' edx='0x49656e69'/>
+ <cpuid eax_in='0x00000001' ecx_in='0x00' eax='0x000206d7'
ebx='0x05200800' ecx='0x1fbee3ff' edx='0xbfebfbff'/>
+ <cpuid eax_in='0x00000002' ecx_in='0x00' eax='0x76035a01'
ebx='0x00f0b2ff' ecx='0x00000000' edx='0x00ca0000'/>
+ <cpuid eax_in='0x00000003' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x00' eax='0x3c004121'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x01' eax='0x3c004122'
ebx='0x01c0003f' ecx='0x0000003f' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x02' eax='0x3c004143'
ebx='0x01c0003f' ecx='0x000001ff' edx='0x00000000'/>
+ <cpuid eax_in='0x00000004' ecx_in='0x03' eax='0x3c07c163'
ebx='0x04c0003f' ecx='0x00003fff' edx='0x00000006'/>
+ <cpuid eax_in='0x00000005' ecx_in='0x00' eax='0x00000040'
ebx='0x00000040' ecx='0x00000003' edx='0x00021120'/>
+ <cpuid eax_in='0x00000006' ecx_in='0x00' eax='0x00000077'
ebx='0x00000002' ecx='0x00000009' edx='0x00000000'/>
+ <cpuid eax_in='0x00000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x9c000000'/>
+ <cpuid eax_in='0x00000008' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x00000009' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000a' ecx_in='0x00' eax='0x07300403'
ebx='0x00000000' ecx='0x00000000' edx='0x00000603'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x00' eax='0x00000001'
ebx='0x00000002' ecx='0x00000100' edx='0x00000005'/>
+ <cpuid eax_in='0x0000000b' ecx_in='0x01' eax='0x00000005'
ebx='0x00000010' ecx='0x00000201' edx='0x00000005'/>
+ <cpuid eax_in='0x0000000c' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x00' eax='0x00000007'
ebx='0x00000340' ecx='0x00000340' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x01' eax='0x00000001'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x0000000d' ecx_in='0x02' eax='0x00000100'
ebx='0x00000240' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000000' ecx_in='0x00' eax='0x80000008'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000001' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000001' edx='0x2c100800'/>
+ <cpuid eax_in='0x80000002' ecx_in='0x00' eax='0x20202020'
ebx='0x49202020' ecx='0x6c65746e' edx='0x20295228'/>
+ <cpuid eax_in='0x80000003' ecx_in='0x00' eax='0x6e6f6558'
ebx='0x20295228' ecx='0x20555043' edx='0x322d3545'/>
+ <cpuid eax_in='0x80000004' ecx_in='0x00' eax='0x20303536'
ebx='0x20402030' ecx='0x30302e32' edx='0x007a4847'/>
+ <cpuid eax_in='0x80000005' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80000006' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x01006040' edx='0x00000000'/>
+ <cpuid eax_in='0x80000007' ecx_in='0x00' eax='0x00000000'
ebx='0x00000000' ecx='0x00000000' edx='0x00000100'/>
+ <cpuid eax_in='0x80000008' ecx_in='0x00' eax='0x0000302e'
ebx='0x00000000' ecx='0x00000000' edx='0x00000000'/>
+ <cpuid eax_in='0x80860000' ecx_in='0x00' eax='0x00000007'
ebx='0x00000340' ecx='0x00000340' edx='0x00000000'/>
+ <cpuid eax_in='0xc0000000' ecx_in='0x00' eax='0x00000007'
ebx='0x00000340' ecx='0x00000340' edx='0x00000000'/>
+</cpudata>
--
2.21.0
10:41 p.m.
New subject: [libvirt] [PATCH 05/26] cputest: Add data for Intel(R) Xeon(R) CPU E5-2650
On Wed, Feb 27, 2019 at 02:28:55PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 1 +
.../x86_64-cpuid-Xeon-E5-2650-disabled.xml | 5 +
.../x86_64-cpuid-Xeon-E5-2650-enabled.xml | 8 +
.../x86_64-cpuid-Xeon-E5-2650-guest.xml | 29 +
.../x86_64-cpuid-Xeon-E5-2650-host.xml | 30 +
.../x86_64-cpuid-Xeon-E5-2650-json.xml | 14 +
.../x86_64-cpuid-Xeon-E5-2650.json | 931 ++++++++++++++++++
.../cputestdata/x86_64-cpuid-Xeon-E5-2650.xml | 34 +
8 files changed, 1052 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 06/26] cpu_x86: Separate ancestor model parsing from x86ModelParse
The code is separated into a new x86ModelParseAncestor function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 65 +++++++++++++++++++++++++++--------------------
1 file changed, 38 insertions(+), 27 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index d3a88da21d..8a0ff50afe 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1150,6 +1150,42 @@ x86ModelCompare(virCPUx86ModelPtr model1,
}
+static int
+x86ModelParseAncestor(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt,
+ virCPUx86MapPtr map)
+{
+ VIR_AUTOFREE(char *) name = NULL;
+ virCPUx86ModelPtr ancestor;
+ int rc;
+
+ if ((rc = virXPathBoolean("boolean(./model)", ctxt)) <= 0)
+ return rc;
+
+ name = virXPathString("string(./model/@name)", ctxt);
+ if (!name) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Missing ancestor's name in CPU model %s"),
+ model->name);
+ return -1;
+ }
+
+ if (!(ancestor = x86ModelFind(map, name))) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Ancestor model %s not found for CPU model %s"),
+ name, model->name);
+ return -1;
+ }
+
+ model->vendor = ancestor->vendor;
+ model->signature = ancestor->signature;
+ if (x86DataCopy(&model->data, &ancestor->data) < 0)
+ return -1;
+
+ return 0;
+}
+
+
static int
x86ModelParse(xmlXPathContextPtr ctxt,
const char *name,
@@ -1169,33 +1205,8 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (VIR_STRDUP(model->name, name) < 0)
goto cleanup;
- if (virXPathNode("./model", ctxt)) {
- virCPUx86ModelPtr ancestor;
- char *anname;
-
- anname = virXPathString("string(./model/@name)", ctxt);
- if (!anname) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Missing ancestor's name in CPU model %s"),
- model->name);
- goto cleanup;
- }
-
- if (!(ancestor = x86ModelFind(map, anname))) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Ancestor model %s not found for CPU model %s"),
- anname, model->name);
- VIR_FREE(anname);
- goto cleanup;
- }
-
- VIR_FREE(anname);
-
- model->vendor = ancestor->vendor;
- model->signature = ancestor->signature;
- if (x86DataCopy(&model->data, &ancestor->data) < 0)
- goto cleanup;
- }
+ if (x86ModelParseAncestor(model, ctxt, map) < 0)
+ goto cleanup;
if (virXPathBoolean("boolean(./signature)", ctxt)) {
unsigned int sigFamily = 0;
--
2.21.0
8:05 p.m.
New subject: [libvirt] [PATCH 06/26] cpu_x86: Separate ancestor model parsing from x86ModelParse
On Wed, Feb 27, 2019 at 02:28:56PM +0100, Jiri Denemark wrote:
The code is separated into a new x86ModelParseAncestor function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 65 +++++++++++++++++++++++++++--------------------
1 file changed, 38 insertions(+), 27 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 07/26] cpu_x86: Separate signature parsing from x86ModelParse
The code is separated into a new x86ModelParseSignature function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 58 ++++++++++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 8a0ff50afe..163fcbf5ac 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1186,6 +1186,39 @@ x86ModelParseAncestor(virCPUx86ModelPtr model,
}
+static int
+x86ModelParseSignature(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt)
+{
+ int rc;
+
+ if (virXPathBoolean("boolean(./signature)", ctxt)) {
+ unsigned int sigFamily = 0;
+ unsigned int sigModel = 0;
+
+ rc = virXPathUInt("string(./signature/@family)", ctxt,
&sigFamily);
+ if (rc < 0 || sigFamily == 0) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Invalid CPU signature family in model %s"),
+ model->name);
+ return -1;
+ }
+
+ rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel);
+ if (rc < 0 || sigModel == 0) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Invalid CPU signature model in model %s"),
+ model->name);
+ return -1;
+ }
+
+ model->signature = x86MakeSignature(sigFamily, sigModel, 0);
+ }
+
+ return 0;
+}
+
+
static int
x86ModelParse(xmlXPathContextPtr ctxt,
const char *name,
@@ -1208,29 +1241,8 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (x86ModelParseAncestor(model, ctxt, map) < 0)
goto cleanup;
- if (virXPathBoolean("boolean(./signature)", ctxt)) {
- unsigned int sigFamily = 0;
- unsigned int sigModel = 0;
- int rc;
-
- rc = virXPathUInt("string(./signature/@family)", ctxt,
&sigFamily);
- if (rc < 0 || sigFamily == 0) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Invalid CPU signature family in model %s"),
- model->name);
- goto cleanup;
- }
-
- rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel);
- if (rc < 0 || sigModel == 0) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Invalid CPU signature model in model %s"),
- model->name);
- goto cleanup;
- }
-
- model->signature = x86MakeSignature(sigFamily, sigModel, 0);
- }
+ if (x86ModelParseSignature(model, ctxt) < 0)
+ goto cleanup;
if (virXPathBoolean("boolean(./vendor)", ctxt)) {
vendor = virXPathString("string(./vendor/@name)", ctxt);
--
2.21.0
8:24 p.m.
New subject: [libvirt] [PATCH 07/26] cpu_x86: Separate signature parsing from x86ModelParse
On Wed, Feb 27, 2019 at 02:28:57PM +0100, Jiri Denemark wrote:
The code is separated into a new x86ModelParseSignature function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 58 ++++++++++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 23 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 08/26] cpu_x86: Separate vendor parsing from x86ModelParse
The code is separated into a new x86ModelParseVendor function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 50 ++++++++++++++++++++++++++++++-----------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 163fcbf5ac..fcbc105218 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1219,6 +1219,36 @@ x86ModelParseSignature(virCPUx86ModelPtr model,
}
+static int
+x86ModelParseVendor(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt,
+ virCPUx86MapPtr map)
+{
+ VIR_AUTOFREE(char *) vendor = NULL;
+ int rc;
+
+ if ((rc = virXPathBoolean("boolean(./vendor)", ctxt)) <= 0)
+ return rc;
+
+ vendor = virXPathString("string(./vendor/@name)", ctxt);
+ if (!vendor) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Invalid vendor element in CPU model %s"),
+ model->name);
+ return -1;
+ }
+
+ if (!(model->vendor = x86VendorFind(map, vendor))) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Unknown vendor %s referenced by CPU model %s"),
+ vendor, model->name);
+ return -1;
+ }
+
+ return 0;
+}
+
+
static int
x86ModelParse(xmlXPathContextPtr ctxt,
const char *name,
@@ -1227,7 +1257,6 @@ x86ModelParse(xmlXPathContextPtr ctxt,
virCPUx86MapPtr map = data;
xmlNodePtr *nodes = NULL;
virCPUx86ModelPtr model;
- char *vendor = NULL;
size_t i;
int n;
int ret = -1;
@@ -1244,22 +1273,8 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (x86ModelParseSignature(model, ctxt) < 0)
goto cleanup;
- if (virXPathBoolean("boolean(./vendor)", ctxt)) {
- vendor = virXPathString("string(./vendor/@name)", ctxt);
- if (!vendor) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Invalid vendor element in CPU model %s"),
- model->name);
- goto cleanup;
- }
-
- if (!(model->vendor = x86VendorFind(map, vendor))) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Unknown vendor %s referenced by CPU model %s"),
- vendor, model->name);
- goto cleanup;
- }
- }
+ if (x86ModelParseVendor(model, ctxt, map) < 0)
+ goto cleanup;
n = virXPathNodeSet("./feature", ctxt, &nodes);
if (n < 0)
@@ -1295,7 +1310,6 @@ x86ModelParse(xmlXPathContextPtr ctxt,
cleanup:
x86ModelFree(model);
- VIR_FREE(vendor);
VIR_FREE(nodes);
return ret;
}
--
2.21.0
8:35 p.m.
New subject: [libvirt] [PATCH 08/26] cpu_x86: Separate vendor parsing from x86ModelParse
On Wed, Feb 27, 2019 at 02:28:58PM +0100, Jiri Denemark wrote:
The code is separated into a new x86ModelParseVendor function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 50 ++++++++++++++++++++++++++++++-----------------
1 file changed, 32 insertions(+), 18 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:28 p.m.
New subject: [libvirt] [PATCH 09/26] cpu_x86: Separate feature list parsing from x86ModelParse
The code is separated into a new x86ModelParseFeatures function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 68 +++++++++++++++++++++++++++--------------------
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index fcbc105218..82f7bcbb45 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1249,16 +1249,51 @@ x86ModelParseVendor(virCPUx86ModelPtr model,
}
+static int
+x86ModelParseFeatures(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt,
+ virCPUx86MapPtr map)
+{
+ VIR_AUTOFREE(xmlNodePtr *) nodes = NULL;
+ size_t i;
+ int n;
+
+ if ((n = virXPathNodeSet("./feature", ctxt, &nodes)) <= 0)
+ return n;
+
+ for (i = 0; i < n; i++) {
+ VIR_AUTOFREE(char *) ftname = NULL;
+ virCPUx86FeaturePtr feature;
+
+ if (!(ftname = virXMLPropString(nodes[i], "name"))) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Missing feature name for CPU model %s"),
+ model->name);
+ return -1;
+ }
+
+ if (!(feature = x86FeatureFind(map, ftname))) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Feature %s required by CPU model %s not found"),
+ ftname, model->name);
+ return -1;
+ }
+
+ if (x86DataAdd(&model->data, &feature->data))
+ return -1;
+ }
+
+ return 0;
+}
+
+
static int
x86ModelParse(xmlXPathContextPtr ctxt,
const char *name,
void *data)
{
virCPUx86MapPtr map = data;
- xmlNodePtr *nodes = NULL;
virCPUx86ModelPtr model;
- size_t i;
- int n;
int ret = -1;
if (!(model = x86ModelNew()))
@@ -1276,33 +1311,9 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (x86ModelParseVendor(model, ctxt, map) < 0)
goto cleanup;
- n = virXPathNodeSet("./feature", ctxt, &nodes);
- if (n < 0)
+ if (x86ModelParseFeatures(model, ctxt, map) < 0)
goto cleanup;
- for (i = 0; i < n; i++) {
- virCPUx86FeaturePtr feature;
- char *ftname;
-
- if (!(ftname = virXMLPropString(nodes[i], "name"))) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Missing feature name for CPU model %s"),
model->name);
- goto cleanup;
- }
-
- if (!(feature = x86FeatureFind(map, ftname))) {
- virReportError(VIR_ERR_INTERNAL_ERROR,
- _("Feature %s required by CPU model %s not found"),
- ftname, model->name);
- VIR_FREE(ftname);
- goto cleanup;
- }
- VIR_FREE(ftname);
-
- if (x86DataAdd(&model->data, &feature->data))
- goto cleanup;
- }
-
if (VIR_APPEND_ELEMENT(map->models, map->nmodels, model) < 0)
goto cleanup;
@@ -1310,7 +1321,6 @@ x86ModelParse(xmlXPathContextPtr ctxt,
cleanup:
x86ModelFree(model);
- VIR_FREE(nodes);
return ret;
}
--
2.21.0
8:38 p.m.
New subject: [libvirt] [PATCH 09/26] cpu_x86: Separate feature list parsing from x86ModelParse
On Wed, Feb 27, 2019 at 02:28:59PM +0100, Jiri Denemark wrote:
The code is separated into a new x86ModelParseFeatures function.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 68 +++++++++++++++++++++++++++--------------------
1 file changed, 39 insertions(+), 29 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 10/26] cpu_x86: Make sure CPU model names are unique in cpu_map
Having multiple CPU model definitions with the same name could result in
unexpected behavior.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 82f7bcbb45..c2f22f399f 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -1293,9 +1293,15 @@ x86ModelParse(xmlXPathContextPtr ctxt,
void *data)
{
virCPUx86MapPtr map = data;
- virCPUx86ModelPtr model;
+ virCPUx86ModelPtr model = NULL;
int ret = -1;
+ if (x86ModelFind(map, name)) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("Multiple definitions of CPU model '%s'"),
name);
+ goto cleanup;
+ }
+
if (!(model = x86ModelNew()))
goto cleanup;
--
2.21.0
8:41 p.m.
New subject: [libvirt] [PATCH 10/26] cpu_x86: Make sure CPU model names are unique in cpu_map
On Wed, Feb 27, 2019 at 02:29:00PM +0100, Jiri Denemark wrote:
Having multiple CPU model definitions with the same name could result
in
unexpected behavior.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 11/26] cpu_x86: Allow multiple signatures for a CPU model
CPU signatures in the cpu_map serve as a hint for CPUID to CPU model
matching algorithm. If the CPU signatures matches any CPU model in the
cpu_map, this model will be the preferred one.
This works out well and solved several mismatches, but in real world
CPUs which should match a single CPU model may be produced with several
different signatures. For example, low voltage Broadwell CPUs for
laptops and Broadwell CPUs for servers differ in CPU model numbers while
we should detect them all as Broadwell CPU model.
This patch adds support for storing several signatures for a single CPU
model to make this hint useful for more CPUs. Later commits will provide
additional signatures for existing CPU models, which will correct some
results in our CPU test suite.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 104 ++++++++++++++++++++++++++++++++++++++--------
1 file changed, 86 insertions(+), 18 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index c2f22f399f..89303400af 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -147,7 +147,8 @@ typedef virCPUx86Model *virCPUx86ModelPtr;
struct _virCPUx86Model {
char *name;
virCPUx86VendorPtr vendor;
- uint32_t signature;
+ size_t nsignatures;
+ uint32_t *signatures;
virCPUx86Data data;
};
@@ -974,11 +975,29 @@ x86ModelFree(virCPUx86ModelPtr model)
return;
VIR_FREE(model->name);
+ VIR_FREE(model->signatures);
virCPUx86DataClear(&model->data);
VIR_FREE(model);
}
+static int
+x86ModelCopySignatures(virCPUx86ModelPtr dst,
+ virCPUx86ModelPtr src)
+{
+ size_t i;
+
+ if (VIR_ALLOC_N(dst->signatures, src->nsignatures) < 0)
+ return -1;
+
+ dst->nsignatures = src->nsignatures;
+ for (i = 0; i < src->nsignatures; i++)
+ dst->signatures[i] = src->signatures[i];
+
+ return 0;
+}
+
+
static virCPUx86ModelPtr
x86ModelCopy(virCPUx86ModelPtr model)
{
@@ -986,13 +1005,13 @@ x86ModelCopy(virCPUx86ModelPtr model)
if (VIR_ALLOC(copy) < 0 ||
VIR_STRDUP(copy->name, model->name) < 0 ||
+ x86ModelCopySignatures(copy, model) < 0 ||
x86DataCopy(©->data, &model->data) < 0) {
x86ModelFree(copy);
return NULL;
}
copy->vendor = model->vendor;
- copy->signature = model->signature;
return copy;
}
@@ -1178,8 +1197,8 @@ x86ModelParseAncestor(virCPUx86ModelPtr model,
}
model->vendor = ancestor->vendor;
- model->signature = ancestor->signature;
- if (x86DataCopy(&model->data, &ancestor->data) < 0)
+ if (x86ModelCopySignatures(model, ancestor) < 0 ||
+ x86DataCopy(&model->data, &ancestor->data) < 0)
return -1;
return 0;
@@ -1187,16 +1206,32 @@ x86ModelParseAncestor(virCPUx86ModelPtr model,
static int
-x86ModelParseSignature(virCPUx86ModelPtr model,
- xmlXPathContextPtr ctxt)
+x86ModelParseSignatures(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt)
{
- int rc;
+ VIR_AUTOFREE(xmlNodePtr *) nodes = NULL;
+ xmlNodePtr root = ctxt->node;
+ size_t i;
+ int n;
- if (virXPathBoolean("boolean(./signature)", ctxt)) {
+ if ((n = virXPathNodeSet("./signature", ctxt, &nodes)) <= 0)
+ return n;
+
+ /* Remove inherited signatures. */
+ VIR_FREE(model->signatures);
+
+ model->nsignatures = n;
+ if (VIR_ALLOC_N(model->signatures, n) < 0)
+ return -1;
+
+ for (i = 0; i < n; i++) {
unsigned int sigFamily = 0;
unsigned int sigModel = 0;
+ int rc;
- rc = virXPathUInt("string(./signature/@family)", ctxt,
&sigFamily);
+ ctxt->node = nodes[i];
+
+ rc = virXPathUInt("string(@family)", ctxt, &sigFamily);
if (rc < 0 || sigFamily == 0) {
virReportError(VIR_ERR_INTERNAL_ERROR,
_("Invalid CPU signature family in model %s"),
@@ -1204,7 +1239,7 @@ x86ModelParseSignature(virCPUx86ModelPtr model,
return -1;
}
- rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel);
+ rc = virXPathUInt("string(@model)", ctxt, &sigModel);
if (rc < 0 || sigModel == 0) {
virReportError(VIR_ERR_INTERNAL_ERROR,
_("Invalid CPU signature model in model %s"),
@@ -1212,9 +1247,10 @@ x86ModelParseSignature(virCPUx86ModelPtr model,
return -1;
}
- model->signature = x86MakeSignature(sigFamily, sigModel, 0);
+ model->signatures[i] = x86MakeSignature(sigFamily, sigModel, 0);
}
+ ctxt->node = root;
return 0;
}
@@ -1311,7 +1347,7 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (x86ModelParseAncestor(model, ctxt, map) < 0)
goto cleanup;
- if (x86ModelParseSignature(model, ctxt) < 0)
+ if (x86ModelParseSignatures(model, ctxt) < 0)
goto cleanup;
if (x86ModelParseVendor(model, ctxt, map) < 0)
@@ -1615,7 +1651,8 @@ x86Compute(virCPUDefPtr host,
&host_model->vendor->cpuid) < 0)
goto error;
- if (x86DataAddSignature(&guest_model->data, host_model->signature) <
0)
+ if (host_model->signatures &&
+ x86DataAddSignature(&guest_model->data, *host_model->signatures)
< 0)
goto error;
if (cpu->type == VIR_CPU_TYPE_GUEST
@@ -1721,6 +1758,21 @@ virCPUx86Compare(virCPUDefPtr host,
}
+static bool
+x86ModelHasSignature(virCPUx86ModelPtr model,
+ uint32_t signature)
+{
+ size_t i;
+
+ for (i = 0; i < model->nsignatures; i++) {
+ if (model->signatures[i] == signature)
+ return true;
+ }
+
+ return false;
+}
+
+
/*
* Checks whether a candidate model is a better fit for the CPU data than the
* current model.
@@ -1762,8 +1814,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current,
* consider candidates with matching family/model.
*/
if (signature &&
- current->signature == signature &&
- candidate->signature != signature) {
+ x86ModelHasSignature(current, signature) &&
+ !x86ModelHasSignature(candidate, signature)) {
VIR_DEBUG("%s differs in signature from matching %s",
cpuCandidate->model, cpuCurrent->model);
return 0;
@@ -1779,8 +1831,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current,
* result in longer list of features.
*/
if (signature &&
- candidate->signature == signature &&
- current->signature != signature) {
+ x86ModelHasSignature(candidate, signature) &&
+ !x86ModelHasSignature(current, signature)) {
VIR_DEBUG("%s provides matching signature", cpuCandidate->model);
return 1;
}
@@ -1844,6 +1896,8 @@ x86Decode(virCPUDefPtr cpu,
virCPUx86Data features = VIR_CPU_X86_DATA_INIT;
virCPUx86VendorPtr vendor;
virDomainCapsCPUModelPtr hvModel = NULL;
+ virBuffer sigBuf = VIR_BUFFER_INITIALIZER;
+ char *sigs = NULL;
uint32_t signature;
ssize_t i;
int rc;
@@ -1936,6 +1990,18 @@ x86Decode(virCPUDefPtr cpu,
if (vendor && VIR_STRDUP(cpu->vendor, vendor->name) < 0)
goto cleanup;
+ for (i = 0; i < model->nsignatures; i++)
+ virBufferAsprintf(&sigBuf, "%06x,", model->signatures[i]);
+
+ virBufferTrim(&sigBuf, ",", -1);
+ if (virBufferCheckError(&sigBuf) < 0)
+ goto cleanup;
+
+ sigs = virBufferContentAndReset(&sigBuf);
+
+ VIR_DEBUG("Using CPU model %s (signatures %s) for CPU with signature
%06lx",
+ model->name, sigs, (long)signature);
+
VIR_STEAL_PTR(cpu->model, cpuModel->model);
VIR_STEAL_PTR(cpu->features, cpuModel->features);
cpu->nfeatures = cpuModel->nfeatures;
@@ -1950,6 +2016,7 @@ x86Decode(virCPUDefPtr cpu,
virCPUx86DataClear(&data);
virCPUx86DataClear(©);
virCPUx86DataClear(&features);
+ VIR_FREE(sigs);
return ret;
}
@@ -2848,7 +2915,8 @@ virCPUx86Translate(virCPUDefPtr cpu,
virCPUx86DataAddCPUIDInt(&model->data, &model->vendor->cpuid)
< 0)
goto cleanup;
- if (x86DataAddSignature(&model->data, model->signature) < 0)
+ if (model->signatures &&
+ x86DataAddSignature(&model->data, model->signatures[0]) < 0)
goto cleanup;
if (!(translated = virCPUDefCopyWithoutModel(cpu)))
--
2.21.0
11:27 p.m.
New subject: [libvirt] [PATCH 11/26] cpu_x86: Allow multiple signatures for a CPU model
On Wed, Feb 27, 2019 at 02:29:01PM +0100, Jiri Denemark wrote:
CPU signatures in the cpu_map serve as a hint for CPUID to CPU model
matching algorithm. If the CPU signatures matches any CPU model in the
cpu_map, this model will be the preferred one.
This works out well and solved several mismatches, but in real world
CPUs which should match a single CPU model may be produced with several
different signatures. For example, low voltage Broadwell CPUs for
laptops and Broadwell CPUs for servers differ in CPU model numbers while
we should detect them all as Broadwell CPU model.
This patch adds support for storing several signatures for a single CPU
model to make this hint useful for more CPUs. Later commits will provide
additional signatures for existing CPU models, which will correct some
results in our CPU test suite.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 104 ++++++++++++++++++++++++++++++++++++++--------
1 file changed, 86 insertions(+), 18 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index c2f22f399f..89303400af 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -974,11 +975,29 @@ x86ModelFree(virCPUx86ModelPtr model)
return;
VIR_FREE(model->name);
+ VIR_FREE(model->signatures);
virCPUx86DataClear(&model->data);
VIR_FREE(model);
}
+static int
+x86ModelCopySignatures(virCPUx86ModelPtr dst,
+ virCPUx86ModelPtr src)
+{
This would have been easier to read split into several patches,
e.g. adding this helper that will just:
return dst->signature == src->signature;
Although there are not that many users of this function anyway.
+ size_t i;
+
+ if (VIR_ALLOC_N(dst->signatures, src->nsignatures) < 0)
+ return -1;
+
+ dst->nsignatures = src->nsignatures;
+ for (i = 0; i < src->nsignatures; i++)
+ dst->signatures[i] = src->signatures[i];
+
+ return 0;
+}
+
+
static virCPUx86ModelPtr
x86ModelCopy(virCPUx86ModelPtr model)
{
@@ -986,13 +1005,13 @@ x86ModelCopy(virCPUx86ModelPtr model)
if (VIR_ALLOC(copy) < 0 ||
VIR_STRDUP(copy->name, model->name) < 0 ||
+ x86ModelCopySignatures(copy, model) < 0 ||
x86DataCopy(©->data, &model->data) < 0) {
x86ModelFree(copy);
return NULL;
}
copy->vendor = model->vendor;
- copy->signature = model->signature;
return copy;
}
@@ -1178,8 +1197,8 @@ x86ModelParseAncestor(virCPUx86ModelPtr model,
}
model->vendor = ancestor->vendor;
- model->signature = ancestor->signature;
- if (x86DataCopy(&model->data, &ancestor->data) < 0)
+ if (x86ModelCopySignatures(model, ancestor) < 0 ||
+ x86DataCopy(&model->data, &ancestor->data) < 0)
return -1;
return 0;
@@ -1187,16 +1206,32 @@ x86ModelParseAncestor(virCPUx86ModelPtr model,
static int
-x86ModelParseSignature(virCPUx86ModelPtr model,
- xmlXPathContextPtr ctxt)
+x86ModelParseSignatures(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt)
{
- int rc;
This variable was added to this place just a few commits above.
+ VIR_AUTOFREE(xmlNodePtr *) nodes = NULL;
+ xmlNodePtr root = ctxt->node;
+ size_t i;
+ int n;
- if (virXPathBoolean("boolean(./signature)", ctxt)) {
+ if ((n = virXPathNodeSet("./signature", ctxt, &nodes)) <= 0)
+ return n;
+
+ /* Remove inherited signatures. */
+ VIR_FREE(model->signatures);
+
+ model->nsignatures = n;
+ if (VIR_ALLOC_N(model->signatures, n) < 0)
+ return -1;
+
+ for (i = 0; i < n; i++) {
unsigned int sigFamily = 0;
unsigned int sigModel = 0;
+ int rc;
- rc = virXPathUInt("string(./signature/@family)", ctxt,
&sigFamily);
+ ctxt->node = nodes[i];
+
+ rc = virXPathUInt("string(@family)", ctxt, &sigFamily);
The ctxt->node and XPath changes could have been separate.
if (rc < 0 || sigFamily == 0) {
virReportError(VIR_ERR_INTERNAL_ERROR,
_("Invalid CPU signature family in model %s"),
@@ -1204,7 +1239,7 @@ x86ModelParseSignature(virCPUx86ModelPtr model,
return -1;
}
- rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel);
+ rc = virXPathUInt("string(@model)", ctxt, &sigModel);
if (rc < 0 || sigModel == 0) {
virReportError(VIR_ERR_INTERNAL_ERROR,
_("Invalid CPU signature model in model %s"),
@@ -1212,9 +1247,10 @@ x86ModelParseSignature(virCPUx86ModelPtr model,
return -1;
}
- model->signature = x86MakeSignature(sigFamily, sigModel, 0);
+ model->signatures[i] = x86MakeSignature(sigFamily, sigModel, 0);
}
+ ctxt->node = root;
return 0;
}
@@ -1311,7 +1347,7 @@ x86ModelParse(xmlXPathContextPtr ctxt,
if (x86ModelParseAncestor(model, ctxt, map) < 0)
goto cleanup;
- if (x86ModelParseSignature(model, ctxt) < 0)
+ if (x86ModelParseSignatures(model, ctxt) < 0)
goto cleanup;
if (x86ModelParseVendor(model, ctxt, map) < 0)
@@ -1615,7 +1651,8 @@ x86Compute(virCPUDefPtr host,
&host_model->vendor->cpuid) < 0)
goto error;
- if (x86DataAddSignature(&guest_model->data, host_model->signature) <
0)
+ if (host_model->signatures &&
+ x86DataAddSignature(&guest_model->data, *host_model->signatures)
< 0)
goto error;
if (cpu->type == VIR_CPU_TYPE_GUEST
@@ -1721,6 +1758,21 @@ virCPUx86Compare(virCPUDefPtr host,
}
+static bool
+x86ModelHasSignature(virCPUx86ModelPtr model,
+ uint32_t signature)
+{
+ size_t i;
+
+ for (i = 0; i < model->nsignatures; i++) {
+ if (model->signatures[i] == signature)
+ return true;
+ }
+
+ return false;
+}
+
+
/*
* Checks whether a candidate model is a better fit for the CPU data than the
* current model.
@@ -1762,8 +1814,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current,
* consider candidates with matching family/model.
*/
if (signature &&
- current->signature == signature &&
- candidate->signature != signature) {
+ x86ModelHasSignature(current, signature) &&
+ !x86ModelHasSignature(candidate, signature)) {
VIR_DEBUG("%s differs in signature from matching %s",
cpuCandidate->model, cpuCurrent->model);
return 0;
@@ -1779,8 +1831,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current,
* result in longer list of features.
*/
if (signature &&
- candidate->signature == signature &&
- current->signature != signature) {
+ x86ModelHasSignature(candidate, signature) &&
+ !x86ModelHasSignature(current, signature)) {
VIR_DEBUG("%s provides matching signature", cpuCandidate->model);
return 1;
}
@@ -1844,6 +1896,8 @@ x86Decode(virCPUDefPtr cpu,
virCPUx86Data features = VIR_CPU_X86_DATA_INIT;
virCPUx86VendorPtr vendor;
virDomainCapsCPUModelPtr hvModel = NULL;
+ virBuffer sigBuf = VIR_BUFFER_INITIALIZER;
+ char *sigs = NULL;
uint32_t signature;
ssize_t i;
int rc;
@@ -1936,6 +1990,18 @@ x86Decode(virCPUDefPtr cpu,
if (vendor && VIR_STRDUP(cpu->vendor, vendor->name) < 0)
goto cleanup;
+ for (i = 0; i < model->nsignatures; i++)
+ virBufferAsprintf(&sigBuf, "%06x,", model->signatures[i]);
+
+ virBufferTrim(&sigBuf, ",", -1);
+ if (virBufferCheckError(&sigBuf) < 0)
+ goto cleanup;
+
+ sigs = virBufferContentAndReset(&sigBuf);
+
Formatting the list of signatures is a) unrelated to decoding the CPU
b) only used for debug output
Can you split it out in a separate function to address a)?
I don't think we have a way to avoid b).
Alternatively, you can format just the model name.
+ VIR_DEBUG("Using CPU model %s (signatures %s) for CPU with
signature %06lx",
+ model->name, sigs, (long)signature);
+
VIR_STEAL_PTR(cpu->model, cpuModel->model);
VIR_STEAL_PTR(cpu->features, cpuModel->features);
cpu->nfeatures = cpuModel->nfeatures;
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
12:09 a.m.
New subject: [libvirt] [PATCH 11/26] cpu_x86: Allow multiple signatures for a CPU model
On Thu, Feb 28, 2019 at 16:27:34 +0100, Ján Tomko wrote:
On Wed, Feb 27, 2019 at 02:29:01PM +0100, Jiri Denemark wrote:
>CPU signatures in the cpu_map serve as a hint for CPUID to CPU model
>matching algorithm. If the CPU signatures matches any CPU model in the
>cpu_map, this model will be the preferred one.
>
>This works out well and solved several mismatches, but in real world
>CPUs which should match a single CPU model may be produced with several
>different signatures. For example, low voltage Broadwell CPUs for
>laptops and Broadwell CPUs for servers differ in CPU model numbers while
>we should detect them all as Broadwell CPU model.
>
>This patch adds support for storing several signatures for a single CPU
>model to make this hint useful for more CPUs. Later commits will provide
>additional signatures for existing CPU models, which will correct some
>results in our CPU test suite.
>
>Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
>---
> src/cpu/cpu_x86.c | 104 ++++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 86 insertions(+), 18 deletions(-)
>
>diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
>index c2f22f399f..89303400af 100644
>--- a/src/cpu/cpu_x86.c
>+++ b/src/cpu/cpu_x86.c
...
>@@ -1187,16 +1206,32 @@ x86ModelParseAncestor(virCPUx86ModelPtr
model,
>
>
> static int
>-x86ModelParseSignature(virCPUx86ModelPtr model,
>- xmlXPathContextPtr ctxt)
>+x86ModelParseSignatures(virCPUx86ModelPtr model,
>+ xmlXPathContextPtr ctxt)
> {
>- int rc;
This variable was added to this place just a few commits above.
Yeah, I moved it inside the for loop in this patch as it made more sense
to me. I can keep it here if you wish.
>+ VIR_AUTOFREE(xmlNodePtr *) nodes = NULL;
>+ xmlNodePtr root = ctxt->node;
>+ size_t i;
>+ int n;
>
>- if (virXPathBoolean("boolean(./signature)", ctxt)) {
>+ if ((n = virXPathNodeSet("./signature", ctxt, &nodes)) <= 0)
>+ return n;
>+
>+ /* Remove inherited signatures. */
>+ VIR_FREE(model->signatures);
>+
>+ model->nsignatures = n;
>+ if (VIR_ALLOC_N(model->signatures, n) < 0)
>+ return -1;
>+
>+ for (i = 0; i < n; i++) {
> unsigned int sigFamily = 0;
> unsigned int sigModel = 0;
>+ int rc;
>
>- rc = virXPathUInt("string(./signature/@family)", ctxt,
&sigFamily);
>+ ctxt->node = nodes[i];
>+
>+ rc = virXPathUInt("string(@family)", ctxt, &sigFamily);
The ctxt->node and XPath changes could have been separate.
I don't think so, the change is part of the switch from one <signature>
element to several <signature> elements.
> if (rc < 0 || sigFamily == 0) {
> virReportError(VIR_ERR_INTERNAL_ERROR,
> _("Invalid CPU signature family in model %s"),
...
>@@ -1936,6 +1990,18 @@ x86Decode(virCPUDefPtr cpu,
> if (vendor && VIR_STRDUP(cpu->vendor, vendor->name) < 0)
> goto cleanup;
>
>+ for (i = 0; i < model->nsignatures; i++)
>+ virBufferAsprintf(&sigBuf, "%06x,", model->signatures[i]);
>+
>+ virBufferTrim(&sigBuf, ",", -1);
>+ if (virBufferCheckError(&sigBuf) < 0)
>+ goto cleanup;
>+
>+ sigs = virBufferContentAndReset(&sigBuf);
>+
Formatting the list of signatures is a) unrelated to decoding the CPU
b) only used for debug output
Can you split it out in a separate function to address a)?
OK, I was too lazy when I was writing this :-)
I don't think we have a way to avoid b).
Alternatively, you can format just the model name.
That was in the first (private) version of this patch, but I realized
it's useful to know whether the CPU model was selected because it
matched an existing signature or whether it is just a guess based on the
number of additional features.
Jirka
9:29 p.m.
New subject: [libvirt] [PATCH 12/26] qemu_capabilities: Inroduce virQEMUCapsGetCPUModelX86Data
The code for transforming qemuMonitorCPUModelInfo data from QEMU into
virCPUDefPtr consumable by virCPU* APIs was hidden inside
virQEMUCapsInitCPUModelX86. This patch moves it into a new function to
make it usable in tests.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 50 ++++++++++++++++++++++++------------
src/qemu/qemu_capspriv.h | 4 +++
2 files changed, 38 insertions(+), 16 deletions(-)
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
index b48bcbebee..0504d99373 100644
--- a/src/qemu/qemu_capabilities.c
+++ b/src/qemu/qemu_capabilities.c
@@ -2818,28 +2818,17 @@ virQEMUCapsInitCPUModelS390(virQEMUCapsPtr qemuCaps,
}
-/**
- * Returns 0 when host CPU model provided by QEMU was filled in qemuCaps,
- * 1 when the caller should fall back to using virCapsPtr->host.cpu,
- * -1 on error.
- */
-static int
-virQEMUCapsInitCPUModelX86(virQEMUCapsPtr qemuCaps,
- virDomainVirtType type,
- qemuMonitorCPUModelInfoPtr model,
- virCPUDefPtr cpu,
- bool migratable)
+virCPUDataPtr
+virQEMUCapsGetCPUModelX86Data(qemuMonitorCPUModelInfoPtr model,
+ bool migratable)
{
- virCPUDataPtr data = NULL;
unsigned long long sigFamily = 0;
unsigned long long sigModel = 0;
unsigned long long sigStepping = 0;
- int ret = -1;
+ virCPUDataPtr data = NULL;
+ virCPUDataPtr ret = NULL;
size_t i;
- if (!model)
- return 1;
-
if (!(data = virCPUDataNew(VIR_ARCH_X86_64)))
goto cleanup;
@@ -2880,6 +2869,35 @@ virQEMUCapsInitCPUModelX86(virQEMUCapsPtr qemuCaps,
if (virCPUx86DataSetSignature(data, sigFamily, sigModel, sigStepping) < 0)
goto cleanup;
+ VIR_STEAL_PTR(ret, data);
+
+ cleanup:
+ virCPUDataFree(data);
+ return ret;
+}
+
+
+/**
+ * Returns 0 when host CPU model provided by QEMU was filled in qemuCaps,
+ * 1 when the caller should fall back to using virCapsPtr->host.cpu,
+ * -1 on error.
+ */
+static int
+virQEMUCapsInitCPUModelX86(virQEMUCapsPtr qemuCaps,
+ virDomainVirtType type,
+ qemuMonitorCPUModelInfoPtr model,
+ virCPUDefPtr cpu,
+ bool migratable)
+{
+ virCPUDataPtr data = NULL;
+ int ret = -1;
+
+ if (!model)
+ return 1;
+
+ if (!(data = virQEMUCapsGetCPUModelX86Data(model, migratable)))
+ goto cleanup;
+
if (cpuDecode(cpu, data, virQEMUCapsGetCPUDefinitions(qemuCaps, type)) < 0)
goto cleanup;
diff --git a/src/qemu/qemu_capspriv.h b/src/qemu/qemu_capspriv.h
index b995e4d5d3..c8d45d699b 100644
--- a/src/qemu/qemu_capspriv.h
+++ b/src/qemu/qemu_capspriv.h
@@ -73,6 +73,10 @@ virQEMUCapsSetCPUModelInfo(virQEMUCapsPtr qemuCaps,
virDomainVirtType type,
qemuMonitorCPUModelInfoPtr modelInfo);
+virCPUDataPtr
+virQEMUCapsGetCPUModelX86Data(qemuMonitorCPUModelInfoPtr model,
+ bool migratable);
+
virCPUDefPtr
virQEMUCapsProbeHostCPUForEmulator(virArch hostArch,
virQEMUCapsPtr qemuCaps,
--
2.21.0
11:38 p.m.
New subject: [libvirt] [PATCH 12/26] qemu_capabilities: Inroduce virQEMUCapsGetCPUModelX86Data
On Wed, Feb 27, 2019 at 02:29:02PM +0100, Jiri Denemark wrote:
The code for transforming qemuMonitorCPUModelInfo data from QEMU into
virCPUDefPtr consumable by virCPU* APIs was hidden inside
virQEMUCapsInitCPUModelX86. This patch moves it into a new function to
make it usable in tests.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 50 ++++++++++++++++++++++++------------
src/qemu/qemu_capspriv.h | 4 +++
2 files changed, 38 insertions(+), 16 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 13/26] qemu_capabilities: Introduce virQEMUCapsGetCPUModelInfo
This is a simple wrapper around virQEMUCapsGetHostCPUData usable in
tests for getting qemuMonitorCPUModelInfoPtr from QEMU caps.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 10 ++++++++++
src/qemu/qemu_capspriv.h | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
index 0504d99373..4c22baab18 100644
--- a/src/qemu/qemu_capabilities.c
+++ b/src/qemu/qemu_capabilities.c
@@ -3041,6 +3041,16 @@ virQEMUCapsInitHostCPUModel(virQEMUCapsPtr qemuCaps,
}
+qemuMonitorCPUModelInfoPtr
+virQEMUCapsGetCPUModelInfo(virQEMUCapsPtr qemuCaps,
+ virDomainVirtType type)
+{
+ virQEMUCapsHostCPUDataPtr cpuData = virQEMUCapsGetHostCPUData(qemuCaps, type);
+
+ return cpuData->info;
+}
+
+
void
virQEMUCapsSetCPUModelInfo(virQEMUCapsPtr qemuCaps,
virDomainVirtType type,
diff --git a/src/qemu/qemu_capspriv.h b/src/qemu/qemu_capspriv.h
index c8d45d699b..2d059bee8c 100644
--- a/src/qemu/qemu_capspriv.h
+++ b/src/qemu/qemu_capspriv.h
@@ -68,6 +68,10 @@ virQEMUCapsInitCPUModel(virQEMUCapsPtr qemuCaps,
void
virQEMUCapsInitQMPBasicArch(virQEMUCapsPtr qemuCaps);
+qemuMonitorCPUModelInfoPtr
+virQEMUCapsGetCPUModelInfo(virQEMUCapsPtr qemuCaps,
+ virDomainVirtType type);
+
void
virQEMUCapsSetCPUModelInfo(virQEMUCapsPtr qemuCaps,
virDomainVirtType type,
--
2.21.0
11:44 p.m.
New subject: [libvirt] [PATCH 13/26] qemu_capabilities: Introduce virQEMUCapsGetCPUModelInfo
On Wed, Feb 27, 2019 at 02:29:03PM +0100, Jiri Denemark wrote:
This is a simple wrapper around virQEMUCapsGetHostCPUData usable in
tests for getting qemuMonitorCPUModelInfoPtr from QEMU caps.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 10 ++++++++++
src/qemu/qemu_capspriv.h | 4 ++++
2 files changed, 14 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 14/26] qemu_capabilities: Use virQEMUCapsGetCPUModelInfo
Most places in qemu_capabilities.c which call virQEMUCapsGetHostCPUData
actually need qemuMonitorCPUModelInfoPtr from QEMU caps. Let's use the
wrapper introduced in the previous commit instead.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 31 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
index 4c22baab18..3a62f9a5ab 100644
--- a/src/qemu/qemu_capabilities.c
+++ b/src/qemu/qemu_capabilities.c
@@ -2401,7 +2401,6 @@ virQEMUCapsProbeQMPHostCPU(virQEMUCapsPtr qemuCaps,
const char *model;
qemuMonitorCPUModelExpansionType type;
virDomainVirtType virtType;
- virQEMUCapsHostCPUDataPtr cpuData;
int ret = -1;
if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_QUERY_CPU_MODEL_EXPANSION))
@@ -2415,8 +2414,6 @@ virQEMUCapsProbeQMPHostCPU(virQEMUCapsPtr qemuCaps,
model = "host";
}
- cpuData = virQEMUCapsGetHostCPUData(qemuCaps, virtType);
-
/* Some x86_64 features defined in cpu_map.xml use spelling which differ
* from the one preferred by QEMU. Static expansion would give us only the
* preferred spelling, thus we need to do a full expansion on the result of
@@ -2468,7 +2465,8 @@ virQEMUCapsProbeQMPHostCPU(virQEMUCapsPtr qemuCaps,
modelInfo->migratability = true;
}
- VIR_STEAL_PTR(cpuData->info, modelInfo);
+ virQEMUCapsSetCPUModelInfo(qemuCaps, virtType, modelInfo);
+ modelInfo = NULL;
ret = 0;
cleanup:
@@ -2493,24 +2491,24 @@ virQEMUCapsGetCPUFeatures(virQEMUCapsPtr qemuCaps,
bool migratable,
char ***features)
{
- virQEMUCapsHostCPUDataPtr data;
+ qemuMonitorCPUModelInfoPtr modelInfo;
char **list;
size_t i;
size_t n;
int ret = -1;
*features = NULL;
- data = virQEMUCapsGetHostCPUData(qemuCaps, virtType);
+ modelInfo = virQEMUCapsGetCPUModelInfo(qemuCaps, virtType);
- if (!data->info)
+ if (!modelInfo)
return 0;
- if (VIR_ALLOC_N(list, data->info->nprops + 1) < 0)
+ if (VIR_ALLOC_N(list, modelInfo->nprops + 1) < 0)
return -1;
n = 0;
- for (i = 0; i < data->info->nprops; i++) {
- qemuMonitorCPUPropertyPtr prop = data->info->props + i;
+ for (i = 0; i < modelInfo->nprops; i++) {
+ qemuMonitorCPUPropertyPtr prop = modelInfo->props + i;
if (migratable && prop->migratable == VIR_TRISTATE_BOOL_NO)
continue;
@@ -2520,7 +2518,7 @@ virQEMUCapsGetCPUFeatures(virQEMUCapsPtr qemuCaps,
}
VIR_STEAL_PTR(*features, list);
- if (migratable && !data->info->migratability)
+ if (migratable && !modelInfo->migratability)
ret = 1;
else
ret = 0;
@@ -2921,17 +2919,17 @@ virQEMUCapsInitCPUModel(virQEMUCapsPtr qemuCaps,
virCPUDefPtr cpu,
bool migratable)
{
- virQEMUCapsHostCPUDataPtr cpuData = virQEMUCapsGetHostCPUData(qemuCaps, type);
+ qemuMonitorCPUModelInfoPtr modelInfo = virQEMUCapsGetCPUModelInfo(qemuCaps, type);
int ret = 1;
- if (migratable && cpuData->info &&
!cpuData->info->migratability)
+ if (migratable && modelInfo && !modelInfo->migratability)
return 1;
if (ARCH_IS_S390(qemuCaps->arch)) {
- ret = virQEMUCapsInitCPUModelS390(qemuCaps, type, cpuData->info,
+ ret = virQEMUCapsInitCPUModelS390(qemuCaps, type, modelInfo,
cpu, migratable);
} else if (ARCH_IS_X86(qemuCaps->arch)) {
- ret = virQEMUCapsInitCPUModelX86(qemuCaps, type, cpuData->info,
+ ret = virQEMUCapsInitCPUModelX86(qemuCaps, type, modelInfo,
cpu, migratable);
}
@@ -3648,8 +3646,7 @@ virQEMUCapsFormatHostCPUModelInfo(virQEMUCapsPtr qemuCaps,
virBufferPtr buf,
virDomainVirtType type)
{
- virQEMUCapsHostCPUDataPtr cpuData = virQEMUCapsGetHostCPUData(qemuCaps, type);
- qemuMonitorCPUModelInfoPtr model = cpuData->info;
+ qemuMonitorCPUModelInfoPtr model = virQEMUCapsGetCPUModelInfo(qemuCaps, type);
const char *typeStr = type == VIR_DOMAIN_VIRT_KVM ? "kvm" :
"tcg";
size_t i;
--
2.21.0
midnight
New subject: [libvirt] [PATCH 14/26] qemu_capabilities: Use virQEMUCapsGetCPUModelInfo
On Wed, Feb 27, 2019 at 02:29:04PM +0100, Jiri Denemark wrote:
Most places in qemu_capabilities.c which call
virQEMUCapsGetHostCPUData
actually need qemuMonitorCPUModelInfoPtr from QEMU caps. Let's use the
wrapper introduced in the previous commit instead.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/qemu/qemu_capabilities.c | 31 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 17 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 15/26] cpu_x86: Add virCPUx86DataGetSignature for tests
The function exports the functionality of x86DataToSignatureFull and
x86MakeSignature to the test suite.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 12 ++++++++++++
src/cpu/cpu_x86.h | 5 +++++
src/libvirt_private.syms | 1 +
3 files changed, 18 insertions(+)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 89303400af..56e6d95bb1 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -3059,6 +3059,18 @@ virCPUx86DataSetSignature(virCPUDataPtr cpuData,
}
+uint32_t
+virCPUx86DataGetSignature(virCPUDataPtr cpuData,
+ unsigned int *family,
+ unsigned int *model,
+ unsigned int *stepping)
+{
+ x86DataToSignatureFull(&cpuData->data.x86, family, model, stepping);
+
+ return x86MakeSignature(*family, *model, *stepping);
+}
+
+
int
virCPUx86DataSetVendor(virCPUDataPtr cpuData,
const char *vendor)
diff --git a/src/cpu/cpu_x86.h b/src/cpu/cpu_x86.h
index dedf8dedfe..78714c0d67 100644
--- a/src/cpu/cpu_x86.h
+++ b/src/cpu/cpu_x86.h
@@ -34,6 +34,11 @@ int virCPUx86DataSetSignature(virCPUDataPtr cpuData,
unsigned int model,
unsigned int stepping);
+uint32_t virCPUx86DataGetSignature(virCPUDataPtr cpuData,
+ unsigned int *family,
+ unsigned int *model,
+ unsigned int *stepping);
+
int virCPUx86DataSetVendor(virCPUDataPtr cpuData,
const char *vendor);
diff --git a/src/libvirt_private.syms b/src/libvirt_private.syms
index 038a744981..2c6143083a 100644
--- a/src/libvirt_private.syms
+++ b/src/libvirt_private.syms
@@ -1206,6 +1206,7 @@ virCPUValidateFeatures;
# cpu/cpu_x86.h
virCPUx86DataAddCPUID;
virCPUx86DataAddFeature;
+virCPUx86DataGetSignature;
virCPUx86DataSetSignature;
virCPUx86DataSetVendor;
--
2.21.0
12:20 a.m.
New subject: [libvirt] [PATCH 15/26] cpu_x86: Add virCPUx86DataGetSignature for tests
On Wed, Feb 27, 2019 at 02:29:05PM +0100, Jiri Denemark wrote:
The function exports the functionality of x86DataToSignatureFull and
x86MakeSignature to the test suite.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 12 ++++++++++++
src/cpu/cpu_x86.h | 5 +++++
src/libvirt_private.syms | 1 +
3 files changed, 18 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 16/26] cpu_map: Add hex representation of signatures
The family/model numbers are nice for humans or for comparing with
/proc/cpuinfo, but sometimes there's a need to see the CPUID
representation of the signature. Let's add it into a comment for each
signature in out cpu_map XMLs as the conversion is not exactly
straightforward.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Broadwell-IBRS.xml | 2 +-
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 2 +-
src/cpu_map/x86_Broadwell-noTSX.xml | 2 +-
src/cpu_map/x86_Broadwell.xml | 2 +-
src/cpu_map/x86_Conroe.xml | 2 +-
src/cpu_map/x86_EPYC-IBRS.xml | 2 +-
src/cpu_map/x86_EPYC.xml | 2 +-
src/cpu_map/x86_Haswell-IBRS.xml | 2 +-
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 2 +-
src/cpu_map/x86_Haswell-noTSX.xml | 2 +-
src/cpu_map/x86_Haswell.xml | 2 +-
src/cpu_map/x86_Icelake-Client.xml | 2 +-
src/cpu_map/x86_Icelake-Server.xml | 2 +-
src/cpu_map/x86_IvyBridge-IBRS.xml | 2 +-
src/cpu_map/x86_IvyBridge.xml | 2 +-
src/cpu_map/x86_Nehalem-IBRS.xml | 2 +-
src/cpu_map/x86_Nehalem.xml | 2 +-
src/cpu_map/x86_Opteron_G1.xml | 2 +-
src/cpu_map/x86_Opteron_G2.xml | 2 +-
src/cpu_map/x86_Opteron_G3.xml | 2 +-
src/cpu_map/x86_Opteron_G4.xml | 2 +-
src/cpu_map/x86_Opteron_G5.xml | 2 +-
src/cpu_map/x86_Penryn.xml | 2 +-
src/cpu_map/x86_SandyBridge-IBRS.xml | 2 +-
src/cpu_map/x86_SandyBridge.xml | 2 +-
src/cpu_map/x86_Skylake-Client-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Client.xml | 2 +-
src/cpu_map/x86_Skylake-Server-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Server.xml | 2 +-
src/cpu_map/x86_Westmere-IBRS.xml | 2 +-
src/cpu_map/x86_Westmere.xml | 2 +-
31 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
index fc7a3371a5..efaa5c9b70 100644
--- a/src/cpu_map/x86_Broadwell-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Broadwell-IBRS'>
- <signature family='6' model='61'/>
+ <signature family='6' model='61'/> <!-- 0306d0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
index 19949cb6ca..fb1cf55a4f 100644
--- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Broadwell-noTSX-IBRS'>
- <signature family='6' model='61'/>
+ <signature family='6' model='61'/> <!-- 0306d0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
index 6219bd4102..8e9cff14ad 100644
--- a/src/cpu_map/x86_Broadwell-noTSX.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Broadwell-noTSX'>
- <signature family='6' model='61'/>
+ <signature family='6' model='61'/> <!-- 0306d0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
index 1511394f0b..a9850c9126 100644
--- a/src/cpu_map/x86_Broadwell.xml
+++ b/src/cpu_map/x86_Broadwell.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Broadwell'>
- <signature family='6' model='61'/>
+ <signature family='6' model='61'/> <!-- 0306d0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Conroe.xml b/src/cpu_map/x86_Conroe.xml
index ebcab7be31..0055e5005a 100644
--- a/src/cpu_map/x86_Conroe.xml
+++ b/src/cpu_map/x86_Conroe.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Conroe'>
- <signature family='6' model='15'/>
+ <signature family='6' model='15'/> <!-- 0006f0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_EPYC-IBRS.xml b/src/cpu_map/x86_EPYC-IBRS.xml
index 219ead70df..283697ebd1 100644
--- a/src/cpu_map/x86_EPYC-IBRS.xml
+++ b/src/cpu_map/x86_EPYC-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='EPYC-IBPB'>
- <signature family='23' model='1'/>
+ <signature family='23' model='1'/> <!-- 800f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_EPYC.xml b/src/cpu_map/x86_EPYC.xml
index 6458dc820c..f0601392fd 100644
--- a/src/cpu_map/x86_EPYC.xml
+++ b/src/cpu_map/x86_EPYC.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='EPYC'>
- <signature family='23' model='1'/>
+ <signature family='23' model='1'/> <!-- 800f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBRS.xml
index 01bab7b803..dea43ad71d 100644
--- a/src/cpu_map/x86_Haswell-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Haswell-IBRS'>
- <signature family='6' model='60'/>
+ <signature family='6' model='60'/> <!-- 0306c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
index 7b53b7be29..7013540428 100644
--- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Haswell-noTSX-IBRS'>
- <signature family='6' model='60'/>
+ <signature family='6' model='60'/> <!-- 0306c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-noTSX.xml
index 10b460818a..e183364f3b 100644
--- a/src/cpu_map/x86_Haswell-noTSX.xml
+++ b/src/cpu_map/x86_Haswell-noTSX.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Haswell-noTSX'>
- <signature family='6' model='60'/>
+ <signature family='6' model='60'/> <!-- 0306c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml
index 84275b1bdf..eee98264b2 100644
--- a/src/cpu_map/x86_Haswell.xml
+++ b/src/cpu_map/x86_Haswell.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Haswell'>
- <signature family='6' model='60'/>
+ <signature family='6' model='60'/> <!-- 0306c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Icelake-Client.xml b/src/cpu_map/x86_Icelake-Client.xml
index bdd46ee96e..0b16bbcc5e 100644
--- a/src/cpu_map/x86_Icelake-Client.xml
+++ b/src/cpu_map/x86_Icelake-Client.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Icelake-Client'>
- <signature family='6' model='126'/>
+ <signature family='6' model='126'/> <!-- 0706e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Icelake-Server.xml b/src/cpu_map/x86_Icelake-Server.xml
index 0c02c9fca8..fb15977a59 100644
--- a/src/cpu_map/x86_Icelake-Server.xml
+++ b/src/cpu_map/x86_Icelake-Server.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Icelake-Server'>
- <signature family='6' model='134'/>
+ <signature family='6' model='134'/> <!-- 080660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge-IBRS.xml
index 27eb120a8a..4a4bc0c97b 100644
--- a/src/cpu_map/x86_IvyBridge-IBRS.xml
+++ b/src/cpu_map/x86_IvyBridge-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='IvyBridge-IBRS'>
- <signature family='6' model='58'/>
+ <signature family='6' model='58'/> <!-- 0306a0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml
index 54f5f55a51..da4792595f 100644
--- a/src/cpu_map/x86_IvyBridge.xml
+++ b/src/cpu_map/x86_IvyBridge.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='IvyBridge'>
- <signature family='6' model='58'/>
+ <signature family='6' model='58'/> <!-- 0306a0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBRS.xml
index f2230ffa89..f3049e0ba6 100644
--- a/src/cpu_map/x86_Nehalem-IBRS.xml
+++ b/src/cpu_map/x86_Nehalem-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Nehalem-IBRS'>
- <signature family='6' model='26'/>
+ <signature family='6' model='26'/> <!-- 0106a0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml
index 8e0fd5dc49..a05c16f2b1 100644
--- a/src/cpu_map/x86_Nehalem.xml
+++ b/src/cpu_map/x86_Nehalem.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Nehalem'>
- <signature family='6' model='26'/>
+ <signature family='6' model='26'/> <!-- 0106a0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_Opteron_G1.xml b/src/cpu_map/x86_Opteron_G1.xml
index 8d043fe889..73cf1de71e 100644
--- a/src/cpu_map/x86_Opteron_G1.xml
+++ b/src/cpu_map/x86_Opteron_G1.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Opteron_G1'>
- <signature family='15' model='6'/>
+ <signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_Opteron_G2.xml b/src/cpu_map/x86_Opteron_G2.xml
index 774e86462f..342105730e 100644
--- a/src/cpu_map/x86_Opteron_G2.xml
+++ b/src/cpu_map/x86_Opteron_G2.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Opteron_G2'>
- <signature family='15' model='6'/>
+ <signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_Opteron_G3.xml b/src/cpu_map/x86_Opteron_G3.xml
index 5d27e635dc..7fbf8ac9e9 100644
--- a/src/cpu_map/x86_Opteron_G3.xml
+++ b/src/cpu_map/x86_Opteron_G3.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Opteron_G3'>
- <signature family='15' model='6'/>
+ <signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='abm'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Opteron_G4.xml b/src/cpu_map/x86_Opteron_G4.xml
index d77cc286ff..463b3676a0 100644
--- a/src/cpu_map/x86_Opteron_G4.xml
+++ b/src/cpu_map/x86_Opteron_G4.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Opteron_G4'>
- <signature family='21' model='1'/>
+ <signature family='21' model='1'/> <!-- 600f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Opteron_G5.xml b/src/cpu_map/x86_Opteron_G5.xml
index 9a5ecbd4da..0f8fe32c87 100644
--- a/src/cpu_map/x86_Opteron_G5.xml
+++ b/src/cpu_map/x86_Opteron_G5.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Opteron_G5'>
- <signature family='21' model='2'/>
+ <signature family='21' model='2'/> <!-- 600f20 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Penryn.xml b/src/cpu_map/x86_Penryn.xml
index 9b0c0cfd0e..41febb2ddf 100644
--- a/src/cpu_map/x86_Penryn.xml
+++ b/src/cpu_map/x86_Penryn.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Penryn'>
- <signature family='6' model='23'/>
+ <signature family='6' model='23'/> <!-- 010670 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBridge-IBRS.xml
index 1f56b4bc81..6d9af68146 100644
--- a/src/cpu_map/x86_SandyBridge-IBRS.xml
+++ b/src/cpu_map/x86_SandyBridge-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='SandyBridge-IBRS'>
- <signature family='6' model='42'/>
+ <signature family='6' model='42'/> <!-- 0206a0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.xml
index eea85fc3f3..d335c71a31 100644
--- a/src/cpu_map/x86_SandyBridge.xml
+++ b/src/cpu_map/x86_SandyBridge.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='SandyBridge'>
- <signature family='6' model='42'/>
+ <signature family='6' model='42'/> <!-- 0206a0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-IBRS.xml
index 1603bb8c13..c8e15ef974 100644
--- a/src/cpu_map/x86_Skylake-Client-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Client-IBRS'>
- <signature family='6' model='94'/>
+ <signature family='6' model='94'/> <!-- 0506e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-Client.xml
index c0286b9fa5..1cfeb9196e 100644
--- a/src/cpu_map/x86_Skylake-Client.xml
+++ b/src/cpu_map/x86_Skylake-Client.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Client'>
- <signature family='6' model='94'/>
+ <signature family='6' model='94'/> <!-- 0506e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Skylake-Server-IBRS.xml
b/src/cpu_map/x86_Skylake-Server-IBRS.xml
index 45350792a0..71179f9f74 100644
--- a/src/cpu_map/x86_Skylake-Server-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Server-IBRS'>
- <signature family='6' model='85'/>
+ <signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Skylake-Server.xml b/src/cpu_map/x86_Skylake-Server.xml
index 0119428357..2da69e0dfc 100644
--- a/src/cpu_map/x86_Skylake-Server.xml
+++ b/src/cpu_map/x86_Skylake-Server.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Server'>
- <signature family='6' model='85'/>
+ <signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Westmere-IBRS.xml b/src/cpu_map/x86_Westmere-IBRS.xml
index dea7a73dcd..3baf56f47a 100644
--- a/src/cpu_map/x86_Westmere-IBRS.xml
+++ b/src/cpu_map/x86_Westmere-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Westmere-IBRS'>
- <signature family='6' model='44'/>
+ <signature family='6' model='44'/> <!-- 0206c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml
index f5c31449e0..14f17f588a 100644
--- a/src/cpu_map/x86_Westmere.xml
+++ b/src/cpu_map/x86_Westmere.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Westmere'>
- <signature family='6' model='44'/>
+ <signature family='6' model='44'/> <!-- 0206c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
--
2.21.0
12:20 a.m.
New subject: [libvirt] [PATCH 16/26] cpu_map: Add hex representation of signatures
On Wed, Feb 27, 2019 at 02:29:06PM +0100, Jiri Denemark wrote:
The family/model numbers are nice for humans or for comparing with
/proc/cpuinfo, but sometimes there's a need to see the CPUID
representation of the signature. Let's add it into a comment for each
signature in out cpu_map XMLs as the conversion is not exactly
straightforward.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Broadwell-IBRS.xml | 2 +-
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 2 +-
src/cpu_map/x86_Broadwell-noTSX.xml | 2 +-
src/cpu_map/x86_Broadwell.xml | 2 +-
src/cpu_map/x86_Conroe.xml | 2 +-
src/cpu_map/x86_EPYC-IBRS.xml | 2 +-
src/cpu_map/x86_EPYC.xml | 2 +-
src/cpu_map/x86_Haswell-IBRS.xml | 2 +-
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 2 +-
src/cpu_map/x86_Haswell-noTSX.xml | 2 +-
src/cpu_map/x86_Haswell.xml | 2 +-
src/cpu_map/x86_Icelake-Client.xml | 2 +-
src/cpu_map/x86_Icelake-Server.xml | 2 +-
src/cpu_map/x86_IvyBridge-IBRS.xml | 2 +-
src/cpu_map/x86_IvyBridge.xml | 2 +-
src/cpu_map/x86_Nehalem-IBRS.xml | 2 +-
src/cpu_map/x86_Nehalem.xml | 2 +-
src/cpu_map/x86_Opteron_G1.xml | 2 +-
src/cpu_map/x86_Opteron_G2.xml | 2 +-
src/cpu_map/x86_Opteron_G3.xml | 2 +-
src/cpu_map/x86_Opteron_G4.xml | 2 +-
src/cpu_map/x86_Opteron_G5.xml | 2 +-
src/cpu_map/x86_Penryn.xml | 2 +-
src/cpu_map/x86_SandyBridge-IBRS.xml | 2 +-
src/cpu_map/x86_SandyBridge.xml | 2 +-
src/cpu_map/x86_Skylake-Client-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Client.xml | 2 +-
src/cpu_map/x86_Skylake-Server-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Server.xml | 2 +-
src/cpu_map/x86_Westmere-IBRS.xml | 2 +-
src/cpu_map/x86_Westmere.xml | 2 +-
31 files changed, 31 insertions(+), 31 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 17/26] cputest: Test CPU signatures
The signature computation code is not too complicated and it will likely
never change so testing it is not very important. We do it mostly for a
nice side effect of easily accessible signature numbers for all CPU
data files.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 92 +++++++++++++++++++
tests/cputestdata/x86_64-cpuid-A10-5800K.sig | 4 +
tests/cputestdata/x86_64-cpuid-Atom-D510.sig | 4 +
tests/cputestdata/x86_64-cpuid-Atom-N450.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i5-2500.sig | 4 +
.../x86_64-cpuid-Core-i5-2540M.sig | 4 +
.../x86_64-cpuid-Core-i5-4670T.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i5-650.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i5-6600.sig | 4 +
.../x86_64-cpuid-Core-i7-2600-xsaveopt.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i7-2600.sig | 4 +
.../x86_64-cpuid-Core-i7-3520M.sig | 4 +
.../x86_64-cpuid-Core-i7-3740QM.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i7-3770.sig | 4 +
.../x86_64-cpuid-Core-i7-4510U.sig | 4 +
.../x86_64-cpuid-Core-i7-4600U.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U-arat.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U-ibrs.sig | 4 +
.../x86_64-cpuid-Core-i7-5600U.sig | 4 +
.../x86_64-cpuid-Core-i7-7600U.sig | 4 +
.../cputestdata/x86_64-cpuid-Core-i7-7700.sig | 4 +
.../cputestdata/x86_64-cpuid-Core2-E6850.sig | 4 +
.../cputestdata/x86_64-cpuid-Core2-Q9500.sig | 4 +
.../x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig | 4 +
.../x86_64-cpuid-EPYC-7601-32-Core.sig | 4 +
tests/cputestdata/x86_64-cpuid-FX-8150.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-1352.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-2350.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-6234.sig | 4 +
.../cputestdata/x86_64-cpuid-Opteron-6282.sig | 4 +
.../x86_64-cpuid-Pentium-P6100.sig | 4 +
tests/cputestdata/x86_64-cpuid-Phenom-B95.sig | 4 +
.../x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-5110.sig | 4 +
.../x86_64-cpuid-Xeon-E3-1245-v5.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2609-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2623-v4.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2630-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2630-v4.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2650-v3.sig | 4 +
.../x86_64-cpuid-Xeon-E5-2650-v4.sig | 4 +
.../cputestdata/x86_64-cpuid-Xeon-E5-2650.sig | 4 +
.../cputestdata/x86_64-cpuid-Xeon-E7-4820.sig | 4 +
.../cputestdata/x86_64-cpuid-Xeon-E7-4830.sig | 4 +
.../x86_64-cpuid-Xeon-E7-8890-v3.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig | 4 +
.../x86_64-cpuid-Xeon-Gold-5115.sig | 4 +
.../x86_64-cpuid-Xeon-Gold-6148.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig | 4 +
tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig | 4 +
50 files changed, 288 insertions(+)
create mode 100644 tests/cputestdata/x86_64-cpuid-A10-5800K.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-D510.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Atom-N450.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-2500.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-2540M.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-4670T.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-650.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i5-6600.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-2600-xsaveopt.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-2600.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3520M.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3740QM.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-3770.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-4510U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-4600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U-arat.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U-ibrs.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-5600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7700.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core2-E6850.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Core2-Q9500.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-FX-8150.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-1352.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-2350.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-6234.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Opteron-6282.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Pentium-P6100.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Phenom-B95.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-5110.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E3-1245-v5.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-4820.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-4830.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-v3.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-Gold-5115.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-Gold-6148.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
diff --git a/tests/cputest.c b/tests/cputest.c
index 19caf41bf3..5b1bdc11c6 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -32,6 +32,7 @@
#include "testutils.h"
#include "cpu_conf.h"
#include "cpu/cpu.h"
+#include "cpu/cpu_x86.h"
#include "cpu/cpu_map.h"
#include "virstring.h"
@@ -642,6 +643,68 @@ cpuTestGuestCPUID(const void *arg)
}
+static int
+cpuTestCompareSignature(const struct data *data,
+ virCPUDataPtr hostData)
+{
+ unsigned long signature;
+ unsigned int family;
+ unsigned int model;
+ unsigned int stepping;
+ char *result = NULL;
+ char *sigStr = NULL;
+ int ret = -1;
+
+ signature = virCPUx86DataGetSignature(hostData, &family, &model,
&stepping);
+
+ if (virAsprintf(&result, "%s/cputestdata/%s-cpuid-%s.sig",
+ abs_srcdir, virArchToString(data->arch), data->host) < 0)
+ goto cleanup;
+
+ if (virAsprintf(&sigStr,
+ "%1$06lx\n"
+ "family: %2$2u (0x%2$02x)\n"
+ "model: %3$2u (0x%3$02x)\n"
+ "stepping: %4$2u (0x%4$02x)\n",
+ signature, family, model, stepping) < 0)
+ goto cleanup;
+
+ ret = virTestCompareToFile(sigStr, result);
+
+ cleanup:
+ VIR_FREE(result);
+ VIR_FREE(sigStr);
+ return ret;
+}
+
+
+static int
+cpuTestCPUIDSignature(const void *arg)
+{
+ const struct data *data = arg;
+ virCPUDataPtr hostData = NULL;
+ char *hostFile = NULL;
+ char *host = NULL;
+ int ret = -1;
+
+ if (virAsprintf(&hostFile, "%s/cputestdata/%s-cpuid-%s.xml",
+ abs_srcdir, virArchToString(data->arch), data->host) < 0)
+ goto cleanup;
+
+ if (virTestLoadFile(hostFile, &host) < 0 ||
+ !(hostData = virCPUDataParse(host)))
+ goto cleanup;
+
+ ret = cpuTestCompareSignature(data, hostData);
+
+ cleanup:
+ virCPUDataFree(hostData);
+ VIR_FREE(hostFile);
+ VIR_FREE(host);
+ return ret;
+}
+
+
static int
cpuTestUpdateLiveCompare(virArch arch,
virCPUDefPtr actual,
@@ -863,6 +926,31 @@ cpuTestJSONCPUID(const void *arg)
VIR_FREE(result);
return ret;
}
+
+
+static int
+cpuTestJSONSignature(const void *arg)
+{
+ const struct data *data = arg;
+ virQEMUCapsPtr qemuCaps = NULL;
+ virCPUDataPtr hostData = NULL;
+ qemuMonitorCPUModelInfoPtr modelInfo;
+ int ret = -1;
+
+ if (!(qemuCaps = cpuTestMakeQEMUCaps(data)))
+ goto cleanup;
+
+ modelInfo = virQEMUCapsGetCPUModelInfo(qemuCaps, VIR_DOMAIN_VIRT_KVM);
+ if (!(hostData = virQEMUCapsGetCPUModelX86Data(modelInfo, false)))
+ goto cleanup;
+
+ ret = cpuTestCompareSignature(data, hostData);
+
+ cleanup:
+ virObjectUnref(qemuCaps);
+ virCPUDataFree(hostData);
+ return ret;
+}
#endif
@@ -1008,6 +1096,8 @@ mymain(void)
if (json != JSON_NONE) { \
DO_TEST(arch, cpuTestJSONCPUID, host, host, \
NULL, NULL, json, 0); \
+ DO_TEST(arch, cpuTestJSONSignature, host, host, \
+ NULL, NULL, 0, 0); \
} \
} while (0)
#else
@@ -1020,6 +1110,8 @@ mymain(void)
NULL, NULL, 0, 0); \
DO_TEST(arch, cpuTestGuestCPUID, host, host, \
NULL, NULL, json, 0); \
+ DO_TEST(arch, cpuTestCPUIDSignature, host, host, \
+ NULL, NULL, 0, 0); \
DO_TEST_JSON(arch, host, json); \
if (json != JSON_NONE) { \
DO_TEST(arch, cpuTestUpdateLive, host, host, \
diff --git a/tests/cputestdata/x86_64-cpuid-A10-5800K.sig
b/tests/cputestdata/x86_64-cpuid-A10-5800K.sig
new file mode 100644
index 0000000000..7da3ad853a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-A10-5800K.sig
@@ -0,0 +1,4 @@
+610f01
+family: 21 (0x15)
+model: 16 (0x10)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Atom-D510.sig
b/tests/cputestdata/x86_64-cpuid-Atom-D510.sig
new file mode 100644
index 0000000000..24bf49172c
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Atom-D510.sig
@@ -0,0 +1,4 @@
+0106ca
+family: 6 (0x06)
+model: 28 (0x1c)
+stepping: 10 (0x0a)
diff --git a/tests/cputestdata/x86_64-cpuid-Atom-N450.sig
b/tests/cputestdata/x86_64-cpuid-Atom-N450.sig
new file mode 100644
index 0000000000..24bf49172c
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Atom-N450.sig
@@ -0,0 +1,4 @@
+0106ca
+family: 6 (0x06)
+model: 28 (0x1c)
+stepping: 10 (0x0a)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-2500.sig
b/tests/cputestdata/x86_64-cpuid-Core-i5-2500.sig
new file mode 100644
index 0000000000..9334bf089d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-2500.sig
@@ -0,0 +1,4 @@
+0206a7
+family: 6 (0x06)
+model: 42 (0x2a)
+stepping: 7 (0x07)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-2540M.sig
b/tests/cputestdata/x86_64-cpuid-Core-i5-2540M.sig
new file mode 100644
index 0000000000..9334bf089d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-2540M.sig
@@ -0,0 +1,4 @@
+0206a7
+family: 6 (0x06)
+model: 42 (0x2a)
+stepping: 7 (0x07)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T.sig
b/tests/cputestdata/x86_64-cpuid-Core-i5-4670T.sig
new file mode 100644
index 0000000000..39b3f14eca
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-4670T.sig
@@ -0,0 +1,4 @@
+0306c3
+family: 6 (0x06)
+model: 60 (0x3c)
+stepping: 3 (0x03)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-650.sig
b/tests/cputestdata/x86_64-cpuid-Core-i5-650.sig
new file mode 100644
index 0000000000..4d1601878a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-650.sig
@@ -0,0 +1,4 @@
+020652
+family: 6 (0x06)
+model: 37 (0x25)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-6600.sig
b/tests/cputestdata/x86_64-cpuid-Core-i5-6600.sig
new file mode 100644
index 0000000000..9cda0e2b4c
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-6600.sig
@@ -0,0 +1,4 @@
+0506e3
+family: 6 (0x06)
+model: 94 (0x5e)
+stepping: 3 (0x03)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-2600-xsaveopt.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-2600-xsaveopt.sig
new file mode 100644
index 0000000000..9334bf089d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-2600-xsaveopt.sig
@@ -0,0 +1,4 @@
+0206a7
+family: 6 (0x06)
+model: 42 (0x2a)
+stepping: 7 (0x07)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-2600.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-2600.sig
new file mode 100644
index 0000000000..9334bf089d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-2600.sig
@@ -0,0 +1,4 @@
+0206a7
+family: 6 (0x06)
+model: 42 (0x2a)
+stepping: 7 (0x07)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-3520M.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-3520M.sig
new file mode 100644
index 0000000000..68e920642b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-3520M.sig
@@ -0,0 +1,4 @@
+0306a9
+family: 6 (0x06)
+model: 58 (0x3a)
+stepping: 9 (0x09)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-3740QM.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-3740QM.sig
new file mode 100644
index 0000000000..68e920642b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-3740QM.sig
@@ -0,0 +1,4 @@
+0306a9
+family: 6 (0x06)
+model: 58 (0x3a)
+stepping: 9 (0x09)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-3770.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-3770.sig
new file mode 100644
index 0000000000..68e920642b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-3770.sig
@@ -0,0 +1,4 @@
+0306a9
+family: 6 (0x06)
+model: 58 (0x3a)
+stepping: 9 (0x09)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-4510U.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-4510U.sig
new file mode 100644
index 0000000000..b5137976f9
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-4510U.sig
@@ -0,0 +1,4 @@
+040651
+family: 6 (0x06)
+model: 69 (0x45)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-4600U.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-4600U.sig
new file mode 100644
index 0000000000..b5137976f9
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-4600U.sig
@@ -0,0 +1,4 @@
+040651
+family: 6 (0x06)
+model: 69 (0x45)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-arat.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-arat.sig
new file mode 100644
index 0000000000..475c8b530b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-arat.sig
@@ -0,0 +1,4 @@
+0306d4
+family: 6 (0x06)
+model: 61 (0x3d)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-ibrs.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-ibrs.sig
new file mode 100644
index 0000000000..475c8b530b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U-ibrs.sig
@@ -0,0 +1,4 @@
+0306d4
+family: 6 (0x06)
+model: 61 (0x3d)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-5600U.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U.sig
new file mode 100644
index 0000000000..475c8b530b
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-5600U.sig
@@ -0,0 +1,4 @@
+0306d4
+family: 6 (0x06)
+model: 61 (0x3d)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.sig
new file mode 100644
index 0000000000..c03d9560a4
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.sig
@@ -0,0 +1,4 @@
+0806e9
+family: 6 (0x06)
+model: 142 (0x8e)
+stepping: 9 (0x09)
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7700.sig
b/tests/cputestdata/x86_64-cpuid-Core-i7-7700.sig
new file mode 100644
index 0000000000..f2300e5c88
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7700.sig
@@ -0,0 +1,4 @@
+0906e9
+family: 6 (0x06)
+model: 158 (0x9e)
+stepping: 9 (0x09)
diff --git a/tests/cputestdata/x86_64-cpuid-Core2-E6850.sig
b/tests/cputestdata/x86_64-cpuid-Core2-E6850.sig
new file mode 100644
index 0000000000..7fe354460e
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core2-E6850.sig
@@ -0,0 +1,4 @@
+0006fb
+family: 6 (0x06)
+model: 15 (0x0f)
+stepping: 11 (0x0b)
diff --git a/tests/cputestdata/x86_64-cpuid-Core2-Q9500.sig
b/tests/cputestdata/x86_64-cpuid-Core2-Q9500.sig
new file mode 100644
index 0000000000..7c20562776
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Core2-Q9500.sig
@@ -0,0 +1,4 @@
+01067a
+family: 6 (0x06)
+model: 23 (0x17)
+stepping: 10 (0x0a)
diff --git a/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig
b/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig
new file mode 100644
index 0000000000..1aa7b071f4
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core-ibpb.sig
@@ -0,0 +1,4 @@
+800f12
+family: 23 (0x17)
+model: 1 (0x01)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core.sig
b/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core.sig
new file mode 100644
index 0000000000..1aa7b071f4
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-EPYC-7601-32-Core.sig
@@ -0,0 +1,4 @@
+800f12
+family: 23 (0x17)
+model: 1 (0x01)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-FX-8150.sig
b/tests/cputestdata/x86_64-cpuid-FX-8150.sig
new file mode 100644
index 0000000000..016add0af1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-FX-8150.sig
@@ -0,0 +1,4 @@
+600f12
+family: 21 (0x15)
+model: 1 (0x01)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Opteron-1352.sig
b/tests/cputestdata/x86_64-cpuid-Opteron-1352.sig
new file mode 100644
index 0000000000..c121f42e2d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Opteron-1352.sig
@@ -0,0 +1,4 @@
+100f23
+family: 16 (0x10)
+model: 2 (0x02)
+stepping: 3 (0x03)
diff --git a/tests/cputestdata/x86_64-cpuid-Opteron-2350.sig
b/tests/cputestdata/x86_64-cpuid-Opteron-2350.sig
new file mode 100644
index 0000000000..c121f42e2d
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Opteron-2350.sig
@@ -0,0 +1,4 @@
+100f23
+family: 16 (0x10)
+model: 2 (0x02)
+stepping: 3 (0x03)
diff --git a/tests/cputestdata/x86_64-cpuid-Opteron-6234.sig
b/tests/cputestdata/x86_64-cpuid-Opteron-6234.sig
new file mode 100644
index 0000000000..016add0af1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Opteron-6234.sig
@@ -0,0 +1,4 @@
+600f12
+family: 21 (0x15)
+model: 1 (0x01)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Opteron-6282.sig
b/tests/cputestdata/x86_64-cpuid-Opteron-6282.sig
new file mode 100644
index 0000000000..016add0af1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Opteron-6282.sig
@@ -0,0 +1,4 @@
+600f12
+family: 21 (0x15)
+model: 1 (0x01)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Pentium-P6100.sig
b/tests/cputestdata/x86_64-cpuid-Pentium-P6100.sig
new file mode 100644
index 0000000000..34b2e7dd59
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Pentium-P6100.sig
@@ -0,0 +1,4 @@
+020655
+family: 6 (0x06)
+model: 37 (0x25)
+stepping: 5 (0x05)
diff --git a/tests/cputestdata/x86_64-cpuid-Phenom-B95.sig
b/tests/cputestdata/x86_64-cpuid-Phenom-B95.sig
new file mode 100644
index 0000000000..331e40b807
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Phenom-B95.sig
@@ -0,0 +1,4 @@
+100f42
+family: 16 (0x10)
+model: 4 (0x04)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig
b/tests/cputestdata/x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig
new file mode 100644
index 0000000000..7f45f649df
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Ryzen-7-1800X-Eight-Core.sig
@@ -0,0 +1,4 @@
+800f11
+family: 23 (0x17)
+model: 1 (0x01)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-5110.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-5110.sig
new file mode 100644
index 0000000000..71a16b935a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-5110.sig
@@ -0,0 +1,4 @@
+0006f6
+family: 6 (0x06)
+model: 15 (0x0f)
+stepping: 6 (0x06)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E3-1245-v5.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E3-1245-v5.sig
new file mode 100644
index 0000000000..9cda0e2b4c
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E3-1245-v5.sig
@@ -0,0 +1,4 @@
+0506e3
+family: 6 (0x06)
+model: 94 (0x5e)
+stepping: 3 (0x03)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3.sig
new file mode 100644
index 0000000000..50c28c28b1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3.sig
@@ -0,0 +1,4 @@
+0306f2
+family: 6 (0x06)
+model: 63 (0x3f)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4.sig
new file mode 100644
index 0000000000..3fd6f3a9fd
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4.sig
@@ -0,0 +1,4 @@
+0406f1
+family: 6 (0x06)
+model: 79 (0x4f)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v3.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v3.sig
new file mode 100644
index 0000000000..50c28c28b1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v3.sig
@@ -0,0 +1,4 @@
+0306f2
+family: 6 (0x06)
+model: 63 (0x3f)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.sig
new file mode 100644
index 0000000000..3fd6f3a9fd
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.sig
@@ -0,0 +1,4 @@
+0406f1
+family: 6 (0x06)
+model: 79 (0x4f)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v3.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v3.sig
new file mode 100644
index 0000000000..50c28c28b1
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v3.sig
@@ -0,0 +1,4 @@
+0306f2
+family: 6 (0x06)
+model: 63 (0x3f)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4.sig
new file mode 100644
index 0000000000..3fd6f3a9fd
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4.sig
@@ -0,0 +1,4 @@
+0406f1
+family: 6 (0x06)
+model: 79 (0x4f)
+stepping: 1 (0x01)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.sig
new file mode 100644
index 0000000000..6cbeebd5a5
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.sig
@@ -0,0 +1,4 @@
+0206d7
+family: 6 (0x06)
+model: 45 (0x2d)
+stepping: 7 (0x07)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820.sig
new file mode 100644
index 0000000000..98fedbee20
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820.sig
@@ -0,0 +1,4 @@
+0206f2
+family: 6 (0x06)
+model: 47 (0x2f)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830.sig
new file mode 100644
index 0000000000..98fedbee20
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830.sig
@@ -0,0 +1,4 @@
+0206f2
+family: 6 (0x06)
+model: 47 (0x2f)
+stepping: 2 (0x02)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-v3.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-v3.sig
new file mode 100644
index 0000000000..56c8074137
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-v3.sig
@@ -0,0 +1,4 @@
+0306f4
+family: 6 (0x06)
+model: 63 (0x3f)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig
new file mode 100644
index 0000000000..81721dbe4a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.sig
@@ -0,0 +1,4 @@
+0206e6
+family: 6 (0x06)
+model: 46 (0x2e)
+stepping: 6 (0x06)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-Gold-5115.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-Gold-5115.sig
new file mode 100644
index 0000000000..fe1537115a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-Gold-5115.sig
@@ -0,0 +1,4 @@
+050654
+family: 6 (0x06)
+model: 85 (0x55)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-Gold-6148.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-Gold-6148.sig
new file mode 100644
index 0000000000..fe1537115a
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-Gold-6148.sig
@@ -0,0 +1,4 @@
+050654
+family: 6 (0x06)
+model: 85 (0x55)
+stepping: 4 (0x04)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
new file mode 100644
index 0000000000..b43a5b1ebf
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
@@ -0,0 +1,4 @@
+0106a5
+family: 6 (0x06)
+model: 26 (0x1a)
+stepping: 5 (0x05)
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
b/tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
new file mode 100644
index 0000000000..c24b28c5d2
--- /dev/null
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
@@ -0,0 +1,4 @@
+010676
+family: 6 (0x06)
+model: 23 (0x17)
+stepping: 6 (0x06)
--
2.21.0
12:29 a.m.
New subject: [libvirt] [PATCH 17/26] cputest: Test CPU signatures
On Wed, Feb 27, 2019 at 02:29:07PM +0100, Jiri Denemark wrote:
The signature computation code is not too complicated and it will
likely
never change so testing it is not very important. We do it mostly for a
nice side effect of easily accessible signature numbers for all CPU
data files.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
tests/cputest.c | 92 +++++++++++++++++++
tests/cputestdata/x86_64-cpuid-A10-5800K.sig | 4 +
[ many diffstat, such files ]
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-W3520.sig
create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-X5460.sig
diff --git a/tests/cputest.c b/tests/cputest.c
index 19caf41bf3..5b1bdc11c6 100644
--- a/tests/cputest.c
+++ b/tests/cputest.c
@@ -32,6 +32,7 @@
#include "testutils.h"
#include "cpu_conf.h"
#include "cpu/cpu.h"
+#include "cpu/cpu_x86.h"
#include "cpu/cpu_map.h"
#include "virstring.h"
@@ -642,6 +643,68 @@ cpuTestGuestCPUID(const void *arg)
}
+static int
+cpuTestCompareSignature(const struct data *data,
+ virCPUDataPtr hostData)
+{
+ unsigned long signature;
+ unsigned int family;
+ unsigned int model;
+ unsigned int stepping;
+ char *result = NULL;
+ char *sigStr = NULL;
Could have used VIR_AUTOFREE
+ int ret = -1;
+
+ signature = virCPUx86DataGetSignature(hostData, &family, &model,
&stepping);
+
+ if (virAsprintf(&result, "%s/cputestdata/%s-cpuid-%s.sig",
+ abs_srcdir, virArchToString(data->arch), data->host) < 0)
+ goto cleanup;
+
+ if (virAsprintf(&sigStr,
+ "%1$06lx\n"
+ "family: %2$2u (0x%2$02x)\n"
+ "model: %3$2u (0x%3$02x)\n"
+ "stepping: %4$2u (0x%4$02x)\n",
$3u to nicely align numbers greater than 0x63
+ signature, family, model, stepping) < 0)
+ goto cleanup;
+
+ ret = virTestCompareToFile(sigStr, result);
+
+ cleanup:
+ VIR_FREE(result);
+ VIR_FREE(sigStr);
+ return ret;
+}
+
+
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
12:49 a.m.
New subject: [libvirt] [PATCH 17/26] cputest: Test CPU signatures
On Thu, Feb 28, 2019 at 17:29:15 +0100, Ján Tomko wrote:
On Wed, Feb 27, 2019 at 02:29:07PM +0100, Jiri Denemark wrote:
>The signature computation code is not too complicated and it will likely
>never change so testing it is not very important. We do it mostly for a
>nice side effect of easily accessible signature numbers for all CPU
>data files.
>
>Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
>---
>+static int
>+cpuTestCompareSignature(const struct data *data,
>+ virCPUDataPtr hostData)
>+{
>+ unsigned long signature;
>+ unsigned int family;
>+ unsigned int model;
>+ unsigned int stepping;
>+ char *result = NULL;
>+ char *sigStr = NULL;
Could have used VIR_AUTOFREE
>+ int ret = -1;
>+
>+ signature = virCPUx86DataGetSignature(hostData, &family, &model,
&stepping);
>+
>+ if (virAsprintf(&result, "%s/cputestdata/%s-cpuid-%s.sig",
>+ abs_srcdir, virArchToString(data->arch), data->host) <
0)
>+ goto cleanup;
>+
>+ if (virAsprintf(&sigStr,
>+ "%1$06lx\n"
>+ "family: %2$2u (0x%2$02x)\n"
>+ "model: %3$2u (0x%3$02x)\n"
>+ "stepping: %4$2u (0x%4$02x)\n",
$3u to nicely align numbers greater than 0x63
Done (both changes).
Jirka
9:29 p.m.
New subject: [libvirt] [PATCH 18/26] cpu_map: Add more signatures for Conroe CPU model
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Conroe.xml | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/cpu_map/x86_Conroe.xml b/src/cpu_map/x86_Conroe.xml
index 0055e5005a..89fe0ad2cf 100644
--- a/src/cpu_map/x86_Conroe.xml
+++ b/src/cpu_map/x86_Conroe.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='Conroe'>
<signature family='6' model='15'/> <!-- 0006f0 -->
+ <signature family='6' model='22'/> <!-- 010660 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
--
2.21.0
12:30 a.m.
New subject: [libvirt] [PATCH 18/26] cpu_map: Add more signatures for Conroe CPU model
On Wed, Feb 27, 2019 at 02:29:08PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Conroe.xml | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 19/26] cpu_map: Add more signatures for Penryn CPU model
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Penryn.xml | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/cpu_map/x86_Penryn.xml b/src/cpu_map/x86_Penryn.xml
index 41febb2ddf..279bb05570 100644
--- a/src/cpu_map/x86_Penryn.xml
+++ b/src/cpu_map/x86_Penryn.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='Penryn'>
<signature family='6' model='23'/> <!-- 010670 -->
+ <signature family='6' model='29'/> <!-- 0106d0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
--
2.21.0
12:30 a.m.
New subject: [libvirt] [PATCH 19/26] cpu_map: Add more signatures for Penryn CPU model
On Wed, Feb 27, 2019 at 02:29:09PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Penryn.xml | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 20/26] cpu_map: Add more signatures for Nehalem CPU models
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Nehalem-IBRS.xml | 3 +++
src/cpu_map/x86_Nehalem.xml | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBRS.xml
index f3049e0ba6..8cc19eff03 100644
--- a/src/cpu_map/x86_Nehalem-IBRS.xml
+++ b/src/cpu_map/x86_Nehalem-IBRS.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Nehalem-IBRS'>
<signature family='6' model='26'/> <!-- 0106a0 -->
+ <signature family='6' model='30'/> <!-- 0106e0 -->
+ <signature family='6' model='31'/> <!-- 0106f0 -->
+ <signature family='6' model='46'/> <!-- 0206e0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml
index a05c16f2b1..530e5e8a0d 100644
--- a/src/cpu_map/x86_Nehalem.xml
+++ b/src/cpu_map/x86_Nehalem.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Nehalem'>
<signature family='6' model='26'/> <!-- 0106a0 -->
+ <signature family='6' model='30'/> <!-- 0106e0 -->
+ <signature family='6' model='31'/> <!-- 0106f0 -->
+ <signature family='6' model='46'/> <!-- 0206e0 -->
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
--
2.21.0
12:31 a.m.
New subject: [libvirt] [PATCH 20/26] cpu_map: Add more signatures for Nehalem CPU models
On Wed, Feb 27, 2019 at 02:29:10PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Nehalem-IBRS.xml | 3 +++
src/cpu_map/x86_Nehalem.xml | 3 +++
2 files changed, 6 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 21/26] cpu_map: Add more signatures for Westmere CPU model
This fixes several CPUs which were incorrectly detected as a different
CPU model.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Westmere.xml | 2 ++
tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml | 9 +++++----
tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml | 10 ++++++----
tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml | 8 ++++----
tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml | 8 +++++---
tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml | 9 +++++----
6 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml
index 14f17f588a..95c1d690c8 100644
--- a/src/cpu_map/x86_Westmere.xml
+++ b/src/cpu_map/x86_Westmere.xml
@@ -1,6 +1,8 @@
<cpus>
<model name='Westmere'>
<signature family='6' model='44'/> <!-- 0206c0 -->
+ <signature family='6' model='47'/> <!-- 0206f0 -->
+ <signature family='6' model='37'/> <!-- 020650 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml
b/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml
index f5980f53e5..cb21e48a9f 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml
@@ -1,12 +1,13 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>SandyBridge</model>
+ <model fallback='forbid'>Westmere</model>
<vendor>Intel</vendor>
<feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='pclmuldq'/>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='tsc-deadline'/>
<feature policy='require' name='hypervisor'/>
<feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
- <feature policy='disable' name='xsave'/>
- <feature policy='disable' name='avx'/>
- <feature policy='disable' name='xsaveopt'/>
+ <feature policy='require' name='rdtscp'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml
b/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml
index db5e0ae6af..20e2fa363a 100644
--- a/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml
@@ -1,6 +1,7 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>core2duo</model>
+ <model fallback='forbid'>Westmere</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
<feature policy='require' name='ss'/>
@@ -8,16 +9,17 @@
<feature policy='require' name='tm'/>
<feature policy='require' name='pbe'/>
<feature policy='require' name='dtes64'/>
+ <feature policy='require' name='monitor'/>
<feature policy='require' name='ds_cpl'/>
<feature policy='require' name='est'/>
<feature policy='require' name='tm2'/>
- <feature policy='require' name='cx16'/>
<feature policy='require' name='xtpr'/>
<feature policy='require' name='pdcm'/>
<feature policy='require' name='pcid'/>
- <feature policy='require' name='popcnt'/>
<feature policy='require' name='arat'/>
<feature policy='require' name='rdtscp'/>
- <feature policy='require' name='lahf_lm'/>
<feature policy='require' name='invtsc'/>
+ <feature policy='disable' name='sse4.1'/>
+ <feature policy='disable' name='sse4.2'/>
+ <feature policy='disable' name='aes'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml
index dbf8580a0e..659779687a 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml
@@ -1,5 +1,5 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>SandyBridge</model>
+ <model fallback='forbid'>Westmere</model>
<vendor>Intel</vendor>
<feature policy='require' name='vme'/>
<feature policy='require' name='ds'/>
@@ -8,6 +8,7 @@
<feature policy='require' name='ht'/>
<feature policy='require' name='tm'/>
<feature policy='require' name='pbe'/>
+ <feature policy='require' name='pclmuldq'/>
<feature policy='require' name='dtes64'/>
<feature policy='require' name='monitor'/>
<feature policy='require' name='ds_cpl'/>
@@ -19,10 +20,9 @@
<feature policy='require' name='pdcm'/>
<feature policy='require' name='pcid'/>
<feature policy='require' name='dca'/>
+ <feature policy='require' name='x2apic'/>
<feature policy='require' name='arat'/>
<feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='rdtscp'/>
<feature policy='require' name='invtsc'/>
- <feature policy='disable' name='tsc-deadline'/>
- <feature policy='disable' name='xsave'/>
- <feature policy='disable' name='avx'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml
index d94a330f37..e8b74c5c30 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml
@@ -1,12 +1,14 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>SandyBridge</model>
+ <model fallback='forbid'>Westmere</model>
<vendor>Intel</vendor>
<feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='pclmuldq'/>
<feature policy='require' name='pcid'/>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='tsc-deadline'/>
<feature policy='require' name='hypervisor'/>
<feature policy='require' name='tsc_adjust'/>
<feature policy='require' name='pdpe1gb'/>
- <feature policy='disable' name='xsave'/>
- <feature policy='disable' name='avx'/>
+ <feature policy='require' name='rdtscp'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml
index aae32bd7e2..da949ad25e 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml
@@ -1,14 +1,15 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>SandyBridge</model>
+ <model fallback='forbid'>Westmere</model>
<vendor>Intel</vendor>
<feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='pclmuldq'/>
<feature policy='require' name='pcid'/>
+ <feature policy='require' name='x2apic'/>
+ <feature policy='require' name='tsc-deadline'/>
<feature policy='require' name='hypervisor'/>
<feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
<feature policy='require' name='pdpe1gb'/>
- <feature policy='disable' name='xsave'/>
- <feature policy='disable' name='avx'/>
- <feature policy='disable' name='xsaveopt'/>
+ <feature policy='require' name='rdtscp'/>
</cpu>
--
2.21.0
12:31 a.m.
New subject: [libvirt] [PATCH 21/26] cpu_map: Add more signatures for Westmere CPU model
On Wed, Feb 27, 2019 at 02:29:11PM +0100, Jiri Denemark wrote:
This fixes several CPUs which were incorrectly detected as a
different
CPU model.
Neat.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Westmere.xml | 2 ++
tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml | 9 +++++----
tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml | 10 ++++++----
tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml | 8 ++++----
tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml | 8 +++++---
tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml | 9 +++++----
6 files changed, 27 insertions(+), 19 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 22/26] cpu_map: Add more signatures for SandyBridge CPU models
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
src/cpu_map/x86_SandyBridge.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBridge-IBRS.xml
index 6d9af68146..7d1342ec6f 100644
--- a/src/cpu_map/x86_SandyBridge-IBRS.xml
+++ b/src/cpu_map/x86_SandyBridge-IBRS.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='SandyBridge-IBRS'>
<signature family='6' model='42'/> <!-- 0206a0 -->
+ <signature family='6' model='45'/> <!-- 0206d0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.xml
index d335c71a31..48e4ac8082 100644
--- a/src/cpu_map/x86_SandyBridge.xml
+++ b/src/cpu_map/x86_SandyBridge.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='SandyBridge'>
<signature family='6' model='42'/> <!-- 0206a0 -->
+ <signature family='6' model='45'/> <!-- 0206d0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
--
2.21.0
12:31 a.m.
New subject: [libvirt] [PATCH 22/26] cpu_map: Add more signatures for SandyBridge CPU models
On Wed, Feb 27, 2019 at 02:29:12PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
src/cpu_map/x86_SandyBridge.xml | 1 +
2 files changed, 2 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 23/26] cpu_map: Add more signatures for IvyBridge CPU models
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
src/cpu_map/x86_IvyBridge.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge-IBRS.xml
index 4a4bc0c97b..e0f2adfa82 100644
--- a/src/cpu_map/x86_IvyBridge-IBRS.xml
+++ b/src/cpu_map/x86_IvyBridge-IBRS.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='IvyBridge-IBRS'>
<signature family='6' model='58'/> <!-- 0306a0 -->
+ <signature family='6' model='62'/> <!-- 0306e0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml
index da4792595f..16213dbc62 100644
--- a/src/cpu_map/x86_IvyBridge.xml
+++ b/src/cpu_map/x86_IvyBridge.xml
@@ -1,6 +1,7 @@
<cpus>
<model name='IvyBridge'>
<signature family='6' model='58'/> <!-- 0306a0 -->
+ <signature family='6' model='62'/> <!-- 0306e0 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
--
2.21.0
12:31 a.m.
New subject: [libvirt] [PATCH 23/26] cpu_map: Add more signatures for IvyBridge CPU models
On Wed, Feb 27, 2019 at 02:29:13PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
src/cpu_map/x86_IvyBridge.xml | 1 +
2 files changed, 2 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 24/26] cpu_map: Add more signatures for Haswell CPU models
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Haswell-IBRS.xml | 3 +++
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 3 +++
src/cpu_map/x86_Haswell-noTSX.xml | 3 +++
src/cpu_map/x86_Haswell.xml | 3 +++
4 files changed, 12 insertions(+)
diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBRS.xml
index dea43ad71d..4f86db838f 100644
--- a/src/cpu_map/x86_Haswell-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-IBRS.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Haswell-IBRS'>
<signature family='6' model='60'/> <!-- 0306c0 -->
+ <signature family='6' model='63'/> <!-- 0306f0 -->
+ <signature family='6' model='69'/> <!-- 040650 -->
+ <signature family='6' model='70'/> <!-- 040660 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
index 7013540428..47318be6d5 100644
--- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Haswell-noTSX-IBRS'>
<signature family='6' model='60'/> <!-- 0306c0 -->
+ <signature family='6' model='63'/> <!-- 0306f0 -->
+ <signature family='6' model='69'/> <!-- 040650 -->
+ <signature family='6' model='70'/> <!-- 040660 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-noTSX.xml
index e183364f3b..efd10c47de 100644
--- a/src/cpu_map/x86_Haswell-noTSX.xml
+++ b/src/cpu_map/x86_Haswell-noTSX.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Haswell-noTSX'>
<signature family='6' model='60'/> <!-- 0306c0 -->
+ <signature family='6' model='63'/> <!-- 0306f0 -->
+ <signature family='6' model='69'/> <!-- 040650 -->
+ <signature family='6' model='70'/> <!-- 040660 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml
index eee98264b2..ac358d7967 100644
--- a/src/cpu_map/x86_Haswell.xml
+++ b/src/cpu_map/x86_Haswell.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Haswell'>
<signature family='6' model='60'/> <!-- 0306c0 -->
+ <signature family='6' model='63'/> <!-- 0306f0 -->
+ <signature family='6' model='69'/> <!-- 040650 -->
+ <signature family='6' model='70'/> <!-- 040660 -->
<vendor name='Intel'/>
<feature name='aes'/>
<feature name='apic'/>
--
2.21.0
12:32 a.m.
New subject: [libvirt] [PATCH 24/26] cpu_map: Add more signatures for Haswell CPU models
On Wed, Feb 27, 2019 at 02:29:14PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Haswell-IBRS.xml | 3 +++
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 3 +++
src/cpu_map/x86_Haswell-noTSX.xml | 3 +++
What do we have here?
src/cpu_map/x86_Haswell.xml | 3 +++
4 files changed, 12 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 25/26] cpu_map: Add more signatures for Broadwell CPU models
This fixes several CPUs which were incorrectly detected as
Skylake-Client.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Broadwell-IBRS.xml | 3 +++
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 3 +++
src/cpu_map/x86_Broadwell-noTSX.xml | 3 +++
src/cpu_map/x86_Broadwell.xml | 3 +++
.../x86_64-cpuid-Xeon-E5-2623-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml | 11 +++++++----
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 +++++++----
.../x86_64-cpuid-Xeon-E5-2650-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml | 11 +++++++----
10 files changed, 54 insertions(+), 24 deletions(-)
diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
index efaa5c9b70..4600cacec0 100644
--- a/src/cpu_map/x86_Broadwell-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-IBRS.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Broadwell-IBRS'>
<signature family='6' model='61'/> <!-- 0306d0 -->
+ <signature family='6' model='71'/> <!-- 040670 -->
+ <signature family='6' model='79'/> <!-- 0406f0 -->
+ <signature family='6' model='86'/> <!-- 050660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
index fb1cf55a4f..b3fc0b726a 100644
--- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Broadwell-noTSX-IBRS'>
<signature family='6' model='61'/> <!-- 0306d0 -->
+ <signature family='6' model='71'/> <!-- 040670 -->
+ <signature family='6' model='79'/> <!-- 0406f0 -->
+ <signature family='6' model='86'/> <!-- 050660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
index 8e9cff14ad..ad932d0853 100644
--- a/src/cpu_map/x86_Broadwell-noTSX.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Broadwell-noTSX'>
<signature family='6' model='61'/> <!-- 0306d0 -->
+ <signature family='6' model='71'/> <!-- 040670 -->
+ <signature family='6' model='79'/> <!-- 0406f0 -->
+ <signature family='6' model='86'/> <!-- 050660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
index a9850c9126..6de9227322 100644
--- a/src/cpu_map/x86_Broadwell.xml
+++ b/src/cpu_map/x86_Broadwell.xml
@@ -1,6 +1,9 @@
<cpus>
<model name='Broadwell'>
<signature family='6' model='61'/> <!-- 0306d0 -->
+ <signature family='6' model='71'/> <!-- 040670 -->
+ <signature family='6' model='79'/> <!-- 0406f0 -->
+ <signature family='6' model='86'/> <!-- 050660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='adx'/>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml
index 7718d7ca59..a5c6d9b471 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml
@@ -1,6 +1,7 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <model fallback='forbid'>Broadwell-IBRS</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
<feature policy='require' name='ss'/>
@@ -18,15 +19,17 @@
<feature policy='require' name='pdcm'/>
<feature policy='require' name='dca'/>
<feature policy='require' name='osxsave'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
<feature policy='require' name='cmt'/>
<feature policy='require' name='intel-pt'/>
<feature policy='require' name='stibp'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='mbm_total'/>
<feature policy='require' name='mbm_local'/>
<feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='abm'/>
<feature policy='require' name='invtsc'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml
index 167a9028ab..de082dbd93 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml
@@ -1,11 +1,14 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <model fallback='forbid'>Broadwell-IBRS</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
<feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='pdpe1gb'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
+ <feature policy='require' name='abm'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
index cd7e25b52a..e2999db8e9 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml
@@ -1,6 +1,7 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client</model>
+ <model fallback='forbid'>Broadwell</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
<feature policy='require' name='ss'/>
@@ -18,14 +19,16 @@
<feature policy='require' name='pdcm'/>
<feature policy='require' name='dca'/>
<feature policy='require' name='osxsave'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
<feature policy='require' name='cmt'/>
<feature policy='require' name='intel-pt'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='mbm_total'/>
<feature policy='require' name='mbm_local'/>
<feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='abm'/>
<feature policy='require' name='invtsc'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
index 5dfce947b2..5b8891093a 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml
@@ -1,11 +1,14 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client</model>
+ <model fallback='forbid'>Broadwell</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
<feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='pdpe1gb'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
+ <feature policy='require' name='abm'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml
index cd7e25b52a..e2999db8e9 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml
@@ -1,6 +1,7 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client</model>
+ <model fallback='forbid'>Broadwell</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
<feature policy='require' name='ss'/>
@@ -18,14 +19,16 @@
<feature policy='require' name='pdcm'/>
<feature policy='require' name='dca'/>
<feature policy='require' name='osxsave'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
<feature policy='require' name='cmt'/>
<feature policy='require' name='intel-pt'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='mbm_total'/>
<feature policy='require' name='mbm_local'/>
<feature policy='require' name='pdpe1gb'/>
+ <feature policy='require' name='abm'/>
<feature policy='require' name='invtsc'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml
b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml
index 5dfce947b2..5b8891093a 100644
--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml
@@ -1,11 +1,14 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client</model>
+ <model fallback='forbid'>Broadwell</model>
<vendor>Intel</vendor>
+ <feature policy='require' name='vme'/>
<feature policy='require' name='ss'/>
+ <feature policy='require' name='f16c'/>
+ <feature policy='require' name='rdrand'/>
<feature policy='require' name='hypervisor'/>
+ <feature policy='require' name='arat'/>
<feature policy='require' name='tsc_adjust'/>
+ <feature policy='require' name='xsaveopt'/>
<feature policy='require' name='pdpe1gb'/>
- <feature policy='disable' name='mpx'/>
- <feature policy='disable' name='xsavec'/>
- <feature policy='disable' name='xgetbv1'/>
+ <feature policy='require' name='abm'/>
</cpu>
--
2.21.0
12:32 a.m.
New subject: [libvirt] [PATCH 25/26] cpu_map: Add more signatures for Broadwell CPU models
On Wed, Feb 27, 2019 at 02:29:15PM +0100, Jiri Denemark wrote:
This fixes several CPUs which were incorrectly detected as
Skylake-Client.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Broadwell-IBRS.xml | 3 +++
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 3 +++
src/cpu_map/x86_Broadwell-noTSX.xml | 3 +++
src/cpu_map/x86_Broadwell.xml | 3 +++
.../x86_64-cpuid-Xeon-E5-2623-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml | 11 +++++++----
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 +++++++----
.../x86_64-cpuid-Xeon-E5-2650-v4-guest.xml | 11 +++++++----
.../cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml | 11 +++++++----
10 files changed, 54 insertions(+), 24 deletions(-)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
9:29 p.m.
New subject: [libvirt] [PATCH 26/26] cpu_map: Add more signatures for Skylake-Client CPU models
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Skylake-Client-IBRS.xml | 5 +++++
src/cpu_map/x86_Skylake-Client.xml | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-IBRS.xml
index c8e15ef974..4440313fc4 100644
--- a/src/cpu_map/x86_Skylake-Client-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml
@@ -1,6 +1,11 @@
<cpus>
<model name='Skylake-Client-IBRS'>
<signature family='6' model='94'/> <!-- 0506e0 -->
+ <signature family='6' model='78'/> <!-- 0406e0 -->
+ <!-- These are Kaby Lake and Coffee Lake successors to Skylake,
+ but we don't have specific models for them. -->
+ <signature family='6' model='142'/> <!-- 0806e0 -->
+ <signature family='6' model='158'/> <!-- 0906e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-Client.xml
index 1cfeb9196e..1053fa4a04 100644
--- a/src/cpu_map/x86_Skylake-Client.xml
+++ b/src/cpu_map/x86_Skylake-Client.xml
@@ -1,6 +1,11 @@
<cpus>
<model name='Skylake-Client'>
<signature family='6' model='94'/> <!-- 0506e0 -->
+ <signature family='6' model='78'/> <!-- 0406e0 -->
+ <!-- These are Kaby Lake and Coffee Lake successors to Skylake,
+ but we don't have specific models for them. -->
+ <signature family='6' model='142'/> <!-- 0806e0 -->
+ <signature family='6' model='158'/> <!-- 0906e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
<feature name='abm'/>
--
2.21.0
12:33 a.m.
New subject: [libvirt] [PATCH 26/26] cpu_map: Add more signatures for Skylake-Client CPU models
On Wed, Feb 27, 2019 at 02:29:16PM +0100, Jiri Denemark wrote:
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Skylake-Client-IBRS.xml | 5 +++++
src/cpu_map/x86_Skylake-Client.xml | 5 +++++
2 files changed, 10 insertions(+)
Reviewed-by: Ján Tomko <jtomko(a)redhat.com>
Jano
2017
days inactive
2019
days old
54 comments
2 participants
participants (2)
-
Jiri Denemark -
Ján Tomko