[PATCH v2] docs: Move RISC-V 'Z' CPU properties section to removed features
RISC-V 'Z' CPU properties were removed in commit 455c0fa9eef, for the release v10.1.0. Move the corresponding section from deprecated.rst to removed-features.rst, adjusting the wording accordingly. Fixes: 455c0fa9eef ("target/riscv: remove capital 'Z' CPU properties") Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> --- docs/about/deprecated.rst | 24 ------------------------ docs/about/removed-features.rst | 7 +++++++ 2 files changed, 7 insertions(+), 24 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ccbc4219497..368fa1b4ed3 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -349,30 +349,6 @@ the addition of volatile memory support, it is now necessary to distinguish between persistent and volatile memory backends. As such, memdev is deprecated in favor of persistent-memdev. - -RISC-V CPU properties which start with capital 'Z' (since 8.2) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -All RISC-V CPU properties which start with capital 'Z' are being deprecated -starting in 8.2. The reason is that they were wrongly added with capital 'Z' -in the past. CPU properties were later added with lower-case names, which -is the format we want to use from now on. - -Users which try to use these deprecated properties will receive a warning -recommending to switch to their stable counterparts: - -- "Zifencei" should be replaced with "zifencei" -- "Zicsr" should be replaced with "zicsr" -- "Zihintntl" should be replaced with "zihintntl" -- "Zihintpause" should be replaced with "zihintpause" -- "Zawrs" should be replaced with "zawrs" -- "Zfa" should be replaced with "zfa" -- "Zfh" should be replaced with "zfh" -- "Zfhmin" should be replaced with "zfhmin" -- "Zve32f" should be replaced with "zve32f" -- "Zve64f" should be replaced with "zve64f" -- "Zve64d" should be replaced with "zve64d" - Block device options '''''''''''''''''''' diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index 6a9944a0c79..225841bd9bb 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1038,6 +1038,13 @@ initial RISC-V QEMU port. Its usage was always been unclear: users don't know what to expect from a CPU called 'any', and in fact the CPU does not do anything special that isn't already done by the default CPUs rv32/rv64. +RISC-V CPU properties which start with capital 'Z' (removed in 10.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +All RISC-V CPU properties which start with capital 'Z' have been removed. +They were wrongly added with capital 'Z' in the past. CPU properties +with lower-case names are used instead. + Power8E and Power8NVL CPUs (removed in 11.1) '''''''''''''''''''''''''''''''''''''''''''' -- 2.55.0
On Tue, 20 Oct 2026 at 08:59, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
RISC-V 'Z' CPU properties were removed in commit 455c0fa9eef, for the release v10.1.0. Move the corresponding section from deprecated.rst to removed-features.rst, adjusting the wording accordingly.
Fixes: 455c0fa9eef ("target/riscv: remove capital 'Z' CPU properties") Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> --- docs/about/deprecated.rst | 24 ------------------------ docs/about/removed-features.rst | 7 +++++++ 2 files changed, 7 insertions(+), 24 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On Tue, 2026-10-20 at 09:59 +0200, Philippe Mathieu-Daudé wrote:
RISC-V 'Z' CPU properties were removed in commit 455c0fa9eef, for the release v10.1.0. Move the corresponding section from deprecated.rst to removed-features.rst, adjusting the wording accordingly.
Fixes: 455c0fa9eef ("target/riscv: remove capital 'Z' CPU properties") Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Thanks! Applied to riscv-to-apply.next Alistair
--- docs/about/deprecated.rst | 24 ------------------------ docs/about/removed-features.rst | 7 +++++++ 2 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ccbc4219497..368fa1b4ed3 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -349,30 +349,6 @@ the addition of volatile memory support, it is now necessary to distinguish between persistent and volatile memory backends. As such, memdev is deprecated in favor of persistent-memdev. - -RISC-V CPU properties which start with capital 'Z' (since 8.2) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -All RISC-V CPU properties which start with capital 'Z' are being deprecated -starting in 8.2. The reason is that they were wrongly added with capital 'Z' -in the past. CPU properties were later added with lower-case names, which -is the format we want to use from now on. - -Users which try to use these deprecated properties will receive a warning -recommending to switch to their stable counterparts: - -- "Zifencei" should be replaced with "zifencei" -- "Zicsr" should be replaced with "zicsr" -- "Zihintntl" should be replaced with "zihintntl" -- "Zihintpause" should be replaced with "zihintpause" -- "Zawrs" should be replaced with "zawrs" -- "Zfa" should be replaced with "zfa" -- "Zfh" should be replaced with "zfh" -- "Zfhmin" should be replaced with "zfhmin" -- "Zve32f" should be replaced with "zve32f" -- "Zve64f" should be replaced with "zve64f" -- "Zve64d" should be replaced with "zve64d" - Block device options '''''''''''''''''''' diff --git a/docs/about/removed-features.rst b/docs/about/removed- features.rst index 6a9944a0c79..225841bd9bb 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1038,6 +1038,13 @@ initial RISC-V QEMU port. Its usage was always been unclear: users don't know what to expect from a CPU called 'any', and in fact the CPU does not do anything special that isn't already done by the default CPUs rv32/rv64. +RISC-V CPU properties which start with capital 'Z' (removed in 10.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +All RISC-V CPU properties which start with capital 'Z' have been removed. +They were wrongly added with capital 'Z' in the past. CPU properties +with lower-case names are used instead. + Power8E and Power8NVL CPUs (removed in 11.1) ''''''''''''''''''''''''''''''''''''''''''''
participants (3)
-
Alistair Francis -
Peter Maydell -
Philippe Mathieu-Daudé