v1: - Remove ast2700a0-evb machine - Remove ast2700-a0 SOC - Remove GIC 128 - 136 for AST2700 A0 *** BLURB HERE *** Jamin Lin (4): hw/arm: Remove ast2700a0-evb machine hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC hw/intc/aspeed: Remove GIC 128 - 136 docs/specs/aspeed-intc: Remove GIC 128 - 136 docs/about/deprecated.rst | 8 -- docs/specs/aspeed-intc.rst | 93 ++++---------- hw/arm/aspeed.c | 28 +--- hw/arm/aspeed_ast27x0.c | 121 ++---------------- hw/intc/aspeed_intc.c | 49 +------ .../functional/aarch64/test_aspeed_ast2700.py | 12 -- 6 files changed, 39 insertions(+), 272 deletions(-) -- 2.43.0
The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- docs/about/deprecated.rst | 8 ------ hw/arm/aspeed.c | 28 +------------------ .../functional/aarch64/test_aspeed_ast2700.py | 12 -------- 3 files changed, 1 insertion(+), 47 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 5d1579dcf8..8a273e019a 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -305,14 +305,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node. -Arm ``ast2700a0-evb`` machine (since 10.1) -'''''''''''''''''''''''''''''''''''''''''' - -The ``ast2700a0-evb`` machine represents the first revision of the AST2700 -and serves as the initial engineering sample rather than a production version. -A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should -replace the older A0 version. - Mips ``mipssim`` machine (since 10.0) ''''''''''''''''''''''''''''''''''''' diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31bbe7701..e729edfe13 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1989,35 +1989,13 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc) TYPE_TMP105, 0x4d); } -static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - - mc->alias = "ast2700-evb"; - mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; - amc->soc_name = "ast2700-a0"; - amc->hw_strap1 = AST2700_EVB_HW_STRAP1; - amc->hw_strap2 = AST2700_EVB_HW_STRAP2; - amc->fmc_model = "w25q01jvq"; - amc->spi_model = "w25q512jv"; - amc->num_cs = 2; - amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; - amc->uart_default = ASPEED_DEV_UART12; - amc->i2c_init = ast2700_evb_i2c_init; - amc->vbootrom = true; - mc->auto_create_sdcard = true; - mc->default_ram_size = 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + mc->alias = "ast2700-evb"; mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; amc->soc_name = "ast2700-a1"; amc->hw_strap1 = AST2700_EVB_HW_STRAP1; @@ -2166,10 +2144,6 @@ static const TypeInfo aspeed_machine_types[] = { .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, #ifdef TARGET_AARCH64 }, { - .name = MACHINE_TYPE_NAME("ast2700a0-evb"), - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_ast2700a0_evb_class_init, - }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py index d02dc7991c..063d9e572c 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -46,10 +46,6 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#') - ASSET_SDK_V906_AST2700 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-a...', - '7247b6f19dbfb700686f8d9f723ac23f3eb229226c0589cb9b06b80d1b61f3cb') - ASSET_SDK_V906_AST2700A1 = Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-d...', 'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9dc6') @@ -111,14 +107,6 @@ def start_ast2700_test_vbootrom(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) - def test_aarch64_ast2700_evb_sdk_v09_06(self): - self.set_machine('ast2700-evb') - - self.archive_extract(self.ASSET_SDK_V906_AST2700) - self.start_ast2700_test('ast2700-a0-default') - self.verify_openbmc_boot_and_login('ast2700-a0-default') - self.do_ast2700_i2c_test() - def test_aarch64_ast2700a1_evb_sdk_v09_06(self): self.set_machine('ast2700a1-evb') -- 2.43.0
Hello Jamin, On 9/1/25 06:08, Jamin Lin wrote:
The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- docs/about/deprecated.rst | 8 ------ hw/arm/aspeed.c | 28 +------------------ .../functional/aarch64/test_aspeed_ast2700.py | 12 -------- 3 files changed, 1 insertion(+), 47 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 5d1579dcf8..8a273e019a 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -305,14 +305,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node.
-Arm ``ast2700a0-evb`` machine (since 10.1) -''''''''''''''''''''''''''''''''''''''''''
We need to wait *two* releases after deprecation before removing a machine or any other feature. So removal of the ast2700a0-evb machine will be possible for QEMU 11.0 (next after QEMU 10.2).
- -The ``ast2700a0-evb`` machine represents the first revision of the AST2700 -and serves as the initial engineering sample rather than a production version. -A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should -replace the older A0 version. -
File docs/about/removed-features.rst should be updated too.
Mips ``mipssim`` machine (since 10.0) '''''''''''''''''''''''''''''''''''''
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31bbe7701..e729edfe13 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1989,35 +1989,13 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc) TYPE_TMP105, 0x4d); }
-static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - - mc->alias = "ast2700-evb";
The "ast2700-evb" alias should be moved first to the ast2700a1_evb machine. This can be done in this QEMU cycle Thanks, C.
- mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; - amc->soc_name = "ast2700-a0"; - amc->hw_strap1 = AST2700_EVB_HW_STRAP1; - amc->hw_strap2 = AST2700_EVB_HW_STRAP2; - amc->fmc_model = "w25q01jvq"; - amc->spi_model = "w25q512jv"; - amc->num_cs = 2; - amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; - amc->uart_default = ASPEED_DEV_UART12; - amc->i2c_init = ast2700_evb_i2c_init; - amc->vbootrom = true; - mc->auto_create_sdcard = true; - mc->default_ram_size = 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+ mc->alias = "ast2700-evb"; mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; amc->soc_name = "ast2700-a1"; amc->hw_strap1 = AST2700_EVB_HW_STRAP1; @@ -2166,10 +2144,6 @@ static const TypeInfo aspeed_machine_types[] = { .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, #ifdef TARGET_AARCH64 }, { - .name = MACHINE_TYPE_NAME("ast2700a0-evb"), - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_ast2700a0_evb_class_init, - }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py index d02dc7991c..063d9e572c 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -46,10 +46,6 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- ASSET_SDK_V906_AST2700 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-a...', - '7247b6f19dbfb700686f8d9f723ac23f3eb229226c0589cb9b06b80d1b61f3cb') - ASSET_SDK_V906_AST2700A1 = Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-d...', 'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9dc6') @@ -111,14 +107,6 @@ def start_ast2700_test_vbootrom(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700_evb_sdk_v09_06(self): - self.set_machine('ast2700-evb') - - self.archive_extract(self.ASSET_SDK_V906_AST2700) - self.start_ast2700_test('ast2700-a0-default') - self.verify_openbmc_boot_and_login('ast2700-a0-default') - self.do_ast2700_i2c_test() - def test_aarch64_ast2700a1_evb_sdk_v09_06(self): self.set_machine('ast2700a1-evb')
Hi Cédric
From: Cédric Le Goater <clg@kaod.org> Sent: Monday, September 1, 2025 4:28 PM To: Jamin Lin <jamin_lin@aspeedtech.com>; reviewer:Incompatible changes <devel@lists.libvirt.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open list:All patches CC here <qemu-devel@nongnu.org>; open list:ASPEED BMCs <qemu-arm@nongnu.org> Cc: Troy Lee <troy_lee@aspeedtech.com>; Kane Chen <kane_chen@aspeedtech.com> Subject: Re: [SPAM] [PATCH v1 1/4] hw/arm: Remove ast2700a0-evb machine
Hello Jamin,
On 9/1/25 06:08, Jamin Lin wrote:
The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- docs/about/deprecated.rst | 8 ------ hw/arm/aspeed.c | 28 +------------------ .../functional/aarch64/test_aspeed_ast2700.py | 12 -------- 3 files changed, 1 insertion(+), 47 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 5d1579dcf8..8a273e019a 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -305,14 +305,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node.
-Arm ``ast2700a0-evb`` machine (since 10.1) -''''''''''''''''''''''''''''''''''''''''''
We need to wait *two* releases after deprecation before removing a machine or any other feature. So removal of the ast2700a0-evb machine will be possible for QEMU 11.0 (next after QEMU 10.2).
Got it. Thanks for review.
- -The ``ast2700a0-evb`` machine represents the first revision of the AST2700 -and serves as the initial engineering sample rather than a production version. -A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should -replace the older A0 version. -
File docs/about/removed-features.rst should be updated too.
Mips ``mipssim`` machine (since 10.0) '''''''''''''''''''''''''''''''''''''
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c31bbe7701..e729edfe13 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1989,35 +1989,13 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc) TYPE_TMP105, 0x4d); }
-static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - - mc->alias = "ast2700-evb";
The "ast2700-evb" alias should be moved first to the ast2700a1_evb machine. This can be done in this QEMU cycle
Will do. Thanks-Jamin
Thanks,
C.
- mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; - amc->soc_name = "ast2700-a0"; - amc->hw_strap1 = AST2700_EVB_HW_STRAP1; - amc->hw_strap2 = AST2700_EVB_HW_STRAP2; - amc->fmc_model = "w25q01jvq"; - amc->spi_model = "w25q512jv"; - amc->num_cs = 2; - amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; - amc->uart_default = ASPEED_DEV_UART12; - amc->i2c_init = ast2700_evb_i2c_init; - amc->vbootrom = true; - mc->auto_create_sdcard = true; - mc->default_ram_size = 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+ mc->alias = "ast2700-evb"; mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; amc->soc_name = "ast2700-a1"; amc->hw_strap1 = AST2700_EVB_HW_STRAP1; @@ -2166,10 +2144,6 @@ static const TypeInfo aspeed_machine_types[] = { .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, #ifdef TARGET_AARCH64 }, { - .name = MACHINE_TYPE_NAME("ast2700a0-evb"), - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_ast2700a0_evb_class_init, - }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700.py index d02dc7991c..063d9e572c 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -46,10 +46,6 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- ASSET_SDK_V906_AST2700 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast 2700-a0-default-obmc.tar.gz', - '7247b6f19dbfb700686f8d9f723ac23f3eb229226c0589cb9b06b80d1b61f3cb') - ASSET_SDK_V906_AST2700A1 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast 2700-default-obmc.tar.gz',
'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9dc6')
@@ -111,14 +107,6 @@ def start_ast2700_test_vbootrom(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700_evb_sdk_v09_06(self): - self.set_machine('ast2700-evb') - - self.archive_extract(self.ASSET_SDK_V906_AST2700) - self.start_ast2700_test('ast2700-a0-default') - self.verify_openbmc_boot_and_login('ast2700-a0-default') - self.do_ast2700_i2c_test() - def test_aarch64_ast2700a1_evb_sdk_v09_06(self): self.set_machine('ast2700a1-evb')
The ast2700-a1 SOC represented the first revision of the AST2700 and was intended as an early engineering sample rather than a production platform. A newer revision, A1, is now supported, and the ast2700-a1 SOC should replace the older A0 version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/arm/aspeed_ast27x0.c | 81 ----------------------------------------- 1 file changed, 81 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..2e47e2f860 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -89,54 +89,6 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { #define AST2700_MAX_IRQ 256 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ -static const int aspeed_soc_ast2700a0_irqmap[] = { - [ASPEED_DEV_SDMC] = 0, - [ASPEED_DEV_HACE] = 4, - [ASPEED_DEV_XDMA] = 5, - [ASPEED_DEV_UART4] = 8, - [ASPEED_DEV_SCU] = 12, - [ASPEED_DEV_RTC] = 13, - [ASPEED_DEV_EMMC] = 15, - [ASPEED_DEV_TIMER1] = 16, - [ASPEED_DEV_TIMER2] = 17, - [ASPEED_DEV_TIMER3] = 18, - [ASPEED_DEV_TIMER4] = 19, - [ASPEED_DEV_TIMER5] = 20, - [ASPEED_DEV_TIMER6] = 21, - [ASPEED_DEV_TIMER7] = 22, - [ASPEED_DEV_TIMER8] = 23, - [ASPEED_DEV_DP] = 28, - [ASPEED_DEV_EHCI1] = 33, - [ASPEED_DEV_EHCI2] = 37, - [ASPEED_DEV_LPC] = 128, - [ASPEED_DEV_IBT] = 128, - [ASPEED_DEV_KCS] = 128, - [ASPEED_DEV_ADC] = 130, - [ASPEED_DEV_GPIO] = 130, - [ASPEED_DEV_I2C] = 130, - [ASPEED_DEV_FMC] = 131, - [ASPEED_DEV_WDT] = 131, - [ASPEED_DEV_PWM] = 131, - [ASPEED_DEV_I3C] = 131, - [ASPEED_DEV_UART0] = 132, - [ASPEED_DEV_UART1] = 132, - [ASPEED_DEV_UART2] = 132, - [ASPEED_DEV_UART3] = 132, - [ASPEED_DEV_UART5] = 132, - [ASPEED_DEV_UART6] = 132, - [ASPEED_DEV_UART7] = 132, - [ASPEED_DEV_UART8] = 132, - [ASPEED_DEV_UART9] = 132, - [ASPEED_DEV_UART10] = 132, - [ASPEED_DEV_UART11] = 132, - [ASPEED_DEV_UART12] = 132, - [ASPEED_DEV_ETH1] = 132, - [ASPEED_DEV_ETH2] = 132, - [ASPEED_DEV_ETH3] = 132, - [ASPEED_DEV_PECI] = 133, - [ASPEED_DEV_SDHCI] = 133, -}; - static const int aspeed_soc_ast2700a1_irqmap[] = { [ASPEED_DEV_SDMC] = 0, [ASPEED_DEV_HACE] = 4, @@ -958,34 +910,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) AST2700_SOC_IOMEM_SIZE); } -static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) -{ - static const char * const valid_cpu_types[] = { - ARM_CPU_TYPE_NAME("cortex-a35"), - NULL - }; - DeviceClass *dc = DEVICE_CLASS(oc); - AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); - - /* Reason: The Aspeed SoC can only be instantiated from a board */ - dc->user_creatable = false; - dc->realize = aspeed_soc_ast2700_realize; - - sc->valid_cpu_types = valid_cpu_types; - sc->silicon_rev = AST2700_A0_SILICON_REV; - sc->sram_size = 0x20000; - sc->spis_num = 3; - sc->ehcis_num = 2; - sc->wdts_num = 8; - sc->macs_num = 1; - sc->uarts_num = 13; - sc->num_cpus = 4; - sc->uarts_base = ASPEED_DEV_UART0; - sc->irqmap = aspeed_soc_ast2700a0_irqmap; - sc->memmap = aspeed_soc_ast2700_memmap; - sc->get_irq = aspeed_soc_ast2700_get_irq; -} - static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) { static const char * const valid_cpu_types[] = { @@ -1020,11 +944,6 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = { .parent = TYPE_ASPEED_SOC, .instance_size = sizeof(Aspeed27x0SoCState), .abstract = true, - }, { - .name = "ast2700-a0", - .parent = TYPE_ASPEED27X0_SOC, - .instance_init = aspeed_soc_ast2700_init, - .class_init = aspeed_soc_ast2700a0_class_init, }, { .name = "ast2700-a1", -- 2.43.0
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/arm/aspeed_ast27x0.c | 40 +++++++++------------------------ hw/intc/aspeed_intc.c | 49 +---------------------------------------- 2 files changed, 12 insertions(+), 77 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2e47e2f860..b0b6849fbb 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -137,37 +137,32 @@ static const int aspeed_soc_ast2700a1_irqmap[] = { [ASPEED_DEV_SDHCI] = 197, }; -/* GICINT 128 */ /* GICINT 192 */ -static const int ast2700_gic128_gic192_intcmap[] = { +static const int ast2700_gic192_intcmap[] = { [ASPEED_DEV_LPC] = 0, [ASPEED_DEV_IBT] = 2, [ASPEED_DEV_KCS] = 4, }; -/* GICINT 129 */ /* GICINT 193 */ -/* GICINT 130 */ /* GICINT 194 */ -static const int ast2700_gic130_gic194_intcmap[] = { +static const int ast2700_gic194_intcmap[] = { [ASPEED_DEV_I2C] = 0, [ASPEED_DEV_ADC] = 16, [ASPEED_DEV_GPIO] = 18, }; -/* GICINT 131 */ /* GICINT 195 */ -static const int ast2700_gic131_gic195_intcmap[] = { +static const int ast2700_gic195_intcmap[] = { [ASPEED_DEV_I3C] = 0, [ASPEED_DEV_WDT] = 16, [ASPEED_DEV_FMC] = 25, [ASPEED_DEV_PWM] = 29, }; -/* GICINT 132 */ /* GICINT 196 */ -static const int ast2700_gic132_gic196_intcmap[] = { +static const int ast2700_gic196_intcmap[] = { [ASPEED_DEV_ETH1] = 0, [ASPEED_DEV_ETH2] = 1, [ASPEED_DEV_ETH3] = 2, @@ -187,14 +182,12 @@ static const int ast2700_gic132_gic196_intcmap[] = { [ASPEED_DEV_EHCI4] = 29, }; -/* GICINT 133 */ /* GICINT 197 */ -static const int ast2700_gic133_gic197_intcmap[] = { +static const int ast2700_gic197_intcmap[] = { [ASPEED_DEV_SDHCI] = 1, [ASPEED_DEV_PECI] = 4, }; -/* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; @@ -204,25 +197,16 @@ struct gic_intc_irq_info { }; static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { - {192, 1, 0, ast2700_gic128_gic192_intcmap}, + {192, 1, 0, ast2700_gic192_intcmap}, {193, 1, 1, NULL}, - {194, 1, 2, ast2700_gic130_gic194_intcmap}, - {195, 1, 3, ast2700_gic131_gic195_intcmap}, - {196, 1, 4, ast2700_gic132_gic196_intcmap}, - {197, 1, 5, ast2700_gic133_gic197_intcmap}, + {194, 1, 2, ast2700_gic194_intcmap}, + {195, 1, 3, ast2700_gic195_intcmap}, + {196, 1, 4, ast2700_gic196_intcmap}, + {197, 1, 5, ast2700_gic197_intcmap}, {198, 1, 6, NULL}, {199, 1, 7, NULL}, {200, 1, 8, NULL}, {201, 1, 9, NULL}, - {128, 0, 1, ast2700_gic128_gic192_intcmap}, - {129, 0, 2, NULL}, - {130, 0, 3, ast2700_gic130_gic194_intcmap}, - {131, 0, 4, ast2700_gic131_gic195_intcmap}, - {132, 0, 5, ast2700_gic132_gic196_intcmap}, - {133, 0, 6, ast2700_gic133_gic197_intcmap}, - {134, 0, 7, NULL}, - {135, 0, 8, NULL}, - {136, 0, 9, NULL}, }; static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) @@ -266,8 +250,7 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, } /* - * Invalid OR gate index, device IRQ should be between 128 to 136 - * and 192 to 201. + * Invalid OR gate index, device IRQ should be between 192 to 201. */ g_assert_not_reached(); } @@ -622,7 +605,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) } /* INTC -> GIC192 - GIC201 */ - /* INTC -> GIC128 - GIC136 */ for (i = 0; i < ic->num_outpins; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, qdev_get_gpio_in(DEVICE(&a->gic), diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5cd786dee6..d003566762 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -21,24 +21,6 @@ * because its memory region is start at 0x1000 * */ -REG32(GICINT128_EN, 0x000) -REG32(GICINT128_STATUS, 0x004) -REG32(GICINT129_EN, 0x100) -REG32(GICINT129_STATUS, 0x104) -REG32(GICINT130_EN, 0x200) -REG32(GICINT130_STATUS, 0x204) -REG32(GICINT131_EN, 0x300) -REG32(GICINT131_STATUS, 0x304) -REG32(GICINT132_EN, 0x400) -REG32(GICINT132_STATUS, 0x404) -REG32(GICINT133_EN, 0x500) -REG32(GICINT133_STATUS, 0x504) -REG32(GICINT134_EN, 0x600) -REG32(GICINT134_STATUS, 0x604) -REG32(GICINT135_EN, 0x700) -REG32(GICINT135_STATUS, 0x704) -REG32(GICINT136_EN, 0x800) -REG32(GICINT136_STATUS, 0x804) REG32(GICINT192_201_EN, 0xB00) REG32(GICINT192_201_STATUS, 0xB04) @@ -507,29 +489,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data, trace_aspeed_intc_write(name, offset, size, data); switch (reg) { - case R_GICINT128_EN: - case R_GICINT129_EN: - case R_GICINT130_EN: - case R_GICINT131_EN: - case R_GICINT132_EN: - case R_GICINT133_EN: - case R_GICINT134_EN: - case R_GICINT135_EN: - case R_GICINT136_EN: case R_GICINT192_201_EN: aspeed_intc_enable_handler(s, offset, data); break; - case R_GICINT128_STATUS: - case R_GICINT129_STATUS: - case R_GICINT130_STATUS: - case R_GICINT131_STATUS: - case R_GICINT132_STATUS: - case R_GICINT133_STATUS: - case R_GICINT134_STATUS: - case R_GICINT135_STATUS: - case R_GICINT136_STATUS: - aspeed_intc_status_handler(s, offset, data); - break; case R_GICINT192_201_STATUS: aspeed_intc_status_handler_multi_outpins(s, offset, data); break; @@ -891,15 +853,6 @@ static const TypeInfo aspeed_intc_info = { static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] = { {0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS}, - {1, 10, 1, R_GICINT128_EN, R_GICINT128_STATUS}, - {2, 11, 1, R_GICINT129_EN, R_GICINT129_STATUS}, - {3, 12, 1, R_GICINT130_EN, R_GICINT130_STATUS}, - {4, 13, 1, R_GICINT131_EN, R_GICINT131_STATUS}, - {5, 14, 1, R_GICINT132_EN, R_GICINT132_STATUS}, - {6, 15, 1, R_GICINT133_EN, R_GICINT133_STATUS}, - {7, 16, 1, R_GICINT134_EN, R_GICINT134_STATUS}, - {8, 17, 1, R_GICINT135_EN, R_GICINT135_STATUS}, - {9, 18, 1, R_GICINT136_EN, R_GICINT136_STATUS}, }; static void aspeed_2700_intc_class_init(ObjectClass *klass, const void *data) @@ -910,7 +863,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, const void *data) dc->desc = "ASPEED 2700 INTC Controller"; aic->num_lines = 32; aic->num_inpins = 10; - aic->num_outpins = 19; + aic->num_outpins = 10; aic->mem_size = 0x4000; aic->nr_regs = 0xB08 >> 2; aic->reg_offset = 0x1000; -- 2.43.0
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- docs/specs/aspeed-intc.rst | 93 +++++++++++--------------------------- 1 file changed, 26 insertions(+), 67 deletions(-) diff --git a/docs/specs/aspeed-intc.rst b/docs/specs/aspeed-intc.rst index 9cefd7f37f..c0a4b4d150 100644 --- a/docs/specs/aspeed-intc.rst +++ b/docs/specs/aspeed-intc.rst @@ -47,18 +47,7 @@ Bit GIC 9 201 ==== ==== -AST2700 A0 ----------- -It has only one INTC controller, and currently, only GIC 128-136 is supported. -To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the INTC, -with gates 1 to 9 supporting GIC 128-136. - -Design for GICINT 132 ---------------------- -The orgate has interrupt sources ranging from 0 to 31, with its output pin -connected to INTC. The output pin is then connected to GIC 132. - -Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 +Block Diagram of GICINT 196 for AST2700 A1 ------------------------------------------------------------------------ .. code-block:: @@ -68,69 +57,39 @@ Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 | To GICINT196 | | | | ETH1 |-----------| |--------------------------| |--------------| | - | -------->|0 | | INTCIO | | orgates[0] | | + | ------->|0 | | INTCIO | | orgates[0] | | | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | - | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | + | ------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | - | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | + | ------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | - | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | + | ------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | - | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | + | ------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | - | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | + | ------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | | UART3 | 26| |--------------------------| |--------------| | | - | ---------|10 27| | | + | ------->|10 27| | | | UART5 | 28| | | - | -------->|11 29| | | + | ------->|11 29| | | | UART6 | | | | - | -------->|12 30| |-----------------------------------------------------------------------| | + | ------->|12 30| |-----------------------------------------------------------------------| | | UART7 | 31| | | - | -------->|13 | | | - | UART8 | OR[0:31] | | |------------------------------| |----------| | - | -------->|14 | | | INTC | | GIC | | - | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | | - | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | | - | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | | - | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | | - | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | | - | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | | - | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | | - | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | | - | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | | - | |inpin[0:9]--------->outpin[9] |---------->|201 | | - |-------------------------------------------------------------------------------------------------------| - |-------------------------------------------------------------------------------------------------------| - | ETH1 |-----------| orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | | - | -------->|0 | orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | | - | ETH2 | 4| orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | | - | -------->|1 5| orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | | - | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132 | | - | -------->|2 19| orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | | - | UART0 | 20| orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | | - | -------->|7 21| orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | | - | UART1 | 22| orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | | - | -------->|8 23| |------------------------------| |----------| | - | UART2 | 24| | - | -------->|9 25| AST2700 A0 Design | - | UART3 | 26| | - | -------->|10 27| | - | UART5 | 28| | - | -------->|11 29| GICINT132 | - | UART6 | | | - | -------->|12 30| | - | UART7 | 31| | - | -------->|13 | | - | UART8 | OR[0:31] | | - | -------->|14 | | - | UART9 | | | - | -------->|15 | | - | UART10 | | | - | -------->|16 | | - | UART11 | | | - | -------->|17 | | - | UART12 | | | - | -------->|18 | | - | |-----------| | + | ------->|13 | | | + | UART8 | OR[0:31] | | |-----------------------------| |----------| | + | ------->|14 | | | INTC | | GIC | | + | UART9 | | | |inpin[0:0]--------->outpin[0]|--------->|192 | | + | ------->|15 | | |inpin[0:1]--------->outpin[1]|--------->|193 | | + | UART10 | | | |inpin[0:2]--------->outpin[2]|--------->|194 | | + | ------->|16 | | |inpin[0:3]--------->outpin[3]|--------->|195 | | + | UART11 | | |--------------> |inpin[0:4]--------->outpin[4]|--------->|196 | | + | ------->|17 | |inpin[0:5]--------->outpin[5]|--------->|197 | | + | UART12 | | |inpin[0:6]--------->outpin[6]|--------->|198 | | + | ------->|18 | |inpin[0:7]--------->outpin[7]|--------->|199 | | + | |-----------| |inpin[0:8]--------->outpin[8]|--------->|200 | | + | |inpin[0:9]--------->outpin[9]|--------->|201 | | + | |-----------------------------| |----------| | + | | | | |-------------------------------------------------------------------------------------------------------| + -- 2.43.0
participants (2)
-
Cédric Le Goater -
Jamin Lin