4:21 p.m.
The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' into
staging (2021-01-06 22:18:36 +0000)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210107
for you to fetch changes up to f97d339d612b86d8d336a11f01719a10893d6707:
docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-07 22:57:49
+0100)
----------------------------------------------------------------
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
----------------------------------------------------------------
Jiaxun Yang (1):
target/mips/addr: Add translation helpers for KSEG1
Philippe Mathieu-Daudé (65):
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
target/mips: Replace CP0_Config0 magic values by proper definitions
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
target/mips/mips-defs: Reorder CPU_MIPS5 definition
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
target/mips: Extract FPU helpers to 'fpu_helper.h'
target/mips: Add !CONFIG_USER_ONLY comment after #endif
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
target/mips: Move common helpers from helper.c to cpu.c
target/mips: Rename helper.c as tlb_helper.c
target/mips: Fix code style for checkpatch.pl
target/mips: Move mmu_init() functions to tlb_helper.c
target/mips: Rename translate_init.c as cpu-defs.c
target/mips/translate: Extract DisasContext structure
target/mips/translate: Add declarations for generic code
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
target/mips: Replace gen_exception_end(EXCP_RI) by
gen_rsvd_instruction
target/mips: Declare generic FPU functions in 'translate.h'
target/mips: Extract FPU specific definitions to translate.h
target/mips: Only build TCG code when CONFIG_TCG is set
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
target/mips/translate: Expose check_mips_64() to 32-bit mode
target/mips: Introduce ase_msa_available() helper
target/mips: Simplify msa_reset()
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
target/mips: Simplify MSA TCG logic
target/mips: Remove now unused ASE_MSA definition
target/mips: Alias MSA vector registers on FPU scalar registers
target/mips: Extract msa_translate_init() from mips_tcg_init()
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
target/mips: Move msa_reset() to msa_helper.c
target/mips: Extract MSA helpers from op_helper.c
target/mips: Extract MSA helper definitions
target/mips: Declare gen_msa/_branch() in 'translate.h'
target/mips: Extract MSA translation routines
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
target/mips: Introduce decode tree bindings for MSA ASE
target/mips: Use decode_ase_msa() generated from decodetree
target/mips: Extract LSA/DLSA translation generators
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA
opcodes
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LL/SC opcodes to decodetree
docs/system: Remove deprecated 'fulong2e' machine alias
docs/system/deprecated.rst | 5 -
docs/system/removed-features.rst | 5 +
target/mips/cpu.h | 23 +-
target/mips/fpu_helper.h | 59 +
target/mips/helper.h | 436 +-
target/mips/internal.h | 64 +-
target/mips/mips-defs.h | 47 +-
target/mips/translate.h | 168 +
target/mips/msa_helper.h.inc | 443 ++
target/mips/mips32r6.decode | 36 +
target/mips/mips64r6.decode | 26 +
target/mips/msa32.decode | 28 +
target/mips/msa64.decode | 17 +
hw/mips/boston.c | 6 +-
hw/mips/fuloong2e.c | 1 -
linux-user/mips/cpu_loop.c | 7 +-
target/mips/addr.c | 10 +
target/mips/cp0_helper.c | 18 +-
target/mips/cp0_timer.c | 4 +-
target/mips/cpu.c | 255 +-
target/mips/fpu_helper.c | 5 +-
target/mips/gdbstub.c | 1 +
target/mips/kvm.c | 13 +-
target/mips/machine.c | 1 +
target/mips/msa_helper.c | 430 ++
target/mips/msa_translate.c | 2286 ++++++++++
target/mips/op_helper.c | 396 +-
target/mips/rel6_translate.c | 44 +
target/mips/{helper.c => tlb_helper.c} | 266 +-
target/mips/translate.c | 3839 +++--------------
target/mips/translate_addr_const.c | 61 +
.../{translate_init.c.inc => cpu-defs.c.inc} | 114 +-
target/mips/meson.build | 21 +-
33 files changed, 4727 insertions(+), 4408 deletions(-)
create mode 100644 target/mips/fpu_helper.h
create mode 100644 target/mips/translate.h
create mode 100644 target/mips/msa_helper.h.inc
create mode 100644 target/mips/mips32r6.decode
create mode 100644 target/mips/mips64r6.decode
create mode 100644 target/mips/msa32.decode
create mode 100644 target/mips/msa64.decode
create mode 100644 target/mips/msa_translate.c
create mode 100644 target/mips/rel6_translate.c
rename target/mips/{helper.c => tlb_helper.c} (87%)
create mode 100644 target/mips/translate_addr_const.c
rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%)
--
2.26.2
4:21 p.m.
New subject: [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug(a)amsat.org>
---
target/mips/cpu.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4cbc31c3e8d..0086f95ea2a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -828,7 +828,7 @@ struct CPUMIPSState {
#define CP0EBase_WG 11
target_ulong CP0_CMGCRBase;
/*
- * CP0 Register 16
+ * CP0 Register 16 (after Release 1)
*/
int32_t CP0_Config0;
#define CP0C0_M 31
@@ -845,6 +845,14 @@ struct CPUMIPSState {
#define CP0C0_VI 3
#define CP0C0_K0 0 /* 2..0 */
#define CP0C0_AR_LENGTH 3
+/*
+ * CP0 Register 16 (before Release 1)
+ */
+#define CP0C0_Impl 16 /* 24..16 */
+#define CP0C0_IC 9 /* 11..9 */
+#define CP0C0_DC 6 /* 8..6 */
+#define CP0C0_IB 5
+#define CP0C0_DB 4
int32_t CP0_Config1;
#define CP0C1_M 31
#define CP0C1_MMU 25 /* 30..25 */
--
2.26.2
4:21 p.m.
New subject: [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201201132817.2863301-3-f4bug(a)amsat.org>
---
target/mips/translate_init.c.inc | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f72fee3b40a..cac3d241831 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -495,7 +495,8 @@ const mips_def_t mips_defs[] =
.name = "R4000",
.CP0_PRid = 0x00000400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2
<< CP0C0_K0),
+ .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 <<
CP0C0_DC) |
+ (2 << CP0C0_K0),
/* Note: Config1 is only used internally, the R4000 has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
@@ -516,7 +517,8 @@ const mips_def_t mips_defs[] =
.name = "VR5432",
.CP0_PRid = 0x00005400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2
<< CP0C0_K0),
+ .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 <<
CP0C0_DC) |
+ (2 << CP0C0_K0),
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
.CP0_LLAddr_shift = 4,
@@ -766,8 +768,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) |
(0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
+ .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 <<
CP0C0_DC) |
+ (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 <<
CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2E has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
@@ -786,8 +788,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2F",
.CP0_PRid = 0x6303,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) |
(0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
+ .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 <<
CP0C0_DC) |
+ (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 <<
CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2F has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
--
2.26.2
4:21 p.m.
New subject: [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1
From: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
It's useful for bootloader to do I/O operations.
Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Huacai Chen <chenhuacai(a)kernel.org>
Message-Id: <20201215064507.30148-3-jiaxun.yang(a)flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
---
target/mips/cpu.h | 2 ++
target/mips/addr.c | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 0086f95ea2a..0c2d397e4a9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1312,6 +1312,8 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
bool mips_um_ksegs_enabled(void);
void mips_um_ksegs_enable(void);
diff --git a/target/mips/addr.c b/target/mips/addr.c
index 27a6036c451..86f1c129c9f 100644
--- a/target/mips/addr.c
+++ b/target/mips/addr.c
@@ -40,6 +40,16 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
return addr | 0x40000000ll;
}
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr)
+{
+ return addr & 0x1fffffffll;
+}
+
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr)
+{
+ return (addr & 0x1fffffffll) | 0xffffffffa0000000ll;
+}
+
bool mips_um_ksegs_enabled(void)
{
return mips_um_ksegs;
--
2.26.2
4:21 p.m.
New subject: [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20210104221154.3127610-2-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..555e165fb01 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -1,12 +1,6 @@
#ifndef QEMU_MIPS_DEFS_H
#define QEMU_MIPS_DEFS_H
-/*
- * If we want to use host float regs...
- *
- * #define USE_HOST_FLOAT_REGS
- */
-
/* Real pages are variable size... */
#define MIPS_TLB_MAX 128
--
2.26.2
4:21 p.m.
New subject: [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-3-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 555e165fb01..48544ba73b4 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -65,13 +65,12 @@
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
+#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
-#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
--
2.26.2
4:21 p.m.
New subject: [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 8 ++++----
target/mips/translate_init.c.inc | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 48544ba73b4..1630ae20d59 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -72,12 +72,12 @@
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
+#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
+#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index cac3d241831..0ba3cf18ef7 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -72,7 +72,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -94,7 +94,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -114,7 +114,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -134,7 +134,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -552,7 +552,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -578,7 +578,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -607,7 +607,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 36,
- .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
4:21 p.m.
New subject: [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20210104221154.3127610-5-f4bug(a)amsat.org>
---
target/mips/cpu.h | 5 +++++
target/mips/mips-defs.h | 4 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 0c2d397e4a9..9c45744c5c1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1305,6 +1305,11 @@ static inline bool ase_mt_available(CPUMIPSState *env)
return env->CP0_Config3 & (1 << CP0C3_MT);
}
+static inline bool cpu_type_is_64bit(const char *cpu_type)
+{
+ return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
+}
+
void cpu_set_exception_base(int vp_index, target_ulong address);
/* addr.c */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 1630ae20d59..89a9a4dda31 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -13,7 +13,7 @@
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
-#define ISA_MIPS3 0x0000000000000004ULL
+#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
@@ -71,6 +71,8 @@
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
+#define CPU_MIPS64 (ISA_MIPS3)
+
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
--
2.26.2
4:21 p.m.
New subject: [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20210104221154.3127610-6-f4bug(a)amsat.org>
---
hw/mips/boston.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index c3b94c68e1b..467fbc1c8be 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -444,7 +444,6 @@ static void boston_mach_init(MachineState *machine)
DriveInfo *hd[6];
Chardev *chr;
int fw_size, fit_err;
- bool is_64b;
if ((machine->ram_size % GiB) ||
(machine->ram_size > (2 * GiB))) {
@@ -463,8 +462,6 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
- is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64);
-
object_initialize_child(OBJECT(machine), "cps", &s->cps,
TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type",
machine->cpu_type,
&error_fatal);
@@ -545,7 +542,8 @@ static void boston_mach_init(MachineState *machine)
}
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
- s->kernel_entry, s->fdt_base, is_64b);
+ s->kernel_entry, s->fdt_base,
+ cpu_type_is_64bit(machine->cpu_type));
} else if (!qtest_enabled()) {
error_report("Please provide either a -kernel or -bios argument");
exit(1);
--
2.26.2
4:21 p.m.
New subject: [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-7-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 3 +--
target/mips/translate.c | 10 +++++-----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 89a9a4dda31..23ce8b8406f 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
@@ -75,7 +74,7 @@
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19933b7868c..172027f9d6e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
switch (reg) {
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -27612,7 +27612,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
--
2.26.2
4:21 p.m.
New subject: [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-8-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 3 +--
linux-user/mips/cpu_loop.c | 1 -
target/mips/translate.c | 4 ++--
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 23ce8b8406f..b36b59c12d3 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
@@ -78,7 +77,7 @@
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cfe7ba5c47d..f0831379cc4 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs
*regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
- env->insn_flags & ISA_MIPS64R2 ||
env->insn_flags & ISA_MIPS32R6 ||
env->insn_flags & ISA_MIPS64R6;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 172027f9d6e..9fc9dedf30d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
- check_insn(ctx, ISA_MIPS64R2);
+ check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS64R2);
+ check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
--
2.26.2
4:21 p.m.
New subject: [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-9-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b36b59c12d3..ccdde0b4a43 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -19,7 +19,6 @@
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
-#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
@@ -81,7 +80,7 @@
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
-#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
+#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
--
2.26.2
4:21 p.m.
New subject: [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-10-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ccdde0b4a43..b71127ddd7c 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -20,7 +20,6 @@
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
-#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
@@ -84,7 +83,7 @@
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
-#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
+#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
--
2.26.2
4:22 p.m.
New subject: [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug(a)amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 3 +--
linux-user/mips/cpu_loop.c | 3 +--
target/mips/helper.c | 6 +++---
target/mips/translate.c | 2 +-
5 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e4d2d9f44f9..3466725b761 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (env->insn_flags & ISA_MIPS64R6) {
+ } else if (env->insn_flags & ISA_MIPS32R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) ||
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b71127ddd7c..fea547508f0 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -21,7 +21,6 @@
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
-#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
* bits 24-39: MIPS ASEs
@@ -87,7 +86,7 @@
/* MIPS Technologies "Release 6" */
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
-#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index f0831379cc4..e400166c583 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs
*regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
- env->insn_flags & ISA_MIPS32R6 ||
- env->insn_flags & ISA_MIPS64R6;
+ env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 87296fbad69..5b74815beb0 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
enter_debug_mode:
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_EXL);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9fc9dedf30d..fc93b9da8eb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
ISA_MIPS64R6 |
+ ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb,
ctx->mem_idx,
--
2.26.2
4:22 p.m.
New subject: [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-12-f4bug(a)amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +--
target/mips/translate.c | 54 ++++++++++++++++++++---------------------
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 3466725b761..94910f75a61 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -411,7 +411,7 @@ static inline void compute_hflags(CPUMIPSState *env)
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
- } else if (env->insn_flags & ISA_MIPS32) {
+ } else if (env->insn_flags & ISA_MIPS_R1) {
if (env->hflags & MIPS_HFLAG_64) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index fea547508f0..a7048ffaffe 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -16,7 +16,7 @@
#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
-#define ISA_MIPS32 0x0000000000000020ULL
+#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
@@ -69,7 +69,7 @@
#define CPU_MIPS64 (ISA_MIPS3)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fc93b9da8eb..a59fbd94bac 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7411,7 +7411,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -8179,7 +8179,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -11006,7 +11006,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
break;
case OPC_DERET:
opn = "deret";
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -11021,7 +11021,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
break;
case OPC_WAIT:
opn = "wait";
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -11056,7 +11056,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
}
if (cc != 0) {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
}
btarget = ctx->base.pc_next + 4 + offset;
@@ -14425,7 +14425,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int xsregs = (ctx->opcode >> 24) & 0x7;
int aregs = (ctx->opcode >> 16) & 0xf;
@@ -14675,7 +14675,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
((int8_t)ctx->opcode) << 3);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int do_ra = ctx->opcode & (1 << 6);
int do_s0 = ctx->opcode & (1 << 5);
@@ -14819,7 +14819,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
int ra = (ctx->opcode >> 5) & 0x1;
if (nd) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (link) {
@@ -14840,7 +14840,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -14891,7 +14891,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_HILO(ctx, OPC_MFHI, 0, rx);
break;
case RR_CNVT:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
switch (cnvt_op) {
case RR_RY_CNVT_ZEB:
tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
@@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -15831,7 +15831,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -16175,7 +16175,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
case CLZ:
mips32_op = OPC_CLZ;
do_cl:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, mips32_op, rt, rs);
break;
case RDHWR:
@@ -16202,7 +16202,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
mips32_op = OPC_DIVU;
goto do_div;
do_div:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
case MADD:
@@ -16221,7 +16221,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUBU;
do_mul:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
default:
@@ -16369,7 +16369,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
gen_helper_do_semihosting(cpu_env);
} else {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception_end(ctx, EXCP_RI);
} else {
@@ -24889,7 +24889,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env,
DisasContext *ctx)
switch (op1) {
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
@@ -24902,7 +24902,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env,
DisasContext *ctx)
gen_HILO(ctx, op1, rd & 3, rs);
break;
case OPC_MOVCI:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
@@ -27577,7 +27577,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MADDU:
case OPC_MSUB:
case OPC_MSUBU:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_MUL:
@@ -27594,7 +27594,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
case OPC_CLO:
case OPC_CLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
@@ -27605,14 +27605,14 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
@@ -31025,7 +31025,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_CACHE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
@@ -31036,7 +31036,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
/* Treat as NOP. */
}
break;
--
2.26.2
4:22 p.m.
New subject: [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-13-f4bug(a)amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_timer.c | 4 +-
target/mips/helper.c | 2 +-
target/mips/translate.c | 138 ++++++++++++++++++-------------------
6 files changed, 76 insertions(+), 76 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 94910f75a61..23ae31ef989 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -407,7 +407,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a7048ffaffe..d1eeb69dfd7 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -17,7 +17,7 @@
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
-#define ISA_MIPS32R2 0x0000000000000040ULL
+#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
@@ -73,7 +73,7 @@
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
+#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index e400166c583..748e1c664f1 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -384,7 +384,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs
*regs)
prog_req.frdefault &= interp_req.frdefault;
prog_req.fre &= interp_req.fre;
- bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
+ bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index 5ec0d6249e9..70de95d338f 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
static void cpu_mips_timer_expire(CPUMIPSState *env)
{
cpu_mips_timer_update(env);
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause |= 1 << CP0Ca_TI;
}
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
@@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5b74815beb0..98d6ecaa65e 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -431,7 +431,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
uint32_t old = env->CP0_Cause;
int i;
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC;
}
if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a59fbd94bac..9c71d306ee5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7612,7 +7612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -7660,27 +7660,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -7696,7 +7696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -7791,17 +7791,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -7837,13 +7837,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
@@ -8357,7 +8357,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
@@ -8403,27 +8403,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -8439,7 +8439,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -8522,21 +8522,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8581,7 +8581,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -9120,7 +9120,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -9165,27 +9165,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -9201,7 +9201,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -9294,17 +9294,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -9339,12 +9339,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase";
@@ -9847,7 +9847,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
@@ -9892,27 +9892,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -9928,7 +9928,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -10015,21 +10015,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -10074,7 +10074,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -13453,7 +13453,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
* The Linux kernel will emulate rdhwr if it's not supported natively.
* Therefore only check the ISA in system mode.
*/
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
#endif
t0 = tcg_temp_new();
@@ -16269,12 +16269,12 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
switch (minor) {
case RDPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rs, rt);
break;
default:
@@ -24984,7 +24984,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* rotr is decoded as srl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTR;
}
/* Fallthrough */
@@ -25010,7 +25010,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTRV;
}
/* Fallthrough */
@@ -25083,7 +25083,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR;
}
/* Fallthrough */
@@ -25101,7 +25101,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR32;
}
/* Fallthrough */
@@ -25133,7 +25133,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTRV;
}
/* Fallthrough */
@@ -28594,7 +28594,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
switch (op1) {
case OPC_EXT:
case OPC_INS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
@@ -28609,7 +28609,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bshfl(ctx, op2, rt, rd);
break;
}
@@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
@@ -30741,7 +30741,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_SYNCI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/*
* Break the TB to be able to sync copied instructions
* immediately.
@@ -30858,7 +30858,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30869,7 +30869,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_EI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30890,11 +30890,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rt, rd);
break;
case OPC_WRPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rt, rd);
break;
default:
@@ -31056,7 +31056,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_MFHC1:
case OPC_MTHC1:
check_cp1_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/* fall through */
case OPC_MFC1:
case OPC_CFC1:
@@ -31250,21 +31250,21 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_LUXC1:
case OPC_SUXC1:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_SWXC1:
case OPC_SDXC1:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
/* Treat as NOP. */
break;
case OPC_ALNV_PS:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_MADD_S:
case OPC_MADD_D:
@@ -31278,7 +31278,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
--
2.26.2
4:22 p.m.
New subject: [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-14-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index d1eeb69dfd7..12ff2b3280c 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,7 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
-#define ISA_MIPS32R3 0x0000000000000200ULL
+#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
@@ -77,7 +77,7 @@
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
-#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
--
2.26.2
4:22 p.m.
New subject: [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 4 ++--
target/mips/translate.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 12ff2b3280c..181f3715472 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -19,7 +19,7 @@
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS_R3 0x0000000000000080ULL
-#define ISA_MIPS32R5 0x0000000000000800ULL
+#define ISA_MIPS_R5 0x0000000000000100ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
@@ -81,7 +81,7 @@
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
-#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9c71d306ee5..83fd6c473a5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -10993,7 +10993,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
if (ctx->opcode & (1 << bit_shift)) {
/* OPC_ERETNC */
opn = "eretnc";
- check_insn(ctx, ISA_MIPS32R5);
+ check_insn(ctx, ISA_MIPS_R5);
gen_helper_eretnc(cpu_env);
} else {
/* OPC_ERET */
--
2.26.2
4:22 p.m.
New subject: [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20210104221154.3127610-16-f4bug(a)amsat.org>
---
target/mips/internal.h | 4 +-
target/mips/mips-defs.h | 4 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_helper.c | 18 +-
target/mips/cpu.c | 6 +-
target/mips/fpu_helper.c | 4 +-
target/mips/helper.c | 10 +-
target/mips/translate.c | 426 ++++++++++++++++++-------------------
8 files changed, 237 insertions(+), 237 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 23ae31ef989..77a648bcf9c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (env->insn_flags & ISA_MIPS32R6) {
+ } else if (env->insn_flags & ISA_MIPS_R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) ||
@@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
#endif
if (((env->CP0_Status & (1 << CP0St_CU0)) &&
- !(env->insn_flags & ISA_MIPS32R6)) ||
+ !(env->insn_flags & ISA_MIPS_R6)) ||
!(env->hflags & MIPS_HFLAG_KSU)) {
env->hflags |= MIPS_HFLAG_CP0;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 181f3715472..97866019a72 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -20,7 +20,7 @@
#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS_R5 0x0000000000000100ULL
-#define ISA_MIPS32R6 0x0000000000002000ULL
+#define ISA_MIPS_R6 0x0000000000000200ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
* bits 24-39: MIPS ASEs
@@ -85,7 +85,7 @@
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
-#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
+#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
/* Wave Computing: "nanoMIPS" */
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 748e1c664f1..19947448a25 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs
*regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
- env->insn_flags & ISA_MIPS32R6;
+ env->insn_flags & ISA_MIPS_R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index 36a92857bfb..aae2af6eccc 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
uint32_t index_p = env->CP0_Index & 0x80000000;
uint32_t tlb_index = arg1 & 0x7fffffff;
if (tlb_index < env->tlb->nb_tlb) {
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
index_p |= arg1 & 0x80000000;
}
env->CP0_Index = index_p | tlb_index;
@@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
- if ((env->insn_flags & ISA_MIPS32R6)) {
+ if ((env->insn_flags & ISA_MIPS_R6)) {
if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
mask &= ~(0x3FULL << CP0PF_BDI);
}
@@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
env->CP0_PWField = arg1 & mask;
if ((new_ptei >= 32) ||
- ((env->insn_flags & ISA_MIPS32R6) &&
+ ((env->insn_flags & ISA_MIPS_R6) &&
(new_ptei == 0 || new_ptei == 1))) {
env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
(old_ptei << CP0PF_PTEI);
@@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
- if ((env->insn_flags & ISA_MIPS32R6)) {
+ if ((env->insn_flags & ISA_MIPS_R6)) {
if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
mask &= ~(0x3F << CP0PF_GDW);
}
@@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
env->CP0_PWField = arg1 & mask;
if ((new_ptew >= 32) ||
- ((env->insn_flags & ISA_MIPS32R6) &&
+ ((env->insn_flags & ISA_MIPS_R6) &&
(new_ptew == 0 || new_ptew == 1))) {
env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
(old_ptew << CP0PF_PTEW);
@@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
if (arg1 < env->tlb->nb_tlb) {
env->CP0_Wired = arg1;
}
@@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = 0x0000000F;
if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
- (env->insn_flags & ISA_MIPS32R6)) {
+ (env->insn_flags & ISA_MIPS_R6)) {
mask |= (1 << 4);
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
mask |= (1 << 5);
}
if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
@@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* 1k pages not implemented */
#if defined(TARGET_MIPS64)
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
int entryhi_r = extract64(arg1, 62, 2);
int config0_at = extract32(env->CP0_Config0, 13, 2);
bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 2283214c879..12126d37f16 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -71,7 +71,7 @@ static bool mips_cpu_has_work(CPUState *cs)
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
if (cpu_mips_hw_interrupts_enabled(env) ||
- (env->insn_flags & ISA_MIPS32R6)) {
+ (env->insn_flags & ISA_MIPS_R6)) {
has_work = true;
}
}
@@ -287,13 +287,13 @@ static void cpu_state_reset(CPUMIPSState *env)
/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
#endif /* !CONFIG_USER_ONLY */
- if ((env->insn_flags & ISA_MIPS32R6) &&
+ if ((env->insn_flags & ISA_MIPS_R6) &&
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
env->CP0_Status |= (1 << CP0St_FR);
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
/* PTW = 1 */
env->CP0_PWSize = 0x40;
/* GDI = 12 */
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index bdb65065ee7..91b6a2e11fc 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -145,7 +145,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs,
uint32_t rt)
}
break;
case 25:
- if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
+ if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) {
return;
}
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
@@ -172,7 +172,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs,
uint32_t rt)
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
break;
default:
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
do_raise_exception(env, EXCP_RI, GETPC());
}
return;
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 98d6ecaa65e..d1b6bb6fb23 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -397,7 +397,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
uint32_t mask = env->CP0_Status_rw_bitmask;
target_ulong old = env->CP0_Status;
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
#if defined(TARGET_MIPS64)
uint32_t ksux = (1 << CP0St_KX) & val;
@@ -434,7 +434,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC;
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
mask &= ~((1 << CP0Ca_WP) & val);
}
@@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
enter_debug_mode:
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_EXL);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 83fd6c473a5..e813add99c5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4014,7 +4014,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
}
break;
case OPC_LUI:
- if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
+ if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) {
/* OPC_AUI */
tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
@@ -7399,7 +7399,7 @@ cp0_unimplemented:
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
{
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
tcg_gen_movi_tl(arg, 0);
} else {
tcg_gen_movi_tl(arg, ~0);
@@ -7448,7 +7448,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_01:
switch (sel) {
case CP0_REG01__RANDOM:
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
@@ -7964,7 +7964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
@@ -8709,7 +8709,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
@@ -8980,7 +8980,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
case CP0_REGISTER_01:
switch (sel) {
case CP0_REG01__RANDOM:
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
@@ -9461,7 +9461,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
@@ -10191,7 +10191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int
sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
@@ -10985,7 +10985,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
gen_helper_tlbr(cpu_env);
break;
case OPC_ERET: /* OPC_ERETNC */
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
} else {
@@ -11007,7 +11007,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
case OPC_DERET:
opn = "deret";
check_insn(ctx, ISA_MIPS_R1);
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
}
@@ -11022,7 +11022,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
case OPC_WAIT:
opn = "wait";
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
}
@@ -11050,7 +11050,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
target_ulong btarget;
TCGv_i32 t0 = tcg_temp_new_i32();
- if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags &
MIPS_HFLAG_BMASK)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags &
MIPS_HFLAG_BMASK)) {
generate_exception_end(ctx, EXCP_RI);
goto out;
}
@@ -11906,23 +11906,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_SEL_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_SELEQZ_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_SELNEZ_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_MOVCF_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
break;
case OPC_MOVZ_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
@@ -11938,7 +11938,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MOVN_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
@@ -11974,7 +11974,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MADDF_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -11990,7 +11990,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MSUBF_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12006,7 +12006,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_RINT_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
@@ -12016,7 +12016,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_CLASS_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
@@ -12026,7 +12026,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MIN_S: /* OPC_RECIP2_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MIN_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12055,7 +12055,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MINA_S: /* OPC_RECIP1_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MINA_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12081,7 +12081,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAX_S: /* OPC_RSQRT1_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAX_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12105,7 +12105,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAXA_S: /* OPC_RSQRT2_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAXA_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12207,7 +12207,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_S:
case OPC_CMP_LE_S:
case OPC_CMP_NGT_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
} else {
@@ -12450,23 +12450,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_SEL_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_SELEQZ_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_SELNEZ_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_MOVCF_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
break;
case OPC_MOVZ_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
@@ -12482,7 +12482,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MOVN_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
@@ -12520,7 +12520,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MADDF_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12536,7 +12536,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MSUBF_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12552,7 +12552,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_RINT_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
@@ -12562,7 +12562,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_CLASS_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
@@ -12572,7 +12572,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MIN_D: /* OPC_RECIP2_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MIN_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12599,7 +12599,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MINA_D: /* OPC_RECIP1_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MINA_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12623,7 +12623,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAX_D: /* OPC_RSQRT1_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAX_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12647,7 +12647,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAXA_D: /* OPC_RSQRT2_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAXA_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12689,7 +12689,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_D:
case OPC_CMP_LE_D:
case OPC_CMP_NGT_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
} else {
@@ -13485,7 +13485,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 4:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (sel != 0) {
/*
* Performance counter registers are not implemented other than
@@ -13497,7 +13497,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 5:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_helper_rdhwr_xnp(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
@@ -16160,7 +16160,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
case 0x2c:
switch (minor) {
case BITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
break;
case SEB:
@@ -16179,26 +16179,26 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
gen_cl(ctx, mips32_op, rt, rs);
break;
case RDHWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_rdhwr(ctx, rt, rs, 0);
break;
case WSBH:
gen_bshfl(ctx, OPC_WSBH, rs, rt);
break;
case MULT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MULT;
goto do_mul;
case MULTU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MULTU;
goto do_mul;
case DIV:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_DIV;
goto do_div;
case DIVU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_DIVU;
goto do_div;
do_div:
@@ -16206,19 +16206,19 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
case MADD:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD;
goto do_mul;
case MADDU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADDU;
goto do_mul;
case MSUB:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB;
goto do_mul;
case MSUBU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUBU;
do_mul:
check_insn(ctx, ISA_MIPS_R1);
@@ -16246,7 +16246,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
switch (minor) {
case JALR: /* JALRC */
case JALR_HB: /* JALRC_HB */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* JALRC, JALRC_HB */
gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
} else {
@@ -16257,7 +16257,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
break;
case JALRS:
case JALRS_HB:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
@@ -16400,7 +16400,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
}
break;
case 0x35:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
switch (minor) {
case MFHI32:
gen_HILO(ctx, OPC_MFHI, 0, rs);
@@ -16674,7 +16674,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVT, 5):
case COND_FLOAT_MOV(MOVT, 6):
case COND_FLOAT_MOV(MOVT, 7):
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
break;
case COND_FLOAT_MOV(MOVF, 0):
@@ -16685,7 +16685,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVF, 5):
case COND_FLOAT_MOV(MOVF, 6):
case COND_FLOAT_MOV(MOVF, 7):
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
break;
default:
@@ -16736,15 +16736,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_shift_imm(ctx, mips32_op, rt, rs, rd);
break;
case SELEQZ:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
break;
case SELNEZ:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
break;
case R6_RDHWR:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
break;
default:
@@ -16768,7 +16768,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
mips32_op = OPC_SUBU;
goto do_arith;
case MUL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MUL;
do_arith:
gen_arith(ctx, mips32_op, rd, rs, rt);
@@ -16821,7 +16821,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
switch (minor) {
/* Conditional moves */
case MOVN: /* MUL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUL */
gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
} else {
@@ -16830,7 +16830,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MOVZ: /* MUH */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUH */
gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
} else {
@@ -16839,15 +16839,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case MULU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
break;
case MUHU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
break;
case LWXS: /* DIV */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* DIV */
gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
} else {
@@ -16856,15 +16856,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case MOD:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
break;
case R6_DIVU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
break;
case MODU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
break;
default:
@@ -16875,12 +16875,12 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
return;
case LSA:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
@@ -16893,7 +16893,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
generate_exception_end(ctx, EXCP_BREAK);
break;
case SIGRIE:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
generate_exception_end(ctx, EXCP_RI);
break;
default:
@@ -16951,61 +16951,61 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
check_cp1_enabled(ctx);
switch (minor) {
case ALNV_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_ALNV_PS;
goto do_madd;
case MADD_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_S;
goto do_madd;
case MADD_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_D;
goto do_madd;
case MADD_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_PS;
goto do_madd;
case MSUB_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_S;
goto do_madd;
case MSUB_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_D;
goto do_madd;
case MSUB_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_PS;
goto do_madd;
case NMADD_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_S;
goto do_madd;
case NMADD_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_D;
goto do_madd;
case NMADD_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_PS;
goto do_madd;
case NMSUB_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_S;
goto do_madd;
case NMSUB_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_D;
goto do_madd;
case NMSUB_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_PS;
do_madd:
gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
break;
case CABS_COND_FMT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
@@ -17024,7 +17024,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case C_COND_FMT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
@@ -17043,11 +17043,11 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case CMP_CONDN_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case CMP_CONDN_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case POOL32FXF:
@@ -17069,7 +17069,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
mips32_op = OPC_PUU_PS;
goto do_ps;
case CVT_PS_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_CVT_PS_S;
do_ps:
gen_farith(ctx, mips32_op, rt, rs, rd, 0);
@@ -17079,7 +17079,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MIN_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
@@ -17095,27 +17095,27 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
/* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) {
case LWXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWXC1;
goto do_ldst_cp1;
case SWXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWXC1;
goto do_ldst_cp1;
case LDXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDXC1;
goto do_ldst_cp1;
case SDXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDXC1;
goto do_ldst_cp1;
case LUXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LUXC1;
goto do_ldst_cp1;
case SUXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SUXC1;
do_ldst_cp1:
gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
@@ -17125,7 +17125,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MAX_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
@@ -17139,7 +17139,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case 0x18:
/* 3D insns */
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case RSQRT2_FMT:
@@ -17190,7 +17190,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case MOVF_FMT: /* RINT_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* RINT_FMT */
switch (fmt) {
case FMT_SDPS_S:
@@ -17221,7 +17221,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MOVT_FMT: /* CLASS_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* CLASS_FMT */
switch (fmt) {
case FMT_SDPS_S:
@@ -17252,7 +17252,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case PREFX:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
break;
default:
goto pool32f_invalid;
@@ -17274,7 +17274,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
goto pool32f_invalid; \
}
case MINA_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
@@ -17287,7 +17287,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MAXA_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
@@ -17329,7 +17329,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
case MOVN_FMT: /* SELEQZ_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
@@ -17347,11 +17347,11 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case MOVN_FMT_04:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVN);
break;
case MOVZ_FMT: /* SELNEZ_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
@@ -17369,11 +17369,11 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case MOVZ_FMT_05:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVZ);
break;
case SEL_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
@@ -17386,7 +17386,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MADDF_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MADDF_S;
@@ -17399,7 +17399,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case MSUBF_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MSUBF_S;
@@ -17432,45 +17432,45 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
minor = (ctx->opcode >> 21) & 0x1f;
switch (minor) {
case BLTZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
break;
case BLTZAL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLTZALS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
break;
case BGEZAL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZALS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLEZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
break;
case BGTZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
break;
/* Traps */
case TLTI: /* BC1EQZC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1EQZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
@@ -17481,7 +17481,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case TGEI: /* BC1NEZC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1NEZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
@@ -17492,15 +17492,15 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case TLTIU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TLTIU;
goto do_trapi;
case TGEIU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TGEIU;
goto do_trapi;
case TNEI: /* SYNCI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SYNCI */
/*
* Break the TB to be able to sync copied instructions
@@ -17514,7 +17514,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case TEQI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TEQI;
do_trapi:
gen_trap(ctx, mips32_op, rs, -1, imm);
@@ -17522,7 +17522,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
case BNEZC:
case BEQZC:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
4, rs, 0, imm << 1, 0);
/*
@@ -17532,11 +17532,11 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
*/
break;
case LUI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
break;
case SYNCI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/*
* Break the TB to be able to sync copied instructions
* immediately.
@@ -17545,24 +17545,24 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case BC2F:
case BC2T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
case BC1F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 :
OPC_BC1F;
goto do_cp1branch;
case BC1T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 :
OPC_BC1T;
goto do_cp1branch;
case BC1ANY4F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1FANY4;
goto do_cp1mips3d;
case BC1ANY4T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1TANY4;
do_cp1mips3d:
check_cop1x(ctx);
@@ -17590,47 +17590,47 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case POOL32C:
minor = (ctx->opcode >> 12) & 0xf;
offset = sextract32(ctx->opcode, 0,
- (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12);
switch (minor) {
case LWL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWL;
goto do_ld_lr;
case SWL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWL;
goto do_st_lr;
case LWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWR;
goto do_ld_lr;
case SWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWR;
goto do_st_lr;
#if defined(TARGET_MIPS64)
case LDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDL;
goto do_ld_lr;
case SDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDL;
goto do_st_lr;
case LDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDR;
goto do_ld_lr;
case SDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDR;
goto do_st_lr;
case LWU:
@@ -17681,11 +17681,11 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
mips32_op = OPC_LHUE;
goto do_ld_lr;
case LWLE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWLE;
goto do_ld_lr;
case LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWRE;
goto do_ld_lr;
case LBE:
@@ -17714,16 +17714,16 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
offset = sextract32(ctx->opcode, 0, 9);
switch (minor2) {
case SWLE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWLE;
goto do_st_lr;
case SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWRE;
goto do_st_lr;
case PREFE:
/* Treat as no-op */
- if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
@@ -17750,7 +17750,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case PREF:
/* Treat as no-op */
- if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
@@ -17762,7 +17762,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case ADDI32: /* AUI, LUI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* AUI, LUI */
gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
} else {
@@ -17800,13 +17800,13 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_slt_imm(ctx, mips32_op, rt, rs, imm);
break;
case JALX32:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case JALS32: /* BOVC, BEQC, BEQZALC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs >= rt) {
/* BOVC */
mips32_op = OPC_BOVC;
@@ -17826,7 +17826,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case BEQ32: /* BC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC */
gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
@@ -17836,7 +17836,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case BNE32: /* BALC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BALC */
gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
@@ -17846,7 +17846,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case J32: /* BGTZC, BLTZC, BLTC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BGTZC */
mips32_op = OPC_BGTZC;
@@ -17865,7 +17865,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case JAL32: /* BLEZC, BGEZC, BGEC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BLEZC */
mips32_op = OPC_BLEZC;
@@ -17900,7 +17900,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break;
case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
case ADDIUPC_00:
@@ -17942,7 +17942,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case BNVC: /* BNEC, BNEZALC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs >= rt) {
/* BNVC */
mips32_op = OPC_BNVC;
@@ -17956,7 +17956,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case R6_BNEZC: /* JIALC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BNEZC */
gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
@@ -17967,7 +17967,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case R6_BEQZC: /* JIC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BEQZC */
gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
@@ -17978,7 +17978,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case BLEZALC: /* BGEZALC, BGEUC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BLEZALC */
mips32_op = OPC_BLEZALC;
@@ -17992,7 +17992,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case BGTZALC: /* BLTZALC, BLTUC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BGTZALC */
mips32_op = OPC_BGTZALC;
@@ -18114,7 +18114,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
opc = OPC_SUBU;
break;
}
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/*
* In the Release 6, the register number location in
* the instruction encoding has changed.
@@ -18146,7 +18146,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case POOL16C:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
gen_pool16c_r6_insn(ctx);
} else {
gen_pool16c_insn(ctx);
@@ -18162,7 +18162,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case POOL16F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & 1) {
generate_exception_end(ctx, EXCP_RI);
} else {
@@ -18280,14 +18280,14 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
case B16: /* BC16 */
gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
sextract32(ctx->opcode, 0, 10) << 1,
- (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
break;
case BNEZ16: /* BNEZC16 */
case BEQZ16: /* BEQZC16 */
gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,
mmreg(uMIPS_RD(ctx->opcode)),
0, sextract32(ctx->opcode, 0, 7) << 1,
- (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
break;
case LI16:
@@ -24970,7 +24970,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
case OPC_SLL: /* Shift with immediate */
if (sa == 5 && rd == 0 &&
rs == 0 && rt == 0) { /* PAUSE */
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -25045,7 +25045,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
+ if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
decode_opc_special_r6(env, ctx);
} else {
@@ -25148,14 +25148,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
+ if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
decode_opc_special_r6(env, ctx);
}
break;
#endif
default:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special_r6(env, ctx);
} else if (ctx->insn_flags & INSN_R5900) {
decode_opc_special_tx79(env, ctx);
@@ -27565,7 +27565,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -28552,7 +28552,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
switch (op1) {
case OPC_LWLE:
case OPC_LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LBUE:
case OPC_LHUE:
@@ -28565,7 +28565,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
return;
case OPC_SWLE:
case OPC_SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SBE:
case OPC_SHE:
@@ -28605,7 +28605,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
case OPC_ALIGN_2:
case OPC_ALIGN_3:
case OPC_BITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
decode_opc_special3_r6(env, ctx);
break;
default:
@@ -28637,7 +28637,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
case OPC_DALIGN_6:
case OPC_DALIGN_7:
case OPC_DBITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
decode_opc_special3_r6(env, ctx);
break;
default:
@@ -28677,7 +28677,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
}
break;
default:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special3_r6(env, ctx);
} else {
decode_opc_special3_legacy(env, ctx);
@@ -30706,7 +30706,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BLTZALL:
case OPC_BGEZALL:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_BLTZ:
case OPC_BGEZ:
@@ -30714,7 +30714,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BLTZAL:
case OPC_BGEZAL:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0) {
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
@@ -30733,11 +30733,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_TNEI:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SIGRIE:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_SYNCI:
@@ -30757,14 +30757,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case OPC_DAHI:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
}
break;
case OPC_DATI:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
@@ -30844,14 +30844,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
break;
case OPC_DVP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_dvp(t0, cpu_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_EVP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_evp(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30904,7 +30904,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
@@ -30933,7 +30933,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
/* Branch */
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -30946,7 +30946,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -30963,7 +30963,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BLEZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
/* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
@@ -30973,7 +30973,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BGTZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
/* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
@@ -30981,7 +30981,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BEQL:
case OPC_BNEL:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_BEQ:
case OPC_BNE:
@@ -30995,7 +30995,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_LB:
case OPC_LH:
@@ -31007,7 +31007,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SWL:
case OPC_SWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SB:
case OPC_SH:
@@ -31016,14 +31016,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case OPC_CACHE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
@@ -31032,7 +31032,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case OPC_PREF:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
@@ -31076,7 +31076,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif
case OPC_BC1EQZ: /* OPC_BC1ANY2 */
check_cp1_enabled(ctx);
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC1EQZ */
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
@@ -31090,19 +31090,19 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BC1NEZ:
check_cp1_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
break;
case OPC_BC1ANY4:
check_cp1_enabled(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
/* fall through */
case OPC_BC1:
check_cp1_enabled(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
break;
@@ -31120,7 +31120,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
{
int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
check_cp1_enabled(ctx);
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
switch (r6_op) {
case R6_OPC_CMP_AF_S:
case R6_OPC_CMP_UN_S:
@@ -31205,7 +31205,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Compact branches [R6] and COP2 [non-R6] */
case OPC_BC: /* OPC_LWC2 */
case OPC_BALC: /* OPC_SWC2 */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC, OPC_BALC */
gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
@@ -31219,7 +31219,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs != 0) {
/* OPC_BEQZC, OPC_BNEZC */
gen_compute_compact_branch(ctx, op, rs, 0,
@@ -31243,7 +31243,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_CP3:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
@@ -31300,7 +31300,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* fall through */
case OPC_LDL:
case OPC_LDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LWU:
case OPC_LD:
@@ -31310,7 +31310,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDL:
case OPC_SDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
@@ -31318,7 +31318,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SCD:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_insn(ctx, ISA_MIPS3);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
@@ -31327,7 +31327,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
@@ -31344,7 +31344,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#else
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
MIPS_INVAL("major opcode");
@@ -31353,7 +31353,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
case OPC_DAUI: /* OPC_JALX */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
#if defined(TARGET_MIPS64)
/* OPC_DAUI */
check_mips_64(ctx);
@@ -31387,7 +31387,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_PCREL:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
break;
default: /* Invalid */
@@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
+ ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb,
ctx->mem_idx,
--
2.26.2
4:22 p.m.
New subject: [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset()
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-2-f4bug(a)amsat.org>
---
target/mips/cpu.c | 26 +++++++++-----------------
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 12126d37f16..4a251e2d3e8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "translate_init.c.inc"
-/* TODO QOM'ify CPU reset and remove */
-static void cpu_state_reset(CPUMIPSState *env)
+static void mips_cpu_reset(DeviceState *dev)
{
- CPUState *cs = env_cpu(env);
+ CPUState *cs = CPU(dev);
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ mcc->parent_reset(dev);
+
+ memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
@@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env)
/* UHI interface can be used to obtain argc and argv */
env->active_tc.gpr[4] = -1;
}
-}
-
-static void mips_cpu_reset(DeviceState *dev)
-{
- CPUState *s = CPU(dev);
- MIPSCPU *cpu = MIPS_CPU(s);
- MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
- CPUMIPSState *env = &cpu->env;
-
- mcc->parent_reset(dev);
-
- memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
-
- cpu_state_reset(env);
#ifndef CONFIG_USER_ONLY
if (kvm_enabled()) {
--
2.26.2
4:22 p.m.
New subject: [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug(a)amsat.org>
---
target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++
target/mips/internal.h | 49 --------------------------
linux-user/mips/cpu_loop.c | 1 +
target/mips/fpu_helper.c | 1 +
target/mips/gdbstub.c | 1 +
target/mips/kvm.c | 1 +
target/mips/machine.c | 1 +
target/mips/msa_helper.c | 1 +
target/mips/op_helper.c | 2 +-
target/mips/translate.c | 1 +
target/mips/translate_init.c.inc | 2 ++
11 files changed, 69 insertions(+), 50 deletions(-)
create mode 100644 target/mips/fpu_helper.h
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
new file mode 100644
index 00000000000..1c2d6d35a71
--- /dev/null
+++ b/target/mips/fpu_helper.h
@@ -0,0 +1,59 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ * Copyright (C) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "fpu/softfloat-helpers.h"
+#include "cpu.h"
+
+extern const FloatRoundMode ieee_rm[4];
+
+uint32_t float_class_s(uint32_t arg, float_status *fst);
+uint64_t float_class_d(uint64_t arg, float_status *fst);
+
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+ set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) ==
0,
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_fp_status(CPUMIPSState *env)
+{
+ restore_rounding_mode(env);
+ restore_flush_mode(env);
+ restore_snan_bit_mode(env);
+}
+
+/* MSA */
+
+enum CPUMIPSMSADataFormat {
+ DF_BYTE = 0,
+ DF_HALF,
+ DF_WORD,
+ DF_DOUBLE
+};
+
+static inline void restore_msa_fp_status(CPUMIPSState *env)
+{
+ float_status *status = &env->active_tc.msa_fp_status;
+ int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >>
MSACSR_RM;
+ bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
+
+ set_float_rounding_mode(ieee_rm[rounding_mode], status);
+ set_flush_to_zero(flush_to_zero, status);
+ set_flush_inputs_to_zero(flush_to_zero, status);
+}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 77a648bcf9c..f159187b246 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,7 +9,6 @@
#define MIPS_INTERNAL_H
#include "exec/memattrs.h"
-#include "fpu/softfloat-helpers.h"
/*
* MMU types, the first four entries have the same layout as the
@@ -75,13 +74,6 @@ struct mips_def_t {
extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;
-enum CPUMIPSMSADataFormat {
- DF_BYTE = 0,
- DF_HALF,
- DF_WORD,
- DF_DOUBLE
-};
-
void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
/* op_helper.c */
-uint32_t float_class_s(uint32_t arg, float_status *fst);
-uint64_t float_class_d(uint64_t arg, float_status *fst);
-
-extern const FloatRoundMode ieee_rm[4];
-
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
- set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_snan_bit_mode(CPUMIPSState *env)
-{
- set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) ==
0,
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_fp_status(CPUMIPSState *env)
-{
- restore_rounding_mode(env);
- restore_flush_mode(env);
- restore_snan_bit_mode(env);
-}
-
-static inline void restore_msa_fp_status(CPUMIPSState *env)
-{
- float_status *status = &env->active_tc.msa_fp_status;
- int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >>
MSACSR_RM;
- bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
-
- set_float_rounding_mode(ieee_rm[rounding_mode], status);
- set_flush_to_zero(flush_to_zero, status);
- set_flush_inputs_to_zero(flush_to_zero, status);
-}
-
static inline void restore_pamask(CPUMIPSState *env)
{
if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 19947448a25..9d813ece4e7 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -23,6 +23,7 @@
#include "cpu_loop-common.h"
#include "elf.h"
#include "internal.h"
+#include "fpu_helper.h"
# ifdef TARGET_ABI_MIPSO32
# define MIPS_SYSCALL_NUMBER_UNUSED -1
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 91b6a2e11fc..6dd853259e2 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -27,6 +27,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
+#include "fpu_helper.h"
/* Complex FPU operations which may need stack space. */
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index e39f8d75cf0..f1c2a2cf6d6 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "internal.h"
#include "exec/gdbstub.h"
+#include "fpu_helper.h"
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 477692566a4..a5b6fe35dbc 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -24,6 +24,7 @@
#include "sysemu/runstate.h"
#include "kvm_mips.h"
#include "hw/boards.h"
+#include "fpu_helper.h"
#define DEBUG_KVM 0
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 77afe654e91..b5fda6a2786 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "internal.h"
#include "migration/cpu.h"
+#include "fpu_helper.h"
static int cpu_post_load(void *opaque, int version_id)
{
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 249f0fdad80..b89b4c44902 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
+#include "fpu_helper.h"
/* Data format min and max values */
#define DF_BITS(df) (1 << ((df) + 3))
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5aa97902e98..3386b8228e9 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -24,7 +24,7 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/memop.h"
-
+#include "fpu_helper.h"
/*****************************************************************************/
/* Exceptions processing helpers */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e813add99c5..f8f0f95509c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -35,6 +35,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/qemu-print.h"
+#include "fpu_helper.h"
#define MIPS_DEBUG_DISAS 0
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 0ba3cf18ef7..044052fb77c 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -18,6 +18,8 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>;.
*/
+#include "fpu_helper.h"
+
/* CPU / CPU family specific config register values. */
/* Have config1, uncached coherency */
--
2.26.2
4:22 p.m.
New subject: [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-4-f4bug(a)amsat.org>
---
target/mips/helper.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index d1b6bb6fb23..92bd3fb8550 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
}
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
@@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong
address,
}
#if !defined(CONFIG_USER_ONLY)
+
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
#if !defined(CONFIG_USER_ONLY)
#if !defined(TARGET_MIPS64)
@@ -886,7 +888,7 @@ refill:
return true;
}
#endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
void mips_cpu_do_interrupt(CPUState *cs)
{
@@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
}
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
uint32_t exception,
--
2.26.2
4:22 p.m.
New subject: [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-5-f4bug(a)amsat.org>
---
target/mips/helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 92bd3fb8550..cfb6d82fd33 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
-#endif /* !CONFIG_USER_ONLY */
-#if !defined(CONFIG_USER_ONLY)
#if !defined(TARGET_MIPS64)
/*
--
2.26.2
4:22 p.m.
New subject: [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c
The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-6-f4bug(a)amsat.org>
---
target/mips/internal.h | 2 +
target/mips/cpu.c | 215 +++++++++++++++++++++++++++++++++++++++--
target/mips/helper.c | 201 --------------------------------------
3 files changed, 211 insertions(+), 207 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index f159187b246..ae1181d2029 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
+const char *mips_exception_name(int32_t exception);
+
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
int error_code, uintptr_t pc);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4a251e2d3e8..26b4c3e9cd5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -34,6 +34,215 @@
#include "hw/semihosting/semihost.h"
#include "qapi/qapi-commands-machine-target.h"
+#if !defined(CONFIG_USER_ONLY)
+
+/* Called for updates to CP0_Status. */
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
+{
+ int32_t tcstatus, *tcst;
+ uint32_t v = cpu->CP0_Status;
+ uint32_t cu, mx, asid, ksu;
+ uint32_t mask = ((1 << CP0TCSt_TCU3)
+ | (1 << CP0TCSt_TCU2)
+ | (1 << CP0TCSt_TCU1)
+ | (1 << CP0TCSt_TCU0)
+ | (1 << CP0TCSt_TMX)
+ | (3 << CP0TCSt_TKSU)
+ | (0xff << CP0TCSt_TASID));
+
+ cu = (v >> CP0St_CU0) & 0xf;
+ mx = (v >> CP0St_MX) & 0x1;
+ ksu = (v >> CP0St_KSU) & 0x3;
+ asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+
+ tcstatus = cu << CP0TCSt_TCU0;
+ tcstatus |= mx << CP0TCSt_TMX;
+ tcstatus |= ksu << CP0TCSt_TKSU;
+ tcstatus |= asid;
+
+ if (tc == cpu->current_tc) {
+ tcst = &cpu->active_tc.CP0_TCStatus;
+ } else {
+ tcst = &cpu->tcs[tc].CP0_TCStatus;
+ }
+
+ *tcst &= ~mask;
+ *tcst |= tcstatus;
+ compute_hflags(cpu);
+}
+
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
+{
+ uint32_t mask = env->CP0_Status_rw_bitmask;
+ target_ulong old = env->CP0_Status;
+
+ if (env->insn_flags & ISA_MIPS_R6) {
+ bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
+#if defined(TARGET_MIPS64)
+ uint32_t ksux = (1 << CP0St_KX) & val;
+ ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+ ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+ val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
+ if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
+ mask &= ~(3 << CP0St_KSU);
+ }
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
+ }
+
+ env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+ if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+ /* Access to at least one of the 64-bit segments has been disabled */
+ tlb_flush(env_cpu(env));
+ }
+#endif
+ if (ase_mt_available(env)) {
+ sync_c0_status(env, env, env->current_tc);
+ } else {
+ compute_hflags(env);
+ }
+}
+
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
+{
+ uint32_t mask = 0x00C00300;
+ uint32_t old = env->CP0_Cause;
+ int i;
+
+ if (env->insn_flags & ISA_MIPS_R2) {
+ mask |= 1 << CP0Ca_DC;
+ }
+ if (env->insn_flags & ISA_MIPS_R6) {
+ mask &= ~((1 << CP0Ca_WP) & val);
+ }
+
+ env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
+
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+ if (env->CP0_Cause & (1 << CP0Ca_DC)) {
+ cpu_mips_stop_count(env);
+ } else {
+ cpu_mips_start_count(env);
+ }
+ }
+
+ /* Set/reset software interrupts */
+ for (i = 0 ; i < 2 ; i++) {
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+ cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP +
i)));
+ }
+ }
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+static const char * const excp_names[EXCP_LAST + 1] = {
+ [EXCP_RESET] = "reset",
+ [EXCP_SRESET] = "soft reset",
+ [EXCP_DSS] = "debug single step",
+ [EXCP_DINT] = "debug interrupt",
+ [EXCP_NMI] = "non-maskable interrupt",
+ [EXCP_MCHECK] = "machine check",
+ [EXCP_EXT_INTERRUPT] = "interrupt",
+ [EXCP_DFWATCH] = "deferred watchpoint",
+ [EXCP_DIB] = "debug instruction breakpoint",
+ [EXCP_IWATCH] = "instruction fetch watchpoint",
+ [EXCP_AdEL] = "address error load",
+ [EXCP_AdES] = "address error store",
+ [EXCP_TLBF] = "TLB refill",
+ [EXCP_IBE] = "instruction bus error",
+ [EXCP_DBp] = "debug breakpoint",
+ [EXCP_SYSCALL] = "syscall",
+ [EXCP_BREAK] = "break",
+ [EXCP_CpU] = "coprocessor unusable",
+ [EXCP_RI] = "reserved instruction",
+ [EXCP_OVERFLOW] = "arithmetic overflow",
+ [EXCP_TRAP] = "trap",
+ [EXCP_FPE] = "floating point",
+ [EXCP_DDBS] = "debug data break store",
+ [EXCP_DWATCH] = "data watchpoint",
+ [EXCP_LTLBL] = "TLB modify",
+ [EXCP_TLBL] = "TLB load",
+ [EXCP_TLBS] = "TLB store",
+ [EXCP_DBE] = "data bus error",
+ [EXCP_DDBL] = "debug data break load",
+ [EXCP_THREAD] = "thread",
+ [EXCP_MDMX] = "MDMX",
+ [EXCP_C2E] = "precise coprocessor 2",
+ [EXCP_CACHE] = "cache error",
+ [EXCP_TLBXI] = "TLB execute-inhibit",
+ [EXCP_TLBRI] = "TLB read-inhibit",
+ [EXCP_MSADIS] = "MSA disabled",
+ [EXCP_MSAFPE] = "MSA floating point",
+};
+
+const char *mips_exception_name(int32_t exception)
+{
+ if (exception < 0 || exception > EXCP_LAST) {
+ return "unknown";
+ }
+ return excp_names[exception];
+}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+ vp->env.exception_base = address;
+}
+
+target_ulong exception_resume_pc(CPUMIPSState *env)
+{
+ target_ulong bad_pc;
+ target_ulong isa_mode;
+
+ isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+ bad_pc = env->active_tc.PC | isa_mode;
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /*
+ * If the exception was raised from a delay slot, come back to
+ * the jump.
+ */
+ bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
+ }
+
+ return bad_pc;
+}
+
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ if (cpu_mips_hw_interrupts_enabled(env) &&
+ cpu_mips_hw_interrupts_pending(env)) {
+ /* Raise it */
+ cs->exception_index = EXCP_EXT_INTERRUPT;
+ env->error_code = 0;
+ mips_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
+ return false;
+}
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
+ uint32_t exception,
+ int error_code,
+ uintptr_t pc)
+{
+ CPUState *cs = env_cpu(env);
+
+ qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
+ __func__, exception, mips_exception_name(exception),
+ error_code);
+ cs->exception_index = exception;
+ env->error_code = error_code;
+
+ cpu_loop_exit_restore(cs, pc);
+}
+
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -587,9 +796,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type)
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
- MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
- vp->env.exception_base = address;
-}
diff --git a/target/mips/helper.c b/target/mips/helper.c
index cfb6d82fd33..68804b84b15 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
-/* Called for updates to CP0_Status. */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
- int32_t tcstatus, *tcst;
- uint32_t v = cpu->CP0_Status;
- uint32_t cu, mx, asid, ksu;
- uint32_t mask = ((1 << CP0TCSt_TCU3)
- | (1 << CP0TCSt_TCU2)
- | (1 << CP0TCSt_TCU1)
- | (1 << CP0TCSt_TCU0)
- | (1 << CP0TCSt_TMX)
- | (3 << CP0TCSt_TKSU)
- | (0xff << CP0TCSt_TASID));
-
- cu = (v >> CP0St_CU0) & 0xf;
- mx = (v >> CP0St_MX) & 0x1;
- ksu = (v >> CP0St_KSU) & 0x3;
- asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
- tcstatus = cu << CP0TCSt_TCU0;
- tcstatus |= mx << CP0TCSt_TMX;
- tcstatus |= ksu << CP0TCSt_TKSU;
- tcstatus |= asid;
-
- if (tc == cpu->current_tc) {
- tcst = &cpu->active_tc.CP0_TCStatus;
- } else {
- tcst = &cpu->tcs[tc].CP0_TCStatus;
- }
-
- *tcst &= ~mask;
- *tcst |= tcstatus;
- compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
- uint32_t mask = env->CP0_Status_rw_bitmask;
- target_ulong old = env->CP0_Status;
-
- if (env->insn_flags & ISA_MIPS_R6) {
- bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
- uint32_t ksux = (1 << CP0St_KX) & val;
- ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
- ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
- val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
- if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
- mask &= ~(3 << CP0St_KSU);
- }
- mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
- }
-
- env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
- if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
- /* Access to at least one of the 64-bit segments has been disabled */
- tlb_flush(env_cpu(env));
- }
-#endif
- if (ase_mt_available(env)) {
- sync_c0_status(env, env, env->current_tc);
- } else {
- compute_hflags(env);
- }
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
- uint32_t mask = 0x00C00300;
- uint32_t old = env->CP0_Cause;
- int i;
-
- if (env->insn_flags & ISA_MIPS_R2) {
- mask |= 1 << CP0Ca_DC;
- }
- if (env->insn_flags & ISA_MIPS_R6) {
- mask &= ~((1 << CP0Ca_WP) & val);
- }
-
- env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
- if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
- if (env->CP0_Cause & (1 << CP0Ca_DC)) {
- cpu_mips_stop_count(env);
- } else {
- cpu_mips_start_count(env);
- }
- }
-
- /* Set/reset software interrupts */
- for (i = 0 ; i < 2 ; i++) {
- if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
- cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP +
i)));
- }
- }
-}
-
#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
@@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong
address,
return physical;
}
}
-#endif /* !CONFIG_USER_ONLY */
-static const char * const excp_names[EXCP_LAST + 1] = {
- [EXCP_RESET] = "reset",
- [EXCP_SRESET] = "soft reset",
- [EXCP_DSS] = "debug single step",
- [EXCP_DINT] = "debug interrupt",
- [EXCP_NMI] = "non-maskable interrupt",
- [EXCP_MCHECK] = "machine check",
- [EXCP_EXT_INTERRUPT] = "interrupt",
- [EXCP_DFWATCH] = "deferred watchpoint",
- [EXCP_DIB] = "debug instruction breakpoint",
- [EXCP_IWATCH] = "instruction fetch watchpoint",
- [EXCP_AdEL] = "address error load",
- [EXCP_AdES] = "address error store",
- [EXCP_TLBF] = "TLB refill",
- [EXCP_IBE] = "instruction bus error",
- [EXCP_DBp] = "debug breakpoint",
- [EXCP_SYSCALL] = "syscall",
- [EXCP_BREAK] = "break",
- [EXCP_CpU] = "coprocessor unusable",
- [EXCP_RI] = "reserved instruction",
- [EXCP_OVERFLOW] = "arithmetic overflow",
- [EXCP_TRAP] = "trap",
- [EXCP_FPE] = "floating point",
- [EXCP_DDBS] = "debug data break store",
- [EXCP_DWATCH] = "data watchpoint",
- [EXCP_LTLBL] = "TLB modify",
- [EXCP_TLBL] = "TLB load",
- [EXCP_TLBS] = "TLB store",
- [EXCP_DBE] = "data bus error",
- [EXCP_DDBL] = "debug data break load",
- [EXCP_THREAD] = "thread",
- [EXCP_MDMX] = "MDMX",
- [EXCP_C2E] = "precise coprocessor 2",
- [EXCP_CACHE] = "cache error",
- [EXCP_TLBXI] = "TLB execute-inhibit",
- [EXCP_TLBRI] = "TLB read-inhibit",
- [EXCP_MSADIS] = "MSA disabled",
- [EXCP_MSAFPE] = "MSA floating point",
-};
-
-static const char *mips_exception_name(int32_t exception)
-{
- if (exception < 0 || exception > EXCP_LAST) {
- return "unknown";
- }
- return excp_names[exception];
-}
-
-target_ulong exception_resume_pc(CPUMIPSState *env)
-{
- target_ulong bad_pc;
- target_ulong isa_mode;
-
- isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
- bad_pc = env->active_tc.PC | isa_mode;
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /*
- * If the exception was raised from a delay slot, come back to
- * the jump.
- */
- bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
- }
-
- return bad_pc;
-}
-
-#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler(CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
@@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
cs->exception_index = EXCP_NONE;
}
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
-
- if (cpu_mips_hw_interrupts_enabled(env) &&
- cpu_mips_hw_interrupts_pending(env)) {
- /* Raise it */
- cs->exception_index = EXCP_EXT_INTERRUPT;
- env->error_code = 0;
- mips_cpu_do_interrupt(cs);
- return true;
- }
- }
- return false;
-}
-
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
@@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
}
}
#endif /* !CONFIG_USER_ONLY */
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
- uint32_t exception,
- int error_code,
- uintptr_t pc)
-{
- CPUState *cs = env_cpu(env);
-
- qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
- __func__, exception, mips_exception_name(exception),
- error_code);
- cs->exception_index = exception;
- env->error_code = error_code;
-
- cpu_loop_exit_restore(cs, pc);
-}
--
2.26.2
4:22 p.m.
New subject: [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201206233949.3783184-13-f4bug(a)amsat.org>
---
target/mips/{helper.c => tlb_helper.c} | 2 +-
target/mips/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
rename target/mips/{helper.c => tlb_helper.c} (99%)
diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c
similarity index 99%
rename from target/mips/helper.c
rename to target/mips/tlb_helper.c
index 68804b84b15..b02c0479e79 100644
--- a/target/mips/helper.c
+++ b/target/mips/tlb_helper.c
@@ -1,5 +1,5 @@
/*
- * MIPS emulation helpers for qemu.
+ * MIPS TLB (Translation lookaside buffer) helpers.
*
* Copyright (c) 2004-2005 Jocelyn Mayer
*
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 4179395a8ea..5a49951c6d7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -4,10 +4,10 @@
'dsp_helper.c',
'fpu_helper.c',
'gdbstub.c',
- 'helper.c',
'lmmi_helper.c',
'msa_helper.c',
'op_helper.c',
+ 'tlb_helper.c',
'translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
4:22 p.m.
New subject: [PULL 25/66] target/mips: Fix code style for checkpatch.pl
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201206233949.3783184-14-f4bug(a)amsat.org>
---
target/mips/translate_init.c.inc | 36 ++++++++++++++++----------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 044052fb77c..21ee22c05dc 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -936,19 +936,19 @@ void mips_cpu_list(void)
}
#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &no_mmu_map_address;
}
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &fixed_mmu_map_address;
}
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
env->tlb->map_address = &r4k_map_address;
@@ -960,25 +960,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
}
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env_cpu(env), "MMU type not supported\n");
+ case MMU_TYPE_NONE:
+ no_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(env, def);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
}
}
#endif /* CONFIG_USER_ONLY */
--
2.26.2
4:22 p.m.
New subject: [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201206233949.3783184-15-f4bug(a)amsat.org>
---
target/mips/internal.h | 1 +
target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++
target/mips/translate_init.c.inc | 48 --------------------------------
3 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index ae1181d2029..9a7698019e2 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);
/* helper.c */
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index b02c0479e79..082c17928d3 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
return TLBRET_NOMATCH;
}
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+ env->tlb->map_address = &r4k_map_address;
+ env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb->helper_tlbp = r4k_helper_tlbp;
+ env->tlb->helper_tlbr = r4k_helper_tlbr;
+ env->tlb->helper_tlbinv = r4k_helper_tlbinv;
+ env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
+}
+
+void mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+ switch (def->mmu_type) {
+ case MMU_TYPE_NONE:
+ no_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(env, def);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
+ }
+}
+
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
{
/*
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 21ee22c05dc..535d4c0c702 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -935,54 +935,6 @@ void mips_cpu_list(void)
}
}
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
- env->tlb->helper_tlbinv = r4k_helper_tlbinv;
- env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
-}
-
-static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
- switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env_cpu(env), "MMU type not supported\n");
- }
-}
-#endif /* CONFIG_USER_ONLY */
-
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
{
int i;
--
2.26.2
4:22 p.m.
New subject: [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-10-f4bug(a)amsat.org>
---
target/mips/cpu.c | 2 +-
target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (100%)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 26b4c3e9cd5..55c6a054bba 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs)
return has_work;
}
-#include "translate_init.c.inc"
+#include "cpu-defs.c.inc"
static void mips_cpu_reset(DeviceState *dev)
{
diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc
similarity index 100%
rename from target/mips/translate_init.c.inc
rename to target/mips/cpu-defs.c.inc
--
2.26.2
4:22 p.m.
New subject: [PULL 28/66] target/mips/translate: Extract DisasContext structure
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201207235539.4070364-2-f4bug(a)amsat.org>
---
target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 38 +------------------------------
2 files changed, 51 insertions(+), 37 deletions(-)
create mode 100644 target/mips/translate.h
diff --git a/target/mips/translate.h b/target/mips/translate.h
new file mode 100644
index 00000000000..fcda1a99001
--- /dev/null
+++ b/target/mips/translate.h
@@ -0,0 +1,50 @@
+/*
+ * MIPS translation routines.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_TRANSLATE_H
+#define TARGET_MIPS_TRANSLATE_H
+
+#include "exec/translator.h"
+
+typedef struct DisasContext {
+ DisasContextBase base;
+ target_ulong saved_pc;
+ target_ulong page_start;
+ uint32_t opcode;
+ uint64_t insn_flags;
+ int32_t CP0_Config1;
+ int32_t CP0_Config2;
+ int32_t CP0_Config3;
+ int32_t CP0_Config5;
+ /* Routine used to access memory */
+ int mem_idx;
+ MemOp default_tcg_memop_mask;
+ uint32_t hflags, saved_hflags;
+ target_ulong btarget;
+ bool ulri;
+ int kscrexist;
+ bool rxi;
+ int ie;
+ bool bi;
+ bool bp;
+ uint64_t PAMask;
+ bool mvh;
+ bool eva;
+ bool sc;
+ int CP0_LLAddr_shift;
+ bool ps;
+ bool vp;
+ bool cmgcr;
+ bool mrp;
+ bool nan2008;
+ bool abs2008;
+ bool saar;
+ bool mi;
+ int gi;
+} DisasContext;
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f8f0f95509c..9e824e12d44 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -36,6 +36,7 @@
#include "exec/log.h"
#include "qemu/qemu-print.h"
#include "fpu_helper.h"
+#include "translate.h"
#define MIPS_DEBUG_DISAS 0
@@ -2554,43 +2555,6 @@ static TCGv mxu_CR;
tcg_temp_free_i32(helper_tmp); \
} while (0)
-typedef struct DisasContext {
- DisasContextBase base;
- target_ulong saved_pc;
- target_ulong page_start;
- uint32_t opcode;
- uint64_t insn_flags;
- int32_t CP0_Config1;
- int32_t CP0_Config2;
- int32_t CP0_Config3;
- int32_t CP0_Config5;
- /* Routine used to access memory */
- int mem_idx;
- MemOp default_tcg_memop_mask;
- uint32_t hflags, saved_hflags;
- target_ulong btarget;
- bool ulri;
- int kscrexist;
- bool rxi;
- int ie;
- bool bi;
- bool bp;
- uint64_t PAMask;
- bool mvh;
- bool eva;
- bool sc;
- int CP0_LLAddr_shift;
- bool ps;
- bool vp;
- bool cmgcr;
- bool mrp;
- bool nan2008;
- bool abs2008;
- bool saar;
- bool mi;
- int gi;
-} DisasContext;
-
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
--
2.26.2
4:22 p.m.
New subject: [PULL 29/66] target/mips/translate: Add declarations for generic code
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug(a)amsat.org>
---
target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++++
target/mips/translate.c | 45 ++++++++++-------------------------------
2 files changed, 49 insertions(+), 34 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index fcda1a99001..d9d4d3943af 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -10,6 +10,8 @@
#include "exec/translator.h"
+#define MIPS_DEBUG_DISAS 0
+
typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
@@ -47,4 +49,40 @@ typedef struct DisasContext {
int gi;
} DisasContext;
+/* MIPS major opcodes */
+#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
+
+void generate_exception(DisasContext *ctx, int excp);
+void generate_exception_err(DisasContext *ctx, int excp, int err);
+void generate_exception_end(DisasContext *ctx, int excp);
+void check_insn(DisasContext *ctx, uint64_t flags);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_load_gpr(TCGv t, int reg);
+void gen_store_gpr(TCGv t, int reg);
+
+extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv bcond;
+
+#define LOG_DISAS(...) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+#define MIPS_INVAL(op) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, \
+ TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n",
\
+ ctx->base.pc_next, ctx->opcode, op, \
+ ctx->opcode >> 26, ctx->opcode & 0x3F,
\
+ ((ctx->opcode >> 16) & 0x1F));
\
+ } \
+ } while (0)
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9e824e12d44..5889d24eb65 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -38,11 +38,6 @@
#include "fpu_helper.h"
#include "translate.h"
-#define MIPS_DEBUG_DISAS 0
-
-/* MIPS major opcodes */
-#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
-
enum {
/* indirect opcode tables */
OPC_SPECIAL = (0x00 << 26),
@@ -2491,9 +2486,10 @@ enum {
};
/* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget;
+TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
};
#endif
-#define LOG_DISAS(...) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
- } \
- } while (0)
-
-#define MIPS_INVAL(op) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, \
- TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n",
\
- ctx->base.pc_next, ctx->opcode, op, \
- ctx->opcode >> 26, ctx->opcode & 0x3F,
\
- ((ctx->opcode >> 16) & 0x1F));
\
- } \
- } while (0)
-
/* General purpose registers moves. */
-static inline void gen_load_gpr(TCGv t, int reg)
+void gen_load_gpr(TCGv t, int reg)
{
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
@@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
}
}
-static inline void gen_store_gpr(TCGv t, int reg)
+void gen_store_gpr(TCGv t, int reg)
{
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
@@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext
*ctx)
}
}
-static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
+void generate_exception_err(DisasContext *ctx, int excp, int err)
{
TCGv_i32 texcp = tcg_const_i32(excp);
TCGv_i32 terr = tcg_const_i32(err);
@@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasContext *ctx, int
excp, int err)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static inline void generate_exception(DisasContext *ctx, int excp)
+void generate_exception(DisasContext *ctx, int excp)
{
gen_helper_0e0i(raise_exception, excp);
}
-static inline void generate_exception_end(DisasContext *ctx, int excp)
+void generate_exception_end(DisasContext *ctx, int excp)
{
generate_exception_err(ctx, excp, 0);
}
@@ -3013,7 +2991,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
* This code generates a "reserved instruction" exception if the
* CPU does not support the instruction set corresponding to flags.
*/
-static inline void check_insn(DisasContext *ctx, uint64_t flags)
+void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -3064,7 +3042,7 @@ static inline void check_ps(DisasContext *ctx)
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
@@ -3390,8 +3368,7 @@ OP_LD_ATOMIC(lld, ld64);
#endif
#undef OP_LD_ATOMIC
-static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
- int base, int offset)
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
--
2.26.2
4:22 p.m.
New subject: [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-11-f4bug(a)amsat.org>
---
target/mips/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5889d24eb65..445858591a4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2898,7 +2898,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
static inline void check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
}
}
@@ -3104,10 +3104,10 @@ static inline void check_mt(DisasContext *ctx)
static inline void check_cp0_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_err(ctx, EXCP_RI, 0);
+ generate_exception_end(ctx, EXCP_RI);
}
}
}
--
2.26.2
4:22 p.m.
New subject: [PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-12-f4bug(a)amsat.org>
---
target/mips/translate.h | 1 +
target/mips/translate.c | 729 ++++++++++++++++++++--------------------
2 files changed, 368 insertions(+), 362 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index d9d4d3943af..5f744c63374 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -55,6 +55,7 @@ typedef struct DisasContext {
void generate_exception(DisasContext *ctx, int excp);
void generate_exception_err(DisasContext *ctx, int excp, int err);
void generate_exception_end(DisasContext *ctx, int excp);
+void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 445858591a4..7c20ed33df7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2762,6 +2762,11 @@ void generate_exception_end(DisasContext *ctx, int excp)
generate_exception_err(ctx, excp, 0);
}
+void gen_reserved_instruction(DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI);
+}
+
/* Floating point register moves. */
static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
{
@@ -2917,7 +2922,7 @@ static inline void check_cp1_enabled(DisasContext *ctx)
static inline void check_cop1x(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2928,7 +2933,7 @@ static inline void check_cop1x(DisasContext *ctx)
static inline void check_cp1_64bitmode(DisasContext *ctx)
{
if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2946,7 +2951,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
static inline void check_cp1_registers(DisasContext *ctx, int regs)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2960,7 +2965,7 @@ static inline void check_dsp(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2971,7 +2976,7 @@ static inline void check_dsp_r2(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2982,7 +2987,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2994,7 +2999,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3006,7 +3011,7 @@ void check_insn(DisasContext *ctx, uint64_t flags)
static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3045,7 +3050,7 @@ static inline void check_ps(DisasContext *ctx)
void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
#endif
@@ -3066,7 +3071,7 @@ static inline void check_mvh(DisasContext *ctx)
static inline void check_xnp(DisasContext *ctx)
{
if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3078,7 +3083,7 @@ static inline void check_xnp(DisasContext *ctx)
static inline void check_pw(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
#endif
@@ -3090,7 +3095,7 @@ static inline void check_pw(DisasContext *ctx)
static inline void check_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3107,7 +3112,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
generate_exception_end(ctx, EXCP_CpU);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -3120,7 +3125,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
static inline void check_nms(DisasContext *ctx)
{
if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3137,7 +3142,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3148,7 +3153,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
static inline void check_eva(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3813,7 +3818,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
break;
default:
MIPS_INVAL("flt_ldst");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -4462,7 +4467,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int
reg)
break;
default:
MIPS_INVAL("mfthilo1 TX79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -4597,7 +4602,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc,
target_ulong pc,
#endif
default:
MIPS_INVAL("OPC_PCREL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -4808,7 +4813,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int
rs, int rt)
#endif
default:
MIPS_INVAL("r6 mul/div");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -4866,7 +4871,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs,
int rt)
break;
default:
MIPS_INVAL("div1 TX79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -5059,7 +5064,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul/div");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -5190,7 +5195,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul/madd TXx9");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -5253,7 +5258,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul vr54xx");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_store_gpr(t0, rd);
@@ -5879,7 +5884,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int
rs, int rt)
break;
default:
MIPS_INVAL("loongson_cp2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -6068,7 +6073,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
#endif
default:
MIPS_INVAL("loongson_gsshfl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -6116,13 +6121,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
#endif
default:
MIPS_INVAL("loongson_gsshfs");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
MIPS_INVAL("loongson_gslsq");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -6171,7 +6176,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
break;
default:
MIPS_INVAL("loongson_lsdc2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
break;
}
@@ -6427,7 +6432,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
TARGET_FMT_lx "\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -6490,14 +6495,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
* others are reserved.
*/
MIPS_INVAL("jump hint");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_load_gpr(btarget, rs);
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
if (bcond_compute == 0) {
@@ -6562,7 +6567,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -6633,7 +6638,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
}
@@ -6710,14 +6715,14 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t
opc,
* others are reserved.
*/
MIPS_INVAL("jump hint");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_load_gpr(btarget, rs);
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
if (bcond_compute == 0) {
@@ -6750,7 +6755,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -6773,7 +6778,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
}
@@ -6853,7 +6858,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
default:
fail:
MIPS_INVAL("bitops");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
tcg_temp_free(t0);
tcg_temp_free(t1);
return;
@@ -6931,7 +6936,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int
rd)
#endif
default:
MIPS_INVAL("bsfhl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
tcg_temp_free(t0);
return;
}
@@ -10585,7 +10590,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt,
int rd,
die:
tcg_temp_free(t0);
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
@@ -10795,7 +10800,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd,
int rt,
die:
tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
@@ -10955,7 +10960,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
}
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
MIPS_INVAL(opn);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
gen_helper_deret(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -10978,7 +10983,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t
opc,
default:
die:
MIPS_INVAL(opn);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
(void)opn; /* avoid a compiler warning */
@@ -10993,7 +10998,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
TCGv_i32 t0 = tcg_temp_new_i32();
if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags &
MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11084,7 +11089,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
ctx->btarget = btarget;
@@ -11106,7 +11111,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t
op,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
"\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11126,7 +11131,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t
op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11434,7 +11439,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int
fs)
break;
default:
MIPS_INVAL("cp1 move");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11571,7 +11576,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd,
int ft,
break;
default:
MIPS_INVAL("gen_sel_s");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -11608,7 +11613,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd,
int ft,
break;
default:
MIPS_INVAL("gen_sel_d");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -13042,7 +13047,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
break;
default:
MIPS_INVAL("farith");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
}
@@ -13381,7 +13386,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("flt3_arith");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
}
@@ -13456,13 +13461,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int
sel)
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("rdhwr");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -13561,7 +13566,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t
opc,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
"\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13623,7 +13628,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t
opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13644,7 +13649,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t
opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13767,7 +13772,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t
opc,
break;
default:
MIPS_INVAL("Compact conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13941,7 +13946,7 @@ static void gen_mips16_save(DisasContext *ctx,
args = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14037,7 +14042,7 @@ static void gen_mips16_save(DisasContext *ctx,
astatic = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14143,7 +14148,7 @@ static void gen_mips16_restore(DisasContext *ctx,
astatic = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14174,7 +14179,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, int imm,
TCGv t0;
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14232,7 +14237,7 @@ static void decode_i64_mips16(DisasContext *ctx,
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
offset = extended ? offset : offset << 3;
gen_ld(ctx, OPC_LDPC, ry, 0, offset);
@@ -14309,7 +14314,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
check_mips_64(ctx);
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
case 0x2:
@@ -14337,7 +14342,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
check_mips_64(ctx);
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
} else {
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14389,7 +14394,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14452,7 +14457,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -14541,7 +14546,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
check_mips_64(ctx);
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
case 0x2:
@@ -14569,7 +14574,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
check_mips_64(ctx);
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
} else {
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14653,7 +14658,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -14743,7 +14748,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto done;
}
@@ -14860,7 +14865,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14924,7 +14929,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14939,7 +14944,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -15637,7 +15642,7 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int
reglist,
TCGv_i32 t2;
if (ctx->hflags & MIPS_HFLAG_BMASK) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -15790,7 +15795,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -15935,7 +15940,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int
rd,
TCGv t0, t1;
if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -15947,7 +15952,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int
rd,
switch (opc) {
case LWP:
if (rd == base) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
@@ -15968,7 +15973,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int
rd,
#ifdef TARGET_MIPS64
case LDP:
if (rd == base) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
@@ -16313,7 +16318,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
} else {
check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -16363,7 +16368,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx,
int rt, int rs)
default:
pool32axf_invalid:
MIPS_INVAL("pool32axf");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -16632,7 +16637,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
break;
default:
MIPS_INVAL("pool32fxf");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -16836,12 +16841,12 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
pool32a_invalid:
MIPS_INVAL("pool32a");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -16883,7 +16888,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("pool32b");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17363,7 +17368,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
default:
pool32f_invalid:
MIPS_INVAL("pool32f");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else {
@@ -17525,7 +17530,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
/* Fall through */
default:
MIPS_INVAL("pool32i");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17608,7 +17613,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
case LD_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c ld-eva");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
@@ -17647,7 +17652,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
case ST_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c st-eva");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
@@ -17699,7 +17704,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("pool32c");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17991,7 +17996,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_st(ctx, mips32_op, rt, rs, imm);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -18022,7 +18027,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
case 7:
/* LB32, LH32, LWC132, LDC132, LW32 */
if (ctx->hflags & MIPS_HFLAG_BDS16) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 2;
}
break;
@@ -18033,7 +18038,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
case 3:
/* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
if (ctx->hflags & MIPS_HFLAG_BDS32) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 2;
}
break;
@@ -18106,7 +18111,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
case POOL16F:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & 1) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
/* MOVEP */
int enc_dest = uMIPS_RD(ctx->opcode);
@@ -18244,7 +18249,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext
*ctx)
case RES_29:
case RES_31:
case RES_39:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
decode_micromips32_opc(env, ctx);
@@ -19502,7 +19507,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env,
DisasContext *ctx)
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case 1:
@@ -19517,7 +19522,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env,
DisasContext *ctx)
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
}
@@ -19567,7 +19572,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env,
DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -19608,7 +19613,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx,
uint32_t opc,
gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19659,7 +19664,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx,
uint32_t opc,
gen_helper_shilo(t0, v0_t, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19733,7 +19738,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx,
uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19771,7 +19776,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t
opc,
gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19794,7 +19799,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t
opc,
gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19821,7 +19826,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t
opc,
gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19848,12 +19853,12 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t
opc,
gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19997,7 +20002,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx,
uint32_t opc,
gen_store_gpr(t0, ret);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -20090,7 +20095,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx,
uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20233,7 +20238,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx,
uint32_t opc,
gen_bshfl(ctx, OPC_WSBH, ret, rs);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20288,7 +20293,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx,
uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -20385,7 +20390,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env,
DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -20396,7 +20401,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -20429,7 +20434,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t
opc,
case NM_BBNEZC:
check_nms(ctx);
if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
} else if (rt == 0 && opc == NM_BBEQZC) {
/* Unconditional branch */
@@ -20479,7 +20484,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t
opc,
break;
default:
MIPS_INVAL("Immediate Value Compact branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20592,7 +20597,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx,
uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20604,7 +20609,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx,
uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -20665,7 +20670,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx,
uint32_t opc,
break;
default:
MIPS_INVAL("Compact conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20709,7 +20714,7 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t
op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20839,7 +20844,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20856,7 +20861,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
rd = extract32(ctx->opcode, 11, 5);
if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
check_cp1_enabled(ctx);
@@ -20930,7 +20935,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21119,7 +21124,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21136,12 +21141,12 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -21667,7 +21672,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int
opc,
gen_store_gpr(v1_t, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21689,7 +21694,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int
opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -21717,13 +21722,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
switch (extract32(ctx->opcode, 19, 2)) {
case NM_SIGRIE:
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case NM_P_SYSCALL:
if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case NM_BREAK:
@@ -21734,7 +21739,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -21792,12 +21797,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_pool32axf_nanomips_insn(env, ctx);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21816,7 +21821,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21887,7 +21892,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
return 6;
@@ -21922,12 +21927,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_SR_F:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22015,7 +22020,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
extract32(ctx->opcode, 6, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22028,12 +22033,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
extract32(ctx->opcode, 6, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22101,7 +22106,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_st(ctx, OPC_SH, rt, 28, u);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22123,7 +22128,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22183,7 +22188,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22246,7 +22251,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22386,7 +22391,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22406,7 +22411,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
true);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22457,7 +22462,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22501,7 +22506,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22536,7 +22541,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22585,7 +22590,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22601,7 +22606,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
return 4;
@@ -22640,7 +22645,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
if (extract32(ctx->opcode, 2, 1) == 0) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case NM_BREAK16:
@@ -22651,14 +22656,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22697,7 +22702,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22746,7 +22751,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22782,7 +22787,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_ld(ctx, OPC_LBU, rt, rs, offset);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22801,7 +22806,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext
*ctx)
gen_ld(ctx, OPC_LHU, rt, rs, offset);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -23580,7 +23585,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
break;
default: /* Invalid */
MIPS_INVAL("MASK SHLL.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -23695,7 +23700,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
break;
default: /* Invalid */
MIPS_INVAL("MASK SHLL.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24386,7 +24391,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext
*ctx,
break;
default: /* Invalid */
MIPS_INVAL("MASK APPEND");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24420,7 +24425,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext
*ctx,
break;
default: /* Invalid */
MIPS_INVAL("MASK DAPPEND");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24689,7 +24694,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("special_r6 muldiv");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24706,7 +24711,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
*/
gen_cl(ctx, op1, rd, rs);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case R6_OPC_SDBBP:
@@ -24714,7 +24719,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -24735,7 +24740,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case OPC_DMULT:
@@ -24758,14 +24763,14 @@ static void decode_opc_special_r6(CPUMIPSState *env,
DisasContext *ctx)
break;
default:
MIPS_INVAL("special_r6 muldiv");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("special_r6");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24812,7 +24817,7 @@ static void decode_opc_special_tx79(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("special_tx79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24883,16 +24888,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#else
/* Implemented as RI exception for now. */
MIPS_INVAL("spim (unofficial)");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
default: /* Invalid */
MIPS_INVAL("special_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24914,7 +24919,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
rs == 0 && rt == 0) { /* PAUSE */
if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24934,7 +24939,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24960,7 +24965,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24994,7 +24999,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
/* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#else
gen_helper_0e0i(pmon, sa);
#endif
@@ -25035,7 +25040,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25053,7 +25058,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25085,7 +25090,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25150,7 +25155,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
rd = extract32(opcode, 11, 5);
if (unlikely(pd != 0)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else if (rd == 0) {
/* nop */
} else if (rt == 0) {
@@ -26357,16 +26362,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_Q8SLT:
/* TODO: Implement emulation of Q8SLT instruction. */
MIPS_INVAL("OPC_MXU_Q8SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8SLTU:
/* TODO: Implement emulation of Q8SLTU instruction. */
MIPS_INVAL("OPC_MXU_Q8SLTU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26396,41 +26401,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32SLT:
/* TODO: Implement emulation of S32SLT instruction. */
MIPS_INVAL("OPC_MXU_S32SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16SLT:
/* TODO: Implement emulation of D16SLT instruction. */
MIPS_INVAL("OPC_MXU_D16SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16AVG:
/* TODO: Implement emulation of D16AVG instruction. */
MIPS_INVAL("OPC_MXU_D16AVG");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16AVGR:
/* TODO: Implement emulation of D16AVGR instruction. */
MIPS_INVAL("OPC_MXU_D16AVGR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8AVG:
/* TODO: Implement emulation of Q8AVG instruction. */
MIPS_INVAL("OPC_MXU_Q8AVG");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8AVGR:
/* TODO: Implement emulation of Q8AVGR instruction. */
MIPS_INVAL("OPC_MXU_Q8AVGR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8ADD:
/* TODO: Implement emulation of Q8ADD instruction. */
MIPS_INVAL("OPC_MXU_Q8ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26453,26 +26458,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32CPS:
/* TODO: Implement emulation of S32CPS instruction. */
MIPS_INVAL("OPC_MXU_S32CPS");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16CPS:
/* TODO: Implement emulation of D16CPS instruction. */
MIPS_INVAL("OPC_MXU_D16CPS");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8ABD:
/* TODO: Implement emulation of Q8ABD instruction. */
MIPS_INVAL("OPC_MXU_Q8ABD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SAT:
/* TODO: Implement emulation of Q16SAT instruction. */
MIPS_INVAL("OPC_MXU_Q16SAT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26502,16 +26507,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_D16MULF:
/* TODO: Implement emulation of D16MULF instruction. */
MIPS_INVAL("OPC_MXU_D16MULF");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MULE:
/* TODO: Implement emulation of D16MULE instruction. */
MIPS_INVAL("OPC_MXU_D16MULE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26537,7 +26542,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26560,16 +26565,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32STD:
/* TODO: Implement emulation of S32STD instruction. */
MIPS_INVAL("OPC_MXU_S32STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32STDR:
/* TODO: Implement emulation of S32STDR instruction. */
MIPS_INVAL("OPC_MXU_S32STDR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26592,16 +26597,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32LDDV:
/* TODO: Implement emulation of S32LDDV instruction. */
MIPS_INVAL("OPC_MXU_S32LDDV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDDVR:
/* TODO: Implement emulation of S32LDDVR instruction. */
MIPS_INVAL("OPC_MXU_S32LDDVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26624,16 +26629,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32STDV:
/* TODO: Implement emulation of S32TDV instruction. */
MIPS_INVAL("OPC_MXU_S32TDV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32STDVR:
/* TODO: Implement emulation of S32TDVR instruction. */
MIPS_INVAL("OPC_MXU_S32TDVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26656,16 +26661,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32LDI:
/* TODO: Implement emulation of S32LDI instruction. */
MIPS_INVAL("OPC_MXU_S32LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDIR:
/* TODO: Implement emulation of S32LDIR instruction. */
MIPS_INVAL("OPC_MXU_S32LDIR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26688,16 +26693,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32SDI:
/* TODO: Implement emulation of S32SDI instruction. */
MIPS_INVAL("OPC_MXU_S32SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SDIR:
/* TODO: Implement emulation of S32SDIR instruction. */
MIPS_INVAL("OPC_MXU_S32SDIR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26720,16 +26725,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32LDIV:
/* TODO: Implement emulation of S32LDIV instruction. */
MIPS_INVAL("OPC_MXU_S32LDIV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDIVR:
/* TODO: Implement emulation of S32LDIVR instruction. */
MIPS_INVAL("OPC_MXU_S32LDIVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26752,16 +26757,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32SDIV:
/* TODO: Implement emulation of S32SDIV instruction. */
MIPS_INVAL("OPC_MXU_S32SDIV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SDIVR:
/* TODO: Implement emulation of S32SDIVR instruction. */
MIPS_INVAL("OPC_MXU_S32SDIVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26784,21 +26789,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_D32ACC:
/* TODO: Implement emulation of D32ACC instruction. */
MIPS_INVAL("OPC_MXU_D32ACC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32ACCM:
/* TODO: Implement emulation of D32ACCM instruction. */
MIPS_INVAL("OPC_MXU_D32ACCM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32ASUM:
/* TODO: Implement emulation of D32ASUM instruction. */
MIPS_INVAL("OPC_MXU_D32ASUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26821,21 +26826,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_Q16ACC:
/* TODO: Implement emulation of Q16ACC instruction. */
MIPS_INVAL("OPC_MXU_Q16ACC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ACCM:
/* TODO: Implement emulation of Q16ACCM instruction. */
MIPS_INVAL("OPC_MXU_Q16ACCM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ASUM:
/* TODO: Implement emulation of Q16ASUM instruction. */
MIPS_INVAL("OPC_MXU_Q16ASUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26865,21 +26870,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_Q8ADDE:
/* TODO: Implement emulation of Q8ADDE instruction. */
MIPS_INVAL("OPC_MXU_Q8ADDE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D8SUM:
/* TODO: Implement emulation of D8SUM instruction. */
MIPS_INVAL("OPC_MXU_D8SUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D8SUMC:
/* TODO: Implement emulation of D8SUMC instruction. */
MIPS_INVAL("OPC_MXU_D8SUMC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26909,26 +26914,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_S32MUL:
/* TODO: Implement emulation of S32MUL instruction. */
MIPS_INVAL("OPC_MXU_S32MUL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MULU:
/* TODO: Implement emulation of S32MULU instruction. */
MIPS_INVAL("OPC_MXU_S32MULU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32EXTR:
/* TODO: Implement emulation of S32EXTR instruction. */
MIPS_INVAL("OPC_MXU_S32EXTR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32EXTRV:
/* TODO: Implement emulation of S32EXTRV instruction. */
MIPS_INVAL("OPC_MXU_S32EXTRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26976,12 +26981,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_D32SARW:
/* TODO: Implement emulation of D32SARW instruction. */
MIPS_INVAL("OPC_MXU_D32SARW");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32ALN:
/* TODO: Implement emulation of S32ALN instruction. */
MIPS_INVAL("OPC_MXU_S32ALN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32ALNI:
gen_mxu_S32ALNI(ctx);
@@ -26989,7 +26994,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_S32LUI:
/* TODO: Implement emulation of S32LUI instruction. */
MIPS_INVAL("OPC_MXU_S32LUI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32NOR:
gen_mxu_S32NOR(ctx);
@@ -27005,7 +27010,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27028,31 +27033,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_LXW:
/* TODO: Implement emulation of LXW instruction. */
MIPS_INVAL("OPC_MXU_LXW");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXH:
/* TODO: Implement emulation of LXH instruction. */
MIPS_INVAL("OPC_MXU_LXH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXHU:
/* TODO: Implement emulation of LXHU instruction. */
MIPS_INVAL("OPC_MXU_LXHU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXB:
/* TODO: Implement emulation of LXB instruction. */
MIPS_INVAL("OPC_MXU_LXB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXBU:
/* TODO: Implement emulation of LXBU instruction. */
MIPS_INVAL("OPC_MXU_LXBU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27074,36 +27079,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_D32SLLV:
/* TODO: Implement emulation of D32SLLV instruction. */
MIPS_INVAL("OPC_MXU_D32SLLV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLRV:
/* TODO: Implement emulation of D32SLRV instruction. */
MIPS_INVAL("OPC_MXU_D32SLRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SARV:
/* TODO: Implement emulation of D32SARV instruction. */
MIPS_INVAL("OPC_MXU_D32SARV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLLV:
/* TODO: Implement emulation of Q16SLLV instruction. */
MIPS_INVAL("OPC_MXU_Q16SLLV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLRV:
/* TODO: Implement emulation of Q16SLRV instruction. */
MIPS_INVAL("OPC_MXU_Q16SLRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SARV:
/* TODO: Implement emulation of Q16SARV instruction. */
MIPS_INVAL("OPC_MXU_Q16SARV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27129,7 +27134,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext
*ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27152,36 +27157,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_Q8MOVZ:
/* TODO: Implement emulation of Q8MOVZ instruction. */
MIPS_INVAL("OPC_MXU_Q8MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MOVN:
/* TODO: Implement emulation of Q8MOVN instruction. */
MIPS_INVAL("OPC_MXU_Q8MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MOVZ:
/* TODO: Implement emulation of D16MOVZ instruction. */
MIPS_INVAL("OPC_MXU_D16MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MOVN:
/* TODO: Implement emulation of D16MOVN instruction. */
MIPS_INVAL("OPC_MXU_D16MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MOVZ:
/* TODO: Implement emulation of S32MOVZ instruction. */
MIPS_INVAL("OPC_MXU_S32MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MOVN:
/* TODO: Implement emulation of S32MOVN instruction. */
MIPS_INVAL("OPC_MXU_S32MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27204,16 +27209,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MXU_Q8MAC:
/* TODO: Implement emulation of Q8MAC instruction. */
MIPS_INVAL("OPC_MXU_Q8MAC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MACSU:
/* TODO: Implement emulation of Q8MACSU instruction. */
MIPS_INVAL("OPC_MXU_Q8MACSU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27272,12 +27277,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_S32MADD:
/* TODO: Implement emulation of S32MADD instruction. */
MIPS_INVAL("OPC_MXU_S32MADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MADDU:
/* TODO: Implement emulation of S32MADDU instruction. */
MIPS_INVAL("OPC_MXU_S32MADDU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
@@ -27285,12 +27290,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_S32MSUB:
/* TODO: Implement emulation of S32MSUB instruction. */
MIPS_INVAL("OPC_MXU_S32MSUB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MSUBU:
/* TODO: Implement emulation of S32MSUBU instruction. */
MIPS_INVAL("OPC_MXU_S32MSUBU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL01:
decode_opc_mxu__pool01(env, ctx);
@@ -27310,27 +27315,27 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_D16MACF:
/* TODO: Implement emulation of D16MACF instruction. */
MIPS_INVAL("OPC_MXU_D16MACF");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MADL:
/* TODO: Implement emulation of D16MADL instruction. */
MIPS_INVAL("OPC_MXU_D16MADL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16MAD:
/* TODO: Implement emulation of S16MAD instruction. */
MIPS_INVAL("OPC_MXU_S16MAD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ADD:
/* TODO: Implement emulation of Q16ADD instruction. */
MIPS_INVAL("OPC_MXU_Q16ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MACE:
/* TODO: Implement emulation of D16MACE instruction. */
MIPS_INVAL("OPC_MXU_D16MACE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL04:
decode_opc_mxu__pool04(env, ctx);
@@ -27359,7 +27364,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D32ADD:
/* TODO: Implement emulation of D32ADD instruction. */
MIPS_INVAL("OPC_MXU_D32ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL12:
decode_opc_mxu__pool12(env, ctx);
@@ -27373,7 +27378,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8ACCE:
/* TODO: Implement emulation of Q8ACCE instruction. */
MIPS_INVAL("OPC_MXU_Q8ACCE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8LDD:
gen_mxu_s8ldd(ctx);
@@ -27381,17 +27386,17 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_S8STD:
/* TODO: Implement emulation of S8STD instruction. */
MIPS_INVAL("OPC_MXU_S8STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8LDI:
/* TODO: Implement emulation of S8LDI instruction. */
MIPS_INVAL("OPC_MXU_S8LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8SDI:
/* TODO: Implement emulation of S8SDI instruction. */
MIPS_INVAL("OPC_MXU_S8SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL15:
decode_opc_mxu__pool15(env, ctx);
@@ -27405,52 +27410,52 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_S16LDD:
/* TODO: Implement emulation of S16LDD instruction. */
MIPS_INVAL("OPC_MXU_S16LDD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16STD:
/* TODO: Implement emulation of S16STD instruction. */
MIPS_INVAL("OPC_MXU_S16STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16LDI:
/* TODO: Implement emulation of S16LDI instruction. */
MIPS_INVAL("OPC_MXU_S16LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16SDI:
/* TODO: Implement emulation of S16SDI instruction. */
MIPS_INVAL("OPC_MXU_S16SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLL:
/* TODO: Implement emulation of D32SLL instruction. */
MIPS_INVAL("OPC_MXU_D32SLL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLR:
/* TODO: Implement emulation of D32SLR instruction. */
MIPS_INVAL("OPC_MXU_D32SLR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SARL:
/* TODO: Implement emulation of D32SARL instruction. */
MIPS_INVAL("OPC_MXU_D32SARL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SAR:
/* TODO: Implement emulation of D32SAR instruction. */
MIPS_INVAL("OPC_MXU_D32SAR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLL:
/* TODO: Implement emulation of Q16SLL instruction. */
MIPS_INVAL("OPC_MXU_Q16SLL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLR:
/* TODO: Implement emulation of Q16SLR instruction. */
MIPS_INVAL("OPC_MXU_Q16SLR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL18:
decode_opc_mxu__pool18(env, ctx);
@@ -27458,7 +27463,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q16SAR:
/* TODO: Implement emulation of Q16SAR instruction. */
MIPS_INVAL("OPC_MXU_Q16SAR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL19:
decode_opc_mxu__pool19(env, ctx);
@@ -27472,26 +27477,26 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MXU_Q16SCOP:
/* TODO: Implement emulation of Q16SCOP instruction. */
MIPS_INVAL("OPC_MXU_Q16SCOP");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MADL:
/* TODO: Implement emulation of Q8MADL instruction. */
MIPS_INVAL("OPC_MXU_Q8MADL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SFL:
/* TODO: Implement emulation of S32SFL instruction. */
MIPS_INVAL("OPC_MXU_S32SFL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8SAD:
/* TODO: Implement emulation of Q8SAD instruction. */
MIPS_INVAL("OPC_MXU_Q8SAD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
gen_set_label(l_exit);
@@ -27570,7 +27575,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special2_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27592,7 +27597,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext
*ctx)
case R6_OPC_PREF:
if (rt >= 24) {
/* hint codes 24-31 are reserved and signal RI */
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
/* Treat as NOP. */
break;
@@ -27631,7 +27636,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext
*ctx)
#ifndef CONFIG_USER_ONLY
case OPC_GINV:
if (unlikely(ctx->gi <= 1)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
check_cp0_enabled(ctx);
switch ((ctx->opcode >> 6) & 3) {
@@ -27642,7 +27647,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext
*ctx)
gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27683,7 +27688,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext
*ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special3_r6");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27734,13 +27739,13 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default:
MIPS_INVAL("MASK ADDUH.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else if (ctx->insn_flags & INSN_LOONGSON2E) {
gen_loongson_integer(ctx, op1, rd, rs, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case OPC_LX_DSP:
@@ -27756,7 +27761,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27787,7 +27792,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default:
MIPS_INVAL("MASK ABSQ_S.PH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27824,7 +27829,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ADDU.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -27864,7 +27869,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK CMPU.EQ.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27900,7 +27905,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK DPAW.PH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27930,7 +27935,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
}
default: /* Invalid */
MIPS_INVAL("MASK INSV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27965,7 +27970,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK EXTR.W");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28011,7 +28016,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ABSQ_S.QH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28050,7 +28055,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ADDU.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28095,7 +28100,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK CMPU_EQ.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28132,7 +28137,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK EXTR.W");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28171,7 +28176,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK DPAQ.W.QH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28201,7 +28206,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
}
default: /* Invalid */
MIPS_INVAL("MASK DINSV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28211,7 +28216,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env,
DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special3_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28249,11 +28254,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */
case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */
case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28281,11 +28286,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28316,14 +28321,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
case MMI_OPC_2_PCPYLD:
gen_mmi_pcpyld(ctx);
break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28344,7 +28349,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
@@ -28354,7 +28359,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28408,23 +28413,23 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */
case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */
case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */
break;
default:
MIPS_INVAL("TX79 MMI class");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
}
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
}
/*
@@ -28632,7 +28637,7 @@ static inline int check_msa_access(DisasContext *ctx)
{
if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
!(ctx->hflags & MIPS_HFLAG_F64))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 0;
}
@@ -28641,7 +28646,7 @@ static inline int check_msa_access(DisasContext *ctx)
generate_exception_end(ctx, EXCP_MSADIS);
return 0;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 0;
}
}
@@ -28698,7 +28703,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx,
uint32_t op1)
check_msa_access(ctx);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
switch (op1) {
@@ -28773,7 +28778,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
{
uint8_t df = (ctx->opcode >> 24) & 0x3;
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
TCGv_i32 tdf = tcg_const_i32(df);
gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
@@ -28783,7 +28788,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -28855,7 +28860,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -28891,7 +28896,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
m = dfm & 0x7;
df = DF_BYTE;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -28939,7 +28944,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -29784,7 +29789,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_HSUB_S_df:
case OPC_HSUB_U_df:
if (df == DF_BYTE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
switch (MASK_MSA_3R(ctx->opcode)) {
@@ -29922,7 +29927,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free_i32(twd);
@@ -29954,7 +29959,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -29991,12 +29996,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx,
uint32_t df,
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
(df == DF_WORD)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
#endif
@@ -30066,7 +30071,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx,
uint32_t df,
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
@@ -30096,7 +30101,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
gen_msa_elm_3e(env, ctx);
return;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -30251,7 +30256,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30279,7 +30284,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
#endif
@@ -30335,7 +30340,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30450,7 +30455,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30479,7 +30484,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -30577,7 +30582,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30661,7 +30666,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
} else {
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
@@ -30680,7 +30685,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS_R2);
@@ -30715,7 +30720,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("regimm");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -30824,7 +30829,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -30841,7 +30846,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -30877,7 +30882,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
/* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
@@ -30890,7 +30895,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
/* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
@@ -31139,7 +31144,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp1");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -31225,7 +31230,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp3");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else {
@@ -31290,7 +31295,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
MIPS_INVAL("major opcode");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
#endif
@@ -31308,7 +31313,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free(t0);
}
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
MIPS_INVAL("major opcode");
#endif
} else {
@@ -31334,7 +31339,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -31439,7 +31444,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase,
CPUState *cs)
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_mips16_opc(env, ctx);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
g_assert(ctx->base.is_jmp == DISAS_NORETURN);
return;
}
--
2.26.2
4:22 p.m.
New subject: [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h'
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-15-f4bug(a)amsat.org>
---
target/mips/translate.h | 7 +++++++
target/mips/translate.c | 12 ++++++------
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 5f744c63374..4c30a328e4b 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -60,12 +60,19 @@ void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
#endif
+void check_cp1_enabled(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+int get_fp_bit(int cc);
+
extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
extern TCGv bcond;
#define LOG_DISAS(...) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7c20ed33df7..610fba61de4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
@@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int
reg)
}
}
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
{
if (cc) {
return 24 + cc;
@@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
}
}
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
--
2.26.2
4:22 p.m.
New subject: [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201214183739.500368-16-f4bug(a)amsat.org>
---
target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 70 ----------------------------------------
2 files changed, 71 insertions(+), 70 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 4c30a328e4b..c70bca998fb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -52,6 +52,77 @@ typedef struct DisasContext {
/* MIPS major opcodes */
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
+#define OPC_CP1 (0x11 << 26)
+
+/* Coprocessor 1 (rs field) */
+#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
+
+/* Values for the fmt field in FP instructions */
+enum {
+ /* 0 - 15 are reserved */
+ FMT_S = 16, /* single fp */
+ FMT_D = 17, /* double fp */
+ FMT_E = 18, /* extended fp */
+ FMT_Q = 19, /* quad fp */
+ FMT_W = 20, /* 32-bit fixed */
+ FMT_L = 21, /* 64-bit fixed */
+ FMT_PS = 22, /* paired single fp */
+ /* 23 - 31 are reserved */
+};
+
+enum {
+ OPC_MFC1 = (0x00 << 21) | OPC_CP1,
+ OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
+ OPC_CFC1 = (0x02 << 21) | OPC_CP1,
+ OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
+ OPC_MTC1 = (0x04 << 21) | OPC_CP1,
+ OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
+ OPC_CTC1 = (0x06 << 21) | OPC_CP1,
+ OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
+ OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
+ OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
+ OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
+ OPC_BZ_V = (0x0B << 21) | OPC_CP1,
+ OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
+ OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
+ OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
+ OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
+ OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
+ OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
+ OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
+ OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
+ OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
+ OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
+ OPC_BZ_B = (0x18 << 21) | OPC_CP1,
+ OPC_BZ_H = (0x19 << 21) | OPC_CP1,
+ OPC_BZ_W = (0x1A << 21) | OPC_CP1,
+ OPC_BZ_D = (0x1B << 21) | OPC_CP1,
+ OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
+ OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
+ OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
+ OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
+};
+
+#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
+#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
+
+enum {
+ OPC_BC1F = (0x00 << 16) | OPC_BC1,
+ OPC_BC1T = (0x01 << 16) | OPC_BC1,
+ OPC_BC1FL = (0x02 << 16) | OPC_BC1,
+ OPC_BC1TL = (0x03 << 16) | OPC_BC1,
+};
+
+enum {
+ OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
+ OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
+};
+
+enum {
+ OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
+ OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
+};
+
void generate_exception(DisasContext *ctx, int excp);
void generate_exception_err(DisasContext *ctx, int excp, int err);
void generate_exception_end(DisasContext *ctx, int excp);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 610fba61de4..39b57794b36 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -43,7 +43,6 @@ enum {
OPC_SPECIAL = (0x00 << 26),
OPC_REGIMM = (0x01 << 26),
OPC_CP0 = (0x10 << 26),
- OPC_CP1 = (0x11 << 26),
OPC_CP2 = (0x12 << 26),
OPC_CP3 = (0x13 << 26),
OPC_SPECIAL2 = (0x1C << 26),
@@ -996,75 +995,6 @@ enum {
OPC_WAIT = 0x20 | OPC_C0,
};
-/* Coprocessor 1 (rs field) */
-#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
-
-/* Values for the fmt field in FP instructions */
-enum {
- /* 0 - 15 are reserved */
- FMT_S = 16, /* single fp */
- FMT_D = 17, /* double fp */
- FMT_E = 18, /* extended fp */
- FMT_Q = 19, /* quad fp */
- FMT_W = 20, /* 32-bit fixed */
- FMT_L = 21, /* 64-bit fixed */
- FMT_PS = 22, /* paired single fp */
- /* 23 - 31 are reserved */
-};
-
-enum {
- OPC_MFC1 = (0x00 << 21) | OPC_CP1,
- OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
- OPC_CFC1 = (0x02 << 21) | OPC_CP1,
- OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
- OPC_MTC1 = (0x04 << 21) | OPC_CP1,
- OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
- OPC_CTC1 = (0x06 << 21) | OPC_CP1,
- OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
- OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
- OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
- OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
- OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
- OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
- OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
- OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
- OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
- OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
- OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
- OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
- OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
-};
-
-#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
-#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
-
-enum {
- OPC_BC1F = (0x00 << 16) | OPC_BC1,
- OPC_BC1T = (0x01 << 16) | OPC_BC1,
- OPC_BC1FL = (0x02 << 16) | OPC_BC1,
- OPC_BC1TL = (0x03 << 16) | OPC_BC1,
-};
-
-enum {
- OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
- OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
-};
-
-enum {
- OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
- OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
-};
-
#define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
enum {
--
2.26.2
4:22 p.m.
New subject: [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug(a)amsat.org>
---
target/mips/meson.build | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5a49951c6d7..596eb1aeeb3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,9 +1,11 @@
mips_ss = ss.source_set()
mips_ss.add(files(
'cpu.c',
+ 'gdbstub.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
'dsp_helper.c',
'fpu_helper.c',
- 'gdbstub.c',
'lmmi_helper.c',
'msa_helper.c',
'op_helper.c',
@@ -15,11 +17,13 @@
mips_softmmu_ss = ss.source_set()
mips_softmmu_ss.add(files(
'addr.c',
- 'cp0_helper.c',
'cp0_timer.c',
'machine.c',
'mips-semi.c',
))
+mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'cp0_helper.c',
+))
target_arch += {'mips': mips_ss}
target_softmmu_arch += {'mips': mips_softmmu_ss}
--
2.26.2
4:22 p.m.
New subject: [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc()
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-2-f4bug(a)amsat.org>
---
target/mips/translate.c | 45 ++++++++++++++++++++++++-----------------
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 39b57794b36..7d2120dd51c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -30518,30 +30518,13 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
}
-static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1;
int16_t imm;
- /* make sure instructions are on a word boundary */
- if (ctx->base.pc_next & 0x3) {
- env->CP0_BadVAddr = ctx->base.pc_next;
- generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
- return;
- }
-
- /* Handle blikely not taken case */
- if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
- TCGLabel *l1 = gen_new_label();
-
- tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
- tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
- gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
- gen_set_label(l1);
- }
-
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -31269,8 +31252,32 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
+ return false;
+ }
+ return true;
+}
+
+static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ /* make sure instructions are on a word boundary */
+ if (ctx->base.pc_next & 0x3) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
+ generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
+ return;
+ }
+
+ /* Handle blikely not taken case */
+ if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
+ TCGLabel *l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
+ tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l1);
+ }
+
+ if (!decode_opc_legacy(env, ctx)) {
gen_reserved_instruction(ctx);
- break;
}
}
--
2.26.2
4:22 p.m.
New subject: [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug(a)amsat.org>
---
target/mips/translate.h | 2 --
target/mips/translate.c | 8 +++-----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index c70bca998fb..402bc5e8846 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -128,9 +128,7 @@ void generate_exception_err(DisasContext *ctx, int excp, int err);
void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
-#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
-#endif
void check_cp1_enabled(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7d2120dd51c..69fa8a50790 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
-#ifdef TARGET_MIPS64
/*
- * This code generates a "reserved instruction" exception if 64-bit
- * instructions are not enabled.
+ * This code generates a "reserved instruction" exception if cpu is not
+ * 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
+ if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
gen_reserved_instruction(ctx);
}
}
-#endif
#ifndef CONFIG_USER_ONLY
static inline void check_mvh(DisasContext *ctx)
--
2.26.2
4:22 p.m.
New subject: [PULL 37/66] target/mips: Introduce ase_msa_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug(a)amsat.org>
---
target/mips/cpu.h | 6 ++++++
target/mips/cpu.c | 2 +-
target/mips/kvm.c | 12 ++++++------
target/mips/translate.c | 6 ++----
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c45744c5c1..b9e227a30e9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MSA implementation */
+static inline bool ase_msa_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MSAP);
+}
+
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 55c6a054bba..45375ebc45c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -532,7 +532,7 @@ static void mips_cpu_reset(DeviceState *dev)
}
/* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
msa_reset(env);
}
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index a5b6fe35dbc..84fb10ea35d 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -79,7 +79,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
- if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (kvm_mips_msa_cap && ase_msa_available(env)) {
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
if (ret < 0) {
/* mark unsupported so it gets disabled on reset */
@@ -105,7 +105,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu)
warn_report("KVM does not support FPU, disabling");
env->CP0_Config1 &= ~(1 << CP0C1_FP);
}
- if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP))
{
+ if (!kvm_mips_msa_cap && ase_msa_available(env)) {
warn_report("KVM does not support MSA, disabling");
env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
}
@@ -618,7 +618,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
* FPU register state is a subset of MSA vector state, so don't put FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -637,7 +637,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
}
/* Only put MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
if (level == KVM_PUT_FULL_STATE) {
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
@@ -698,7 +698,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
* FPU register state is a subset of MSA vector state, so don't save FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -717,7 +717,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
}
/* Only get MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
&env->msair);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 69fa8a50790..c01db5f9d39 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24920,8 +24920,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS_R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
@@ -25023,8 +25022,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS_R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;
--
2.26.2
4:22 p.m.
New subject: [PULL 38/66] target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug(a)amsat.org>
---
target/mips/cpu.c | 5 +----
target/mips/cpu-defs.c.inc | 4 ++++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 45375ebc45c..4c590b90b25 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -531,10 +531,7 @@ static void mips_cpu_reset(DeviceState *dev)
env->hflags |= MIPS_HFLAG_M16;
}
- /* MSA */
- if (ase_msa_available(env)) {
- msa_reset(env);
- }
+ msa_reset(env);
compute_hflags(env);
restore_fp_status(env);
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 535d4c0c702..fe0f47aadf8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -978,6 +978,10 @@ static void mvp_init(CPUMIPSState *env)
static void msa_reset(CPUMIPSState *env)
{
+ if (!ase_msa_available(env)) {
+ return;
+ }
+
#ifdef CONFIG_USER_ONLY
/* MSA access enabled */
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
--
2.26.2
4:22 p.m.
New subject: [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-4-f4bug(a)amsat.org>
---
target/mips/internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 9a7698019e2..1048781bcf4 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -378,7 +378,7 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_COP1X;
}
}
- if (env->insn_flags & ASE_MSA) {
+ if (ase_msa_available(env)) {
if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
env->hflags |= MIPS_HFLAG_MSA;
}
--
2.26.2
4:22 p.m.
New subject: [PULL 40/66] target/mips: Simplify MSA TCG logic
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-5-f4bug(a)amsat.org>
---
target/mips/translate.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c01db5f9d39..e3cea5899f3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28568,13 +28568,8 @@ static inline int check_msa_access(DisasContext *ctx)
}
if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
- if (ctx->insn_flags & ASE_MSA) {
- generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
- } else {
- gen_reserved_instruction(ctx);
- return 0;
- }
+ generate_exception_end(ctx, EXCP_MSADIS);
+ return 0;
}
return 1;
}
@@ -30418,7 +30413,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
- check_insn(ctx, ASE_MSA);
+
check_msa_access(ctx);
switch (MASK_MSA_MINOR(opcode)) {
@@ -31048,9 +31043,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- check_insn(ctx, ASE_MSA);
- gen_msa_branch(env, ctx, op1);
- break;
+ if (ase_msa_available(env)) {
+ gen_msa_branch(env, ctx, op1);
+ break;
+ }
+ /* fall through */
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@@ -31239,7 +31236,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
#endif
} else {
/* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ase_msa_available(env)) {
+ gen_msa(env, ctx);
+ }
}
break;
case OPC_PCREL:
--
2.26.2
4:22 p.m.
New subject: [PULL 41/66] target/mips: Remove now unused ASE_MSA definition
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-6-f4bug(a)amsat.org>
---
target/mips/mips-defs.h | 1 -
target/mips/cpu-defs.c.inc | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 97866019a72..6b8e6800115 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -34,7 +34,6 @@
#define ASE_MT 0x0000000040000000ULL
#define ASE_SMARTMIPS 0x0000000080000000ULL
#define ASE_MICROMIPS 0x0000000100000000ULL
-#define ASE_MSA 0x0000000200000000ULL
/*
* bits 40-51: vendor-specific base instruction sets
*/
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index fe0f47aadf8..3d44b394773 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -410,7 +410,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 32,
.PABITS = 40,
- .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+ .insn_flags = CPU_MIPS32R5,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -723,7 +723,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -763,7 +763,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -889,7 +889,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A | ASE_MSA,
+ .insn_flags = CPU_LOONGSON3A,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
4:22 p.m.
New subject: [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.
Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-7-f4bug(a)amsat.org>
---
target/mips/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e3cea5899f3..30354fee828 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31561,16 +31561,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
-
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- msa_wr_d[i * 2] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+
+ fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ }
+ /* MSA */
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
/*
- * The scalar floating-point unit (FPU) registers are mapped on
- * the MSA vector registers.
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
*/
- fpu_f64[i] = msa_wr_d[i * 2];
+ msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.26.2
4:22 p.m.
New subject: [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init()
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic initialization. We will later move this
function along with the MSA registers to the new C unit.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-8-f4bug(a)amsat.org>
---
target/mips/translate.h | 3 +++
target/mips/translate.c | 33 +++++++++++++++++++--------------
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 402bc5e8846..b9cd315c7f4 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -162,4 +162,7 @@ extern TCGv bcond;
} \
} while (0)
+/* MSA */
+void msa_translate_init(void);
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 30354fee828..bb9420b9f7f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
+void msa_translate_init(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
+ /*
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
+ */
+ msa_wr_d[i * 2] = fpu_f64[i];
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ }
+}
+
void mips_tcg_init(void)
{
int i;
@@ -31566,20 +31584,7 @@ void mips_tcg_init(void)
fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
}
- /* MSA */
- for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
-
- /*
- * The MSA vector registers are mapped on the
- * scalar floating-point unit (FPU) registers.
- */
- msa_wr_d[i * 2] = fpu_f64[i];
- off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
- msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
- }
-
+ msa_translate_init();
cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
--
2.26.2
4:22 p.m.
New subject: [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-9-f4bug(a)amsat.org>
---
target/mips/translate.c | 57 ++++++++++++++++++++---------------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bb9420b9f7f..18cebe26bde 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28615,7 +28615,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df,
uint8_t wt)
tcg_temp_free_i64(t1);
}
-static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
+static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -28660,7 +28660,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx,
uint32_t op1)
ctx->hflags |= MIPS_HFLAG_BDS32;
}
-static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
uint8_t i8 = (ctx->opcode >> 16) & 0xff;
@@ -28718,7 +28718,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
-static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_i5(DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -28791,7 +28791,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(timm);
}
-static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_bit(DisasContext *ctx)
{
#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
@@ -28875,7 +28875,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tws);
}
-static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -29857,7 +29857,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
uint8_t source = (ctx->opcode >> 11) & 0x1f;
@@ -29889,8 +29889,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tsr);
}
-static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
- uint32_t n)
+static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
@@ -30000,7 +29999,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx,
uint32_t df,
tcg_temp_free_i32(tdf);
}
-static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
uint32_t df = 0, n = 0;
@@ -30019,17 +30018,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
df = DF_DOUBLE;
} else if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
- gen_msa_elm_3e(env, ctx);
+ gen_msa_elm_3e(ctx);
return;
} else {
gen_reserved_instruction(ctx);
return;
}
- gen_msa_elm_df(env, ctx, df, n);
+ gen_msa_elm_df(ctx, df, n);
}
-static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_3rf(DisasContext *ctx)
{
#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t df = (ctx->opcode >> 21) & 0x1;
@@ -30187,7 +30186,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
@@ -30271,7 +30270,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
@@ -30342,7 +30341,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -30385,7 +30384,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(twt);
}
-static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_vec(DisasContext *ctx)
{
switch (MASK_MSA_VEC(ctx->opcode)) {
case OPC_AND_V:
@@ -30395,13 +30394,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
case OPC_BMNZ_V:
case OPC_BMZ_V:
case OPC_BSEL_V:
- gen_msa_vec_v(env, ctx);
+ gen_msa_vec_v(ctx);
break;
case OPC_MSA_2R:
- gen_msa_2r(env, ctx);
+ gen_msa_2r(ctx);
break;
case OPC_MSA_2RF:
- gen_msa_2rf(env, ctx);
+ gen_msa_2rf(ctx);
break;
default:
MIPS_INVAL("MSA instruction");
@@ -30410,7 +30409,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
}
}
-static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
@@ -30420,15 +30419,15 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_I8_00:
case OPC_MSA_I8_01:
case OPC_MSA_I8_02:
- gen_msa_i8(env, ctx);
+ gen_msa_i8(ctx);
break;
case OPC_MSA_I5_06:
case OPC_MSA_I5_07:
- gen_msa_i5(env, ctx);
+ gen_msa_i5(ctx);
break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
- gen_msa_bit(env, ctx);
+ gen_msa_bit(ctx);
break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
@@ -30439,18 +30438,18 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_3R_13:
case OPC_MSA_3R_14:
case OPC_MSA_3R_15:
- gen_msa_3r(env, ctx);
+ gen_msa_3r(ctx);
break;
case OPC_MSA_ELM:
- gen_msa_elm(env, ctx);
+ gen_msa_elm(ctx);
break;
case OPC_MSA_3RF_1A:
case OPC_MSA_3RF_1B:
case OPC_MSA_3RF_1C:
- gen_msa_3rf(env, ctx);
+ gen_msa_3rf(ctx);
break;
case OPC_MSA_VEC:
- gen_msa_vec(env, ctx);
+ gen_msa_vec(ctx);
break;
case OPC_LD_B:
case OPC_LD_H:
@@ -31044,7 +31043,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
case OPC_BNZ_W:
case OPC_BNZ_D:
if (ase_msa_available(env)) {
- gen_msa_branch(env, ctx, op1);
+ gen_msa_branch(ctx, op1);
break;
}
/* fall through */
@@ -31237,7 +31236,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
} else {
/* MDMX: Not implemented. */
if (ase_msa_available(env)) {
- gen_msa(env, ctx);
+ gen_msa(ctx);
}
}
break;
--
2.26.2
4:22 p.m.
New subject: [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Message-Id: <20201208003702.4088927-10-f4bug(a)amsat.org>
---
target/mips/translate.c | 71 ++++++++++++++++++++++++++++-------------
1 file changed, 49 insertions(+), 22 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 18cebe26bde..0e7b2abe8bb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28615,49 +28615,76 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df,
uint8_t wt)
tcg_temp_free_i64(t1);
}
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+{
+ TCGv_i64 t0;
+
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
+ tcg_gen_trunc_i64_tl(bcond, t0);
+ tcg_temp_free_i64(t0);
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
+{
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ gen_check_zero_element(bcond, df, wt);
+ if (if_not) {
+ tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ }
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
int64_t s16 = (int16_t)ctx->opcode;
- check_msa_access(ctx);
-
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- gen_reserved_instruction(ctx);
- return;
- }
switch (op1) {
case OPC_BZ_V:
case OPC_BNZ_V:
- {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
- tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
- tcg_gen_trunc_i64_tl(bcond, t0);
- tcg_temp_free_i64(t0);
- }
+ gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
+ TCG_COND_EQ : TCG_COND_NE);
break;
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
- gen_check_zero_element(bcond, df, wt);
+ gen_msa_BxZ(ctx, df, wt, s16, false);
break;
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- gen_check_zero_element(bcond, df, wt);
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ gen_msa_BxZ(ctx, df, wt, s16, true);
break;
}
-
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
-
- ctx->hflags |= MIPS_HFLAG_BC;
- ctx->hflags |= MIPS_HFLAG_BDS32;
}
static void gen_msa_i8(DisasContext *ctx)
--
2.26.2
4:22 p.m.
New subject: [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-15-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/internal.h | 2 ++
target/mips/cpu.c | 1 +
target/mips/msa_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/mips/cpu-defs.c.inc | 36 ------------------------------------
4 files changed, 39 insertions(+), 36 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1048781bcf4..5dd17ff7333 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -199,6 +199,8 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
void mips_tcg_init(void);
+void msa_reset(CPUMIPSState *env);
+
/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4c590b90b25..f45164012a4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -33,6 +33,7 @@
#include "hw/qdev-clock.h"
#include "hw/semihosting/semihost.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "fpu_helper.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index b89b4c44902..f0d728c03f0 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t
wd,
msa_move_v(pwd, pwx);
}
+
+void msa_reset(CPUMIPSState *env)
+{
+ if (!ase_msa_available(env)) {
+ return;
+ }
+
+#ifdef CONFIG_USER_ONLY
+ /* MSA access enabled */
+ env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+ env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+ /*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+ env->active_tc.msacsr = 0;
+
+ restore_msa_fp_status(env);
+
+ /* tininess detected after rounding.*/
+ set_float_detect_tininess(float_tininess_after_rounding,
+ &env->active_tc.msa_fp_status);
+
+ /* clear float_status exception flags */
+ set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+ /* clear float_status nan mode */
+ set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+ /* set proper signanling bit meaning ("1" means "quiet") */
+ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 3d44b394773..ba22ff4bcd1 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -18,8 +18,6 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>;.
*/
-#include "fpu_helper.h"
-
/* CPU / CPU family specific config register values. */
/* Have config1, uncached coherency */
@@ -975,37 +973,3 @@ static void mvp_init(CPUMIPSState *env)
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2)
|
(0x1 << CP0MVPC1_PCP1);
}
-
-static void msa_reset(CPUMIPSState *env)
-{
- if (!ase_msa_available(env)) {
- return;
- }
-
-#ifdef CONFIG_USER_ONLY
- /* MSA access enabled */
- env->CP0_Config5 |= 1 << CP0C5_MSAEn;
- env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
- /* MSA CSR:
- - non-signaling floating point exception mode off (NX bit is 0)
- - Cause, Enables, and Flags are all 0
- - round to nearest / ties to even (RM bits are 0) */
- env->active_tc.msacsr = 0;
-
- restore_msa_fp_status(env);
-
- /* tininess detected after rounding.*/
- set_float_detect_tininess(float_tininess_after_rounding,
- &env->active_tc.msa_fp_status);
-
- /* clear float_status exception flags */
- set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
- /* clear float_status nan mode */
- set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
- /* set proper signanling bit meaning ("1" means "quiet") */
- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
--
2.26.2
4:22 p.m.
New subject: [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201123204448.3260804-5-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/msa_helper.c | 393 ++++++++++++++++++++++++++++++++++++++
target/mips/op_helper.c | 394 ---------------------------------------
2 files changed, 393 insertions(+), 394 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f0d728c03f0..1298a1917ce 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -22,6 +22,7 @@
#include "internal.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "exec/memop.h"
#include "fpu/softfloat.h"
#include "fpu_helper.h"
@@ -8202,6 +8203,398 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
msa_move_v(pwd, pwx);
}
+/* Data format min and max values */
+#define DF_BITS(df) (1 << ((df) + 3))
+
+/* Element-by-element access macros */
+#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
+
+#if !defined(CONFIG_USER_ONLY)
+#define MEMOP_IDX(DF) \
+ TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ cpu_mmu_index(env, false));
+#else
+#define MEMOP_IDX(DF)
+#endif
+
+void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_BYTE)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+#else
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+#else
+ pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+#endif
+#endif
+}
+
+void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_HALF)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+#else
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+#else
+ pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+#endif
+#endif
+}
+
+void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_WORD)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+#else
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+#else
+ pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+#endif
+#endif
+}
+
+void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_DOUBLE)
+#if !defined(CONFIG_USER_ONLY)
+ pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
+ pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
+#else
+ pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
+ pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
+#endif
+}
+
+#define MSA_PAGESPAN(x) \
+ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
+
+static inline void ensure_writable_pages(CPUMIPSState *env,
+ target_ulong addr,
+ int mmu_idx,
+ uintptr_t retaddr)
+{
+ /* FIXME: Probe the actual accesses (pass and use a size) */
+ if (unlikely(MSA_PAGESPAN(addr))) {
+ /* first page */
+ probe_write(env, addr, 0, mmu_idx, retaddr);
+ /* second page */
+ addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ probe_write(env, addr, 0, mmu_idx, retaddr);
+ }
+}
+
+void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_BYTE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
+#else
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
+#else
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
+#endif
+#endif
+}
+
+void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_HALF)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
+#else
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
+#else
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
+#endif
+#endif
+}
+
+void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_WORD)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
+#else
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
+#else
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
+#endif
+#endif
+}
+
+void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_DOUBLE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+ helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
+ helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
+#else
+ cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
+ cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
+#endif
+}
+
void msa_reset(CPUMIPSState *env)
{
if (!ase_msa_available(env)) {
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 3386b8228e9..89c7d4556a0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1173,400 +1173,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
}
#endif /* !CONFIG_USER_ONLY */
-
-/* MSA */
-/* Data format min and max values */
-#define DF_BITS(df) (1 << ((df) + 3))
-
-/* Element-by-element access macros */
-#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
-
-#if !defined(CONFIG_USER_ONLY)
-#define MEMOP_IDX(DF) \
- TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
- cpu_mmu_index(env, false));
-#else
-#define MEMOP_IDX(DF)
-#endif
-
-void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_BYTE)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
-#else
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
-#else
- pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
-#endif
-#endif
-}
-
-void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_HALF)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
-#else
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
-#else
- pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
-#endif
-#endif
-}
-
-void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_WORD)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
-#else
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
-#else
- pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
-#endif
-#endif
-}
-
-void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_DOUBLE)
-#if !defined(CONFIG_USER_ONLY)
- pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
- pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
-#else
- pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
- pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
-#endif
-}
-
-#define MSA_PAGESPAN(x) \
- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
-
-static inline void ensure_writable_pages(CPUMIPSState *env,
- target_ulong addr,
- int mmu_idx,
- uintptr_t retaddr)
-{
- /* FIXME: Probe the actual accesses (pass and use a size) */
- if (unlikely(MSA_PAGESPAN(addr))) {
- /* first page */
- probe_write(env, addr, 0, mmu_idx, retaddr);
- /* second page */
- addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- probe_write(env, addr, 0, mmu_idx, retaddr);
- }
-}
-
-void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_BYTE)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
-#else
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
-#else
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
-#endif
-#endif
-}
-
-void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_HALF)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
-#else
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
-#else
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
-#endif
-#endif
-}
-
-void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_WORD)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
-#else
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
-#else
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
-#endif
-#endif
-}
-
-void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_DOUBLE)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
- helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
- helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
-#else
- cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
- cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
-#endif
-}
-
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#ifndef CONFIG_USER_ONLY
--
2.26.2
4:22 p.m.
New subject: [PULL 48/66] target/mips: Extract MSA helper definitions
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Message-Id: <20201120210844.2625602-4-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/helper.h | 436 +---------------------------------
target/mips/msa_helper.h.inc | 443 +++++++++++++++++++++++++++++++++++
2 files changed, 445 insertions(+), 434 deletions(-)
create mode 100644 target/mips/msa_helper.h.inc
diff --git a/target/mips/helper.h b/target/mips/helper.h
index e97655dc0eb..709494445dd 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -781,438 +781,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
-/* MIPS SIMD Architecture */
-
-DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
-
-DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
-
-DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
-
-DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_3(msa_move_v, void, env, i32, i32)
-
-DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32)
-
-DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
-DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
-
-DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)
-
-#define MSALDST_PROTO(type) \
-DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \
-DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)
-MSALDST_PROTO(b)
-MSALDST_PROTO(h)
-MSALDST_PROTO(w)
-MSALDST_PROTO(d)
-#undef MSALDST_PROTO
-
DEF_HELPER_3(cache, void, env, tl, i32)
+
+#include "msa_helper.h.inc"
diff --git a/target/mips/msa_helper.h.inc b/target/mips/msa_helper.h.inc
new file mode 100644
index 00000000000..4963d1553a0
--- /dev/null
+++ b/target/mips/msa_helper.h.inc
@@ -0,0 +1,443 @@
+/*
+ * MIPS SIMD Architecture Module (MSA) helpers for QEMU.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
+ * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
+
+DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
+
+DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
+
+DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_3(msa_move_v, void, env, i32, i32)
+
+DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32)
+DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32)
+
+DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
+DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
+DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
+
+DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)
+
+#define MSALDST_PROTO(type) \
+DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \
+DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)
+MSALDST_PROTO(b)
+MSALDST_PROTO(h)
+MSALDST_PROTO(w)
+MSALDST_PROTO(d)
+#undef MSALDST_PROTO
--
2.26.2
4:22 p.m.
New subject: [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h'
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-18-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index b9cd315c7f4..c61c11978c2 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -164,5 +164,7 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
+void gen_msa(DisasContext *ctx);
+void gen_msa_branch(DisasContext *ctx, uint32_t op1);
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0e7b2abe8bb..e1763e5bcec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28660,7 +28660,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int
s16, bool if_not)
return true;
}
-static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
+void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -30436,7 +30436,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-static void gen_msa(DisasContext *ctx)
+void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
--
2.26.2
4:22 p.m.
New subject: [PULL 50/66] target/mips: Extract MSA translation routines
Extract 2200 lines from the huge translate.c to a new file,
'msa_translate.c'. As there are too many inter-dependencies
we don't compile it as another object yet, but keep including
it in the big translate.o. We gain in code maintainability.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201120210844.2625602-5-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/msa_translate.c | 2265 +++++++++++++++++++++++++++++++++++
target/mips/translate.c | 2249 ----------------------------------
target/mips/meson.build | 1 +
3 files changed, 2266 insertions(+), 2249 deletions(-)
create mode 100644 target/mips/msa_translate.c
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
new file mode 100644
index 00000000000..a4f9a6c1285
--- /dev/null
+++ b/target/mips/msa_translate.c
@@ -0,0 +1,2265 @@
+/*
+ * MIPS SIMD Architecture (MSA) translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
+ * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+#include "fpu_helper.h"
+#include "internal.h"
+
+#define OPC_MSA (0x1E << 26)
+
+#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
+enum {
+ OPC_MSA_I8_00 = 0x00 | OPC_MSA,
+ OPC_MSA_I8_01 = 0x01 | OPC_MSA,
+ OPC_MSA_I8_02 = 0x02 | OPC_MSA,
+ OPC_MSA_I5_06 = 0x06 | OPC_MSA,
+ OPC_MSA_I5_07 = 0x07 | OPC_MSA,
+ OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
+ OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
+ OPC_MSA_3R_0D = 0x0D | OPC_MSA,
+ OPC_MSA_3R_0E = 0x0E | OPC_MSA,
+ OPC_MSA_3R_0F = 0x0F | OPC_MSA,
+ OPC_MSA_3R_10 = 0x10 | OPC_MSA,
+ OPC_MSA_3R_11 = 0x11 | OPC_MSA,
+ OPC_MSA_3R_12 = 0x12 | OPC_MSA,
+ OPC_MSA_3R_13 = 0x13 | OPC_MSA,
+ OPC_MSA_3R_14 = 0x14 | OPC_MSA,
+ OPC_MSA_3R_15 = 0x15 | OPC_MSA,
+ OPC_MSA_ELM = 0x19 | OPC_MSA,
+ OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
+ OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
+ OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
+ OPC_MSA_VEC = 0x1E | OPC_MSA,
+
+ /* MI10 instruction */
+ OPC_LD_B = (0x20) | OPC_MSA,
+ OPC_LD_H = (0x21) | OPC_MSA,
+ OPC_LD_W = (0x22) | OPC_MSA,
+ OPC_LD_D = (0x23) | OPC_MSA,
+ OPC_ST_B = (0x24) | OPC_MSA,
+ OPC_ST_H = (0x25) | OPC_MSA,
+ OPC_ST_W = (0x26) | OPC_MSA,
+ OPC_ST_D = (0x27) | OPC_MSA,
+};
+
+enum {
+ /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
+ OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
+ OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
+ OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
+ OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
+ OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
+ OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
+ OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
+ OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
+ OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
+ OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
+ OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
+ OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
+
+ /* I8 instruction */
+ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
+ OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
+ OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
+ OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
+ OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
+ OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
+ OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
+ OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
+ OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
+ OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
+
+ /* VEC/2R/2RF instruction */
+ OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
+ OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
+ OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
+ OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
+ OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
+ OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
+ OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
+
+ OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
+ OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
+
+ /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
+ OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
+ OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
+ OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
+ OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
+
+ /* 2RF instruction df(bit 16) = _w, _d */
+ OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
+ OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
+ OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
+ OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
+ OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
+ OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
+ OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
+ OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
+ OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
+ OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
+ OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
+ OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
+ OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
+ OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
+ OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
+ OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
+
+ /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
+ OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
+ OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
+ OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
+ OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
+ OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
+ OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
+ OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
+ OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
+ OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
+ OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
+ OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
+ OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
+ OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
+ OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
+ OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
+ OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
+ OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
+ OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
+ OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
+ OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
+ OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
+ OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
+ OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
+ OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
+ OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
+ OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
+ OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
+ OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
+ OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
+ OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
+ OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
+ OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
+ OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
+ OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
+ OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
+ OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
+ OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
+ OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
+ OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
+ OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
+ OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
+ OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
+ OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
+ OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
+ OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
+ OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
+ OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
+ OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
+ OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
+ OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
+ OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
+ OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
+ OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
+ OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
+ OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
+ OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
+ OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
+ OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
+ OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
+ OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
+ OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
+ OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
+ OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
+
+ /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
+ OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+ OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
+ OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+ OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
+ OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+ OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
+ OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+ OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+ OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
+
+ /* 3RF instruction _df(bit 21) = _w, _d */
+ OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
+ OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
+ OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
+ OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
+ OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
+ OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
+ OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
+ OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
+ OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
+ OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
+ OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
+ OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
+ OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
+ OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
+ OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
+ OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
+ OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
+ OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
+ OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
+ OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
+ OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
+ OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
+ OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
+ OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
+ OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
+ OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
+ OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
+ OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
+ OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
+ OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
+ OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
+ OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
+ OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
+ OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
+ OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
+ OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
+
+ /* BIT instruction df(bits 22..16) = _B _H _W _D */
+ OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
+ OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
+ OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
+ OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
+ OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
+ OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
+ OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
+ OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
+ OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
+ OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
+ OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
+ OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
+};
+
+static const char * const msaregnames[] = {
+ "w0.d0", "w0.d1", "w1.d0", "w1.d1",
+ "w2.d0", "w2.d1", "w3.d0", "w3.d1",
+ "w4.d0", "w4.d1", "w5.d0", "w5.d1",
+ "w6.d0", "w6.d1", "w7.d0", "w7.d1",
+ "w8.d0", "w8.d1", "w9.d0", "w9.d1",
+ "w10.d0", "w10.d1", "w11.d0", "w11.d1",
+ "w12.d0", "w12.d1", "w13.d0", "w13.d1",
+ "w14.d0", "w14.d1", "w15.d0", "w15.d1",
+ "w16.d0", "w16.d1", "w17.d0", "w17.d1",
+ "w18.d0", "w18.d1", "w19.d0", "w19.d1",
+ "w20.d0", "w20.d1", "w21.d0", "w21.d1",
+ "w22.d0", "w22.d1", "w23.d0", "w23.d1",
+ "w24.d0", "w24.d1", "w25.d0", "w25.d1",
+ "w26.d0", "w26.d1", "w27.d0", "w27.d1",
+ "w28.d0", "w28.d1", "w29.d0", "w29.d1",
+ "w30.d0", "w30.d1", "w31.d0", "w31.d1",
+};
+
+static TCGv_i64 msa_wr_d[64];
+
+void msa_translate_init(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
+ /*
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
+ */
+ msa_wr_d[i * 2] = fpu_f64[i];
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ }
+}
+
+static inline int check_msa_access(DisasContext *ctx)
+{
+ if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
+ !(ctx->hflags & MIPS_HFLAG_F64))) {
+ gen_reserved_instruction(ctx);
+ return 0;
+ }
+
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
+ generate_exception_end(ctx, EXCP_MSADIS);
+ return 0;
+ }
+ return 1;
+}
+
+static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
+{
+ /* generates tcg ops to check if any element is 0 */
+ /* Note this function only works with MSA_WRLEN = 128 */
+ uint64_t eval_zero_or_big = 0;
+ uint64_t eval_big = 0;
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ switch (df) {
+ case DF_BYTE:
+ eval_zero_or_big = 0x0101010101010101ULL;
+ eval_big = 0x8080808080808080ULL;
+ break;
+ case DF_HALF:
+ eval_zero_or_big = 0x0001000100010001ULL;
+ eval_big = 0x8000800080008000ULL;
+ break;
+ case DF_WORD:
+ eval_zero_or_big = 0x0000000100000001ULL;
+ eval_big = 0x8000000080000000ULL;
+ break;
+ case DF_DOUBLE:
+ eval_zero_or_big = 0x0000000000000001ULL;
+ eval_big = 0x8000000000000000ULL;
+ break;
+ }
+ tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
+ tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
+ tcg_gen_andi_i64(t0, t0, eval_big);
+ tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big);
+ tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]);
+ tcg_gen_andi_i64(t1, t1, eval_big);
+ tcg_gen_or_i64(t0, t0, t1);
+ /* if all bits are zero then all elements are not zero */
+ /* if some bit is non-zero then some element is zero */
+ tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
+ tcg_gen_trunc_i64_tl(tresult, t0);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+{
+ TCGv_i64 t0;
+
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
+ tcg_gen_trunc_i64_tl(bcond, t0);
+ tcg_temp_free_i64(t0);
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
+{
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ gen_check_zero_element(bcond, df, wt);
+ if (if_not) {
+ tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ }
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
+void gen_msa_branch(DisasContext *ctx, uint32_t op1)
+{
+ uint8_t df = (ctx->opcode >> 21) & 0x3;
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ int64_t s16 = (int16_t)ctx->opcode;
+
+ switch (op1) {
+ case OPC_BZ_V:
+ case OPC_BNZ_V:
+ gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
+ TCG_COND_EQ : TCG_COND_NE);
+ break;
+ case OPC_BZ_B:
+ case OPC_BZ_H:
+ case OPC_BZ_W:
+ case OPC_BZ_D:
+ gen_msa_BxZ(ctx, df, wt, s16, false);
+ break;
+ case OPC_BNZ_B:
+ case OPC_BNZ_H:
+ case OPC_BNZ_W:
+ case OPC_BNZ_D:
+ gen_msa_BxZ(ctx, df, wt, s16, true);
+ break;
+ }
+}
+
+static void gen_msa_i8(DisasContext *ctx)
+{
+#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
+ uint8_t i8 = (ctx->opcode >> 16) & 0xff;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 ti8 = tcg_const_i32(i8);
+
+ switch (MASK_MSA_I8(ctx->opcode)) {
+ case OPC_ANDI_B:
+ gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_ORI_B:
+ gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_NORI_B:
+ gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_XORI_B:
+ gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_BMNZI_B:
+ gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_BMZI_B:
+ gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_BSELI_B:
+ gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
+ break;
+ case OPC_SHF_B:
+ case OPC_SHF_H:
+ case OPC_SHF_W:
+ {
+ uint8_t df = (ctx->opcode >> 24) & 0x3;
+ if (df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ } else {
+ TCGv_i32 tdf = tcg_const_i32(df);
+ gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
+ tcg_temp_free_i32(tdf);
+ }
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(ti8);
+}
+
+static void gen_msa_i5(DisasContext *ctx)
+{
+#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
+ uint8_t df = (ctx->opcode >> 21) & 0x3;
+ int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
+ uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 tdf = tcg_const_i32(df);
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 timm = tcg_temp_new_i32();
+ tcg_gen_movi_i32(timm, u5);
+
+ switch (MASK_MSA_I5(ctx->opcode)) {
+ case OPC_ADDVI_df:
+ gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_SUBVI_df:
+ gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_MAXI_S_df:
+ tcg_gen_movi_i32(timm, s5);
+ gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_MAXI_U_df:
+ gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_MINI_S_df:
+ tcg_gen_movi_i32(timm, s5);
+ gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_MINI_U_df:
+ gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_CEQI_df:
+ tcg_gen_movi_i32(timm, s5);
+ gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_CLTI_S_df:
+ tcg_gen_movi_i32(timm, s5);
+ gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_CLTI_U_df:
+ gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_CLEI_S_df:
+ tcg_gen_movi_i32(timm, s5);
+ gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_CLEI_U_df:
+ gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
+ break;
+ case OPC_LDI_df:
+ {
+ int32_t s10 = sextract32(ctx->opcode, 11, 10);
+ tcg_gen_movi_i32(timm, s10);
+ gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(tdf);
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(timm);
+}
+
+static void gen_msa_bit(DisasContext *ctx)
+{
+#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
+ uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
+ uint32_t df = 0, m = 0;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 tdf;
+ TCGv_i32 tm;
+ TCGv_i32 twd;
+ TCGv_i32 tws;
+
+ if ((dfm & 0x40) == 0x00) {
+ m = dfm & 0x3f;
+ df = DF_DOUBLE;
+ } else if ((dfm & 0x60) == 0x40) {
+ m = dfm & 0x1f;
+ df = DF_WORD;
+ } else if ((dfm & 0x70) == 0x60) {
+ m = dfm & 0x0f;
+ df = DF_HALF;
+ } else if ((dfm & 0x78) == 0x70) {
+ m = dfm & 0x7;
+ df = DF_BYTE;
+ } else {
+ gen_reserved_instruction(ctx);
+ return;
+ }
+
+ tdf = tcg_const_i32(df);
+ tm = tcg_const_i32(m);
+ twd = tcg_const_i32(wd);
+ tws = tcg_const_i32(ws);
+
+ switch (MASK_MSA_BIT(ctx->opcode)) {
+ case OPC_SLLI_df:
+ gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SRAI_df:
+ gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SRLI_df:
+ gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_BCLRI_df:
+ gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_BSETI_df:
+ gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_BNEGI_df:
+ gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_BINSLI_df:
+ gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_BINSRI_df:
+ gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SAT_S_df:
+ gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SAT_U_df:
+ gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SRARI_df:
+ gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ case OPC_SRLRI_df:
+ gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(tdf);
+ tcg_temp_free_i32(tm);
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+}
+
+static void gen_msa_3r(DisasContext *ctx)
+{
+#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
+ uint8_t df = (ctx->opcode >> 21) & 0x3;
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 tdf = tcg_const_i32(df);
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twt = tcg_const_i32(wt);
+
+ switch (MASK_MSA_3R(ctx->opcode)) {
+ case OPC_BINSL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BINSR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BCLR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BNEG_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BSET_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADD_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_AVE_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_AVE_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_AVER_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_AVER_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_CEQ_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_CLE_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_CLE_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_CLT_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_CLT_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DIV_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DIV_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MAX_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MAX_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MAX_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MOD_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MOD_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MADDV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MSUBV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ASUB_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ASUB_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVEV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVOD_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_PCKEV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_PCKOD_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SLL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRA_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRAR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRLR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SUBS_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MULV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SLD_df:
+ gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_VSHF_df:
+ gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_SUBV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SUBS_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SPLAT_df:
+ gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_SUBSUS_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SUBSUU_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+
+ case OPC_DOTP_S_df:
+ case OPC_DOTP_U_df:
+ case OPC_DPADD_S_df:
+ case OPC_DPADD_U_df:
+ case OPC_DPSUB_S_df:
+ case OPC_HADD_S_df:
+ case OPC_DPSUB_U_df:
+ case OPC_HADD_U_df:
+ case OPC_HSUB_S_df:
+ case OPC_HSUB_U_df:
+ if (df == DF_BYTE) {
+ gen_reserved_instruction(ctx);
+ break;
+ }
+ switch (MASK_MSA_3R(ctx->opcode)) {
+ case OPC_HADD_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_HADD_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_HSUB_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_HSUB_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DOTP_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DOTP_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DPADD_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DPADD_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DPSUB_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_DPSUB_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twt);
+ tcg_temp_free_i32(tdf);
+}
+
+static void gen_msa_elm_3e(DisasContext *ctx)
+{
+#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
+ uint8_t source = (ctx->opcode >> 11) & 0x1f;
+ uint8_t dest = (ctx->opcode >> 6) & 0x1f;
+ TCGv telm = tcg_temp_new();
+ TCGv_i32 tsr = tcg_const_i32(source);
+ TCGv_i32 tdt = tcg_const_i32(dest);
+
+ switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
+ case OPC_CTCMSA:
+ gen_load_gpr(telm, source);
+ gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
+ break;
+ case OPC_CFCMSA:
+ gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
+ gen_store_gpr(telm, dest);
+ break;
+ case OPC_MOVE_V:
+ gen_helper_msa_move_v(cpu_env, tdt, tsr);
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free(telm);
+ tcg_temp_free_i32(tdt);
+ tcg_temp_free_i32(tsr);
+}
+
+static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
+{
+#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tn = tcg_const_i32(n);
+ TCGv_i32 tdf = tcg_const_i32(df);
+
+ switch (MASK_MSA_ELM(ctx->opcode)) {
+ case OPC_SLDI_df:
+ gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
+ break;
+ case OPC_SPLATI_df:
+ gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
+ break;
+ case OPC_INSVE_df:
+ gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
+ break;
+ case OPC_COPY_S_df:
+ case OPC_COPY_U_df:
+ case OPC_INSERT_df:
+#if !defined(TARGET_MIPS64)
+ /* Double format valid only for MIPS64 */
+ if (df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ break;
+ }
+ if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
+ (df == DF_WORD)) {
+ gen_reserved_instruction(ctx);
+ break;
+ }
+#endif
+ switch (MASK_MSA_ELM(ctx->opcode)) {
+ case OPC_COPY_S_df:
+ if (likely(wd != 0)) {
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
+ }
+ break;
+ case OPC_COPY_U_df:
+ if (likely(wd != 0)) {
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_WORD:
+ gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
+ }
+ break;
+ case OPC_INSERT_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
+ break;
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ }
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(tn);
+ tcg_temp_free_i32(tdf);
+}
+
+static void gen_msa_elm(DisasContext *ctx)
+{
+ uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
+ uint32_t df = 0, n = 0;
+
+ if ((dfn & 0x30) == 0x00) {
+ n = dfn & 0x0f;
+ df = DF_BYTE;
+ } else if ((dfn & 0x38) == 0x20) {
+ n = dfn & 0x07;
+ df = DF_HALF;
+ } else if ((dfn & 0x3c) == 0x30) {
+ n = dfn & 0x03;
+ df = DF_WORD;
+ } else if ((dfn & 0x3e) == 0x38) {
+ n = dfn & 0x01;
+ df = DF_DOUBLE;
+ } else if (dfn == 0x3E) {
+ /* CTCMSA, CFCMSA, MOVE.V */
+ gen_msa_elm_3e(ctx);
+ return;
+ } else {
+ gen_reserved_instruction(ctx);
+ return;
+ }
+
+ gen_msa_elm_df(ctx, df, n);
+}
+
+static void gen_msa_3rf(DisasContext *ctx)
+{
+#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
+ uint8_t df = (ctx->opcode >> 21) & 0x1;
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twt = tcg_const_i32(wt);
+ TCGv_i32 tdf = tcg_temp_new_i32();
+
+ /* adjust df value for floating-point instruction */
+ tcg_gen_movi_i32(tdf, df + 2);
+
+ switch (MASK_MSA_3RF(ctx->opcode)) {
+ case OPC_FCAF_df:
+ gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FADD_df:
+ gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCUN_df:
+ gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSUB_df:
+ gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCOR_df:
+ gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCEQ_df:
+ gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMUL_df:
+ gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCUNE_df:
+ gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCUEQ_df:
+ gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FDIV_df:
+ gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCNE_df:
+ gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCLT_df:
+ gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMADD_df:
+ gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MUL_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCULT_df:
+ gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMSUB_df:
+ gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MADD_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCLE_df:
+ gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MSUB_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FCULE_df:
+ gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FEXP2_df:
+ gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSAF_df:
+ gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FEXDO_df:
+ gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSUN_df:
+ gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSOR_df:
+ gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSEQ_df:
+ gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FTQ_df:
+ gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSUNE_df:
+ gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSUEQ_df:
+ gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSNE_df:
+ gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSLT_df:
+ gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMIN_df:
+ gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MULR_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSULT_df:
+ gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMIN_A_df:
+ gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MADDR_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSLE_df:
+ gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMAX_df:
+ gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_MSUBR_Q_df:
+ tcg_gen_movi_i32(tdf, df + 1);
+ gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FSULE_df:
+ gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ case OPC_FMAX_A_df:
+ gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twt);
+ tcg_temp_free_i32(tdf);
+}
+
+static void gen_msa_2r(DisasContext *ctx)
+{
+#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
+ (op & (0x7 << 18)))
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ uint8_t df = (ctx->opcode >> 16) & 0x3;
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twt = tcg_const_i32(wt);
+ TCGv_i32 tdf = tcg_const_i32(df);
+
+ switch (MASK_MSA_2R(ctx->opcode)) {
+ case OPC_FILL_df:
+#if !defined(TARGET_MIPS64)
+ /* Double format valid only for MIPS64 */
+ if (df == DF_DOUBLE) {
+ gen_reserved_instruction(ctx);
+ break;
+ }
+#endif
+ gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
+ break;
+ case OPC_NLOC_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_nloc_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_nloc_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_nloc_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_nloc_d(cpu_env, twd, tws);
+ break;
+ }
+ break;
+ case OPC_NLZC_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_nlzc_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_nlzc_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_nlzc_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_nlzc_d(cpu_env, twd, tws);
+ break;
+ }
+ break;
+ case OPC_PCNT_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pcnt_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pcnt_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pcnt_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pcnt_d(cpu_env, twd, tws);
+ break;
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twt);
+ tcg_temp_free_i32(tdf);
+}
+
+static void gen_msa_2rf(DisasContext *ctx)
+{
+#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
+ (op & (0xf << 17)))
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ uint8_t df = (ctx->opcode >> 16) & 0x1;
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twt = tcg_const_i32(wt);
+ /* adjust df value for floating-point instruction */
+ TCGv_i32 tdf = tcg_const_i32(df + 2);
+
+ switch (MASK_MSA_2RF(ctx->opcode)) {
+ case OPC_FCLASS_df:
+ gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FTRUNC_S_df:
+ gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FTRUNC_U_df:
+ gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FSQRT_df:
+ gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FRSQRT_df:
+ gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FRCP_df:
+ gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FRINT_df:
+ gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FLOG2_df:
+ gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FEXUPL_df:
+ gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FEXUPR_df:
+ gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FFQL_df:
+ gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FFQR_df:
+ gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FTINT_S_df:
+ gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FTINT_U_df:
+ gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FFINT_S_df:
+ gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
+ break;
+ case OPC_FFINT_U_df:
+ gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twt);
+ tcg_temp_free_i32(tdf);
+}
+
+static void gen_msa_vec_v(DisasContext *ctx)
+{
+#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
+ uint8_t wt = (ctx->opcode >> 16) & 0x1f;
+ uint8_t ws = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 twt = tcg_const_i32(wt);
+
+ switch (MASK_MSA_VEC(ctx->opcode)) {
+ case OPC_AND_V:
+ gen_helper_msa_and_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_OR_V:
+ gen_helper_msa_or_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_NOR_V:
+ gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_XOR_V:
+ gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_BMNZ_V:
+ gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_BMZ_V:
+ gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
+ break;
+ case OPC_BSEL_V:
+ gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twt);
+}
+
+static void gen_msa_vec(DisasContext *ctx)
+{
+ switch (MASK_MSA_VEC(ctx->opcode)) {
+ case OPC_AND_V:
+ case OPC_OR_V:
+ case OPC_NOR_V:
+ case OPC_XOR_V:
+ case OPC_BMNZ_V:
+ case OPC_BMZ_V:
+ case OPC_BSEL_V:
+ gen_msa_vec_v(ctx);
+ break;
+ case OPC_MSA_2R:
+ gen_msa_2r(ctx);
+ break;
+ case OPC_MSA_2RF:
+ gen_msa_2rf(ctx);
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+}
+
+void gen_msa(DisasContext *ctx)
+{
+ uint32_t opcode = ctx->opcode;
+
+ check_msa_access(ctx);
+
+ switch (MASK_MSA_MINOR(opcode)) {
+ case OPC_MSA_I8_00:
+ case OPC_MSA_I8_01:
+ case OPC_MSA_I8_02:
+ gen_msa_i8(ctx);
+ break;
+ case OPC_MSA_I5_06:
+ case OPC_MSA_I5_07:
+ gen_msa_i5(ctx);
+ break;
+ case OPC_MSA_BIT_09:
+ case OPC_MSA_BIT_0A:
+ gen_msa_bit(ctx);
+ break;
+ case OPC_MSA_3R_0D:
+ case OPC_MSA_3R_0E:
+ case OPC_MSA_3R_0F:
+ case OPC_MSA_3R_10:
+ case OPC_MSA_3R_11:
+ case OPC_MSA_3R_12:
+ case OPC_MSA_3R_13:
+ case OPC_MSA_3R_14:
+ case OPC_MSA_3R_15:
+ gen_msa_3r(ctx);
+ break;
+ case OPC_MSA_ELM:
+ gen_msa_elm(ctx);
+ break;
+ case OPC_MSA_3RF_1A:
+ case OPC_MSA_3RF_1B:
+ case OPC_MSA_3RF_1C:
+ gen_msa_3rf(ctx);
+ break;
+ case OPC_MSA_VEC:
+ gen_msa_vec(ctx);
+ break;
+ case OPC_LD_B:
+ case OPC_LD_H:
+ case OPC_LD_W:
+ case OPC_LD_D:
+ case OPC_ST_B:
+ case OPC_ST_H:
+ case OPC_ST_W:
+ case OPC_ST_D:
+ {
+ int32_t s10 = sextract32(ctx->opcode, 16, 10);
+ uint8_t rs = (ctx->opcode >> 11) & 0x1f;
+ uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ uint8_t df = (ctx->opcode >> 0) & 0x3;
+
+ TCGv_i32 twd = tcg_const_i32(wd);
+ TCGv taddr = tcg_temp_new();
+ gen_base_offset_addr(ctx, taddr, rs, s10 << df);
+
+ switch (MASK_MSA_MINOR(opcode)) {
+ case OPC_LD_B:
+ gen_helper_msa_ld_b(cpu_env, twd, taddr);
+ break;
+ case OPC_LD_H:
+ gen_helper_msa_ld_h(cpu_env, twd, taddr);
+ break;
+ case OPC_LD_W:
+ gen_helper_msa_ld_w(cpu_env, twd, taddr);
+ break;
+ case OPC_LD_D:
+ gen_helper_msa_ld_d(cpu_env, twd, taddr);
+ break;
+ case OPC_ST_B:
+ gen_helper_msa_st_b(cpu_env, twd, taddr);
+ break;
+ case OPC_ST_H:
+ gen_helper_msa_st_h(cpu_env, twd, taddr);
+ break;
+ case OPC_ST_W:
+ gen_helper_msa_st_w(cpu_env, twd, taddr);
+ break;
+ case OPC_ST_D:
+ gen_helper_msa_st_d(cpu_env, twd, taddr);
+ break;
+ }
+
+ tcg_temp_free_i32(twd);
+ tcg_temp_free(taddr);
+ }
+ break;
+ default:
+ MIPS_INVAL("MSA instruction");
+ gen_reserved_instruction(ctx);
+ break;
+ }
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e1763e5bcec..01fe4609c9d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1133,240 +1133,6 @@ enum {
OPC_NMSUB_PS = 0x3E | OPC_CP3,
};
-/* MSA Opcodes */
-#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
- OPC_MSA_I8_00 = 0x00 | OPC_MSA,
- OPC_MSA_I8_01 = 0x01 | OPC_MSA,
- OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_I5_06 = 0x06 | OPC_MSA,
- OPC_MSA_I5_07 = 0x07 | OPC_MSA,
- OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
- OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
- OPC_MSA_3R_0D = 0x0D | OPC_MSA,
- OPC_MSA_3R_0E = 0x0E | OPC_MSA,
- OPC_MSA_3R_0F = 0x0F | OPC_MSA,
- OPC_MSA_3R_10 = 0x10 | OPC_MSA,
- OPC_MSA_3R_11 = 0x11 | OPC_MSA,
- OPC_MSA_3R_12 = 0x12 | OPC_MSA,
- OPC_MSA_3R_13 = 0x13 | OPC_MSA,
- OPC_MSA_3R_14 = 0x14 | OPC_MSA,
- OPC_MSA_3R_15 = 0x15 | OPC_MSA,
- OPC_MSA_ELM = 0x19 | OPC_MSA,
- OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
- OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
- OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
- OPC_MSA_VEC = 0x1E | OPC_MSA,
-
- /* MI10 instruction */
- OPC_LD_B = (0x20) | OPC_MSA,
- OPC_LD_H = (0x21) | OPC_MSA,
- OPC_LD_W = (0x22) | OPC_MSA,
- OPC_LD_D = (0x23) | OPC_MSA,
- OPC_ST_B = (0x24) | OPC_MSA,
- OPC_ST_H = (0x25) | OPC_MSA,
- OPC_ST_W = (0x26) | OPC_MSA,
- OPC_ST_D = (0x27) | OPC_MSA,
-};
-
-enum {
- /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
- OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
- OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
- OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
- OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
- OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
- OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
- OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
- OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
-
- /* I8 instruction */
- OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
- OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
- OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
- OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
- OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
- OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
- OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
-
- /* VEC/2R/2RF instruction */
- OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
- OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
- OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
- OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
- OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
- OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
- OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
-
- OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
- OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
-
- /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
- OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
- OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
- OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
- OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
-
- /* 2RF instruction df(bit 16) = _w, _d */
- OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
- OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
- OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
- OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
- OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
- OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
- OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
- OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
- OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
- OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
- OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
- OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
- OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
- OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
-
- /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
- OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
- OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
- OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
- OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
- OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
- OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
- OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
- OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
- OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
- OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
- OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
- OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
- OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
- OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
- OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
- OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
- OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
- OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
- OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
- OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
- OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
- OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
- OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
- OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
- OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
- OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
- OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
- OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
- OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
- OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
- OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
- OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
- OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
- OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
- OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
- OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
- OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
- OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
- OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
- OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
- OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
- OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
- OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
- OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
- OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
- OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
- OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
- OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
- OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
- OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
- OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
- OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
- OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
- OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
- OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
- OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
- OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
- OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
- OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
- OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
- OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
-
- /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
- OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-
- /* 3RF instruction _df(bit 21) = _w, _d */
- OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
- OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
- OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
- OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
- OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
- OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
- OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
- OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
- OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
- OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
- OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
- OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
- OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
- OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
- OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
- OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
- OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
- OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
- OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
- OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
- OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
- OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
- OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
- OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
- OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
- OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
- OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
- OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
- OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
- OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
- OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
- OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
- OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
- OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
- OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
- OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
- OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
- OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
- OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
- OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
- OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
-
- /* BIT instruction df(bits 22..16) = _B _H _W _D */
- OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
- OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
- OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
- OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
- OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
- OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
- OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
- OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
- OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
- OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
-};
-
-
/*
*
* AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
@@ -2424,7 +2190,6 @@ static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
TCGv_i32 fpu_fcr0, fpu_fcr31;
TCGv_i64 fpu_f64[32];
-static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
@@ -2506,25 +2271,6 @@ static const char * const fregnames[] = {
"f24", "f25", "f26", "f27", "f28",
"f29", "f30", "f31",
};
-static const char * const msaregnames[] = {
- "w0.d0", "w0.d1", "w1.d0", "w1.d1",
- "w2.d0", "w2.d1", "w3.d0", "w3.d1",
- "w4.d0", "w4.d1", "w5.d0", "w5.d1",
- "w6.d0", "w6.d1", "w7.d0", "w7.d1",
- "w8.d0", "w8.d1", "w9.d0", "w9.d1",
- "w10.d0", "w10.d1", "w11.d0", "w11.d1",
- "w12.d0", "w12.d1", "w13.d0", "w13.d1",
- "w14.d0", "w14.d1", "w15.d0", "w15.d1",
- "w16.d0", "w16.d1", "w17.d0", "w17.d1",
- "w18.d0", "w18.d1", "w19.d0", "w19.d1",
- "w20.d0", "w20.d1", "w21.d0", "w21.d1",
- "w22.d0", "w22.d1", "w23.d0", "w23.d1",
- "w24.d0", "w24.d1", "w25.d0", "w25.d1",
- "w26.d0", "w26.d1", "w27.d0", "w27.d1",
- "w28.d0", "w28.d1", "w29.d0", "w29.d1",
- "w30.d0", "w30.d1", "w31.d0", "w31.d1",
-};
-
#if !defined(TARGET_MIPS64)
static const char * const mxuregnames[] = {
"XR1", "XR2", "XR3", "XR4",
"XR5", "XR6", "XR7", "XR8",
@@ -28558,1983 +28304,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
}
}
-/* MIPS SIMD Architecture (MSA) */
-static inline int check_msa_access(DisasContext *ctx)
-{
- if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
- !(ctx->hflags & MIPS_HFLAG_F64))) {
- gen_reserved_instruction(ctx);
- return 0;
- }
-
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
- generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
- }
- return 1;
-}
-
-static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
-{
- /* generates tcg ops to check if any element is 0 */
- /* Note this function only works with MSA_WRLEN = 128 */
- uint64_t eval_zero_or_big = 0;
- uint64_t eval_big = 0;
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
- switch (df) {
- case DF_BYTE:
- eval_zero_or_big = 0x0101010101010101ULL;
- eval_big = 0x8080808080808080ULL;
- break;
- case DF_HALF:
- eval_zero_or_big = 0x0001000100010001ULL;
- eval_big = 0x8000800080008000ULL;
- break;
- case DF_WORD:
- eval_zero_or_big = 0x0000000100000001ULL;
- eval_big = 0x8000000080000000ULL;
- break;
- case DF_DOUBLE:
- eval_zero_or_big = 0x0000000000000001ULL;
- eval_big = 0x8000000000000000ULL;
- break;
- }
- tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
- tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
- tcg_gen_andi_i64(t0, t0, eval_big);
- tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big);
- tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]);
- tcg_gen_andi_i64(t1, t1, eval_big);
- tcg_gen_or_i64(t0, t0, t1);
- /* if all bits are zero then all elements are not zero */
- /* if some bit is non-zero then some element is zero */
- tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
- tcg_gen_trunc_i64_tl(tresult, t0);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
-{
- TCGv_i64 t0;
-
- check_msa_access(ctx);
-
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- gen_reserved_instruction(ctx);
- return true;
- }
- t0 = tcg_temp_new_i64();
- tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
- tcg_gen_setcondi_i64(cond, t0, t0, 0);
- tcg_gen_trunc_i64_tl(bcond, t0);
- tcg_temp_free_i64(t0);
-
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
-
- ctx->hflags |= MIPS_HFLAG_BC;
- ctx->hflags |= MIPS_HFLAG_BDS32;
-
- return true;
-}
-
-static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
-{
- check_msa_access(ctx);
-
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- gen_reserved_instruction(ctx);
- return true;
- }
-
- gen_check_zero_element(bcond, df, wt);
- if (if_not) {
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
- }
-
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
- ctx->hflags |= MIPS_HFLAG_BC;
- ctx->hflags |= MIPS_HFLAG_BDS32;
-
- return true;
-}
-
-void gen_msa_branch(DisasContext *ctx, uint32_t op1)
-{
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- int64_t s16 = (int16_t)ctx->opcode;
-
- switch (op1) {
- case OPC_BZ_V:
- case OPC_BNZ_V:
- gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE);
- break;
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, false);
- break;
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, true);
- break;
- }
-}
-
-static void gen_msa_i8(DisasContext *ctx)
-{
-#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
- uint8_t i8 = (ctx->opcode >> 16) & 0xff;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 ti8 = tcg_const_i32(i8);
-
- switch (MASK_MSA_I8(ctx->opcode)) {
- case OPC_ANDI_B:
- gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_ORI_B:
- gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_NORI_B:
- gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_XORI_B:
- gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMNZI_B:
- gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMZI_B:
- gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BSELI_B:
- gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_SHF_B:
- case OPC_SHF_H:
- case OPC_SHF_W:
- {
- uint8_t df = (ctx->opcode >> 24) & 0x3;
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- } else {
- TCGv_i32 tdf = tcg_const_i32(df);
- gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
- tcg_temp_free_i32(tdf);
- }
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(ti8);
-}
-
-static void gen_msa_i5(DisasContext *ctx)
-{
-#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
- uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tdf = tcg_const_i32(df);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 timm = tcg_temp_new_i32();
- tcg_gen_movi_i32(timm, u5);
-
- switch (MASK_MSA_I5(ctx->opcode)) {
- case OPC_ADDVI_df:
- gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_SUBVI_df:
- gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_U_df:
- gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_U_df:
- gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CEQI_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_U_df:
- gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_U_df:
- gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_LDI_df:
- {
- int32_t s10 = sextract32(ctx->opcode, 11, 10);
- tcg_gen_movi_i32(timm, s10);
- gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(timm);
-}
-
-static void gen_msa_bit(DisasContext *ctx)
-{
-#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
- uint32_t df = 0, m = 0;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tdf;
- TCGv_i32 tm;
- TCGv_i32 twd;
- TCGv_i32 tws;
-
- if ((dfm & 0x40) == 0x00) {
- m = dfm & 0x3f;
- df = DF_DOUBLE;
- } else if ((dfm & 0x60) == 0x40) {
- m = dfm & 0x1f;
- df = DF_WORD;
- } else if ((dfm & 0x70) == 0x60) {
- m = dfm & 0x0f;
- df = DF_HALF;
- } else if ((dfm & 0x78) == 0x70) {
- m = dfm & 0x7;
- df = DF_BYTE;
- } else {
- gen_reserved_instruction(ctx);
- return;
- }
-
- tdf = tcg_const_i32(df);
- tm = tcg_const_i32(m);
- twd = tcg_const_i32(wd);
- tws = tcg_const_i32(ws);
-
- switch (MASK_MSA_BIT(ctx->opcode)) {
- case OPC_SLLI_df:
- gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRAI_df:
- gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLI_df:
- gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BCLRI_df:
- gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BSETI_df:
- gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BNEGI_df:
- gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSLI_df:
- gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSRI_df:
- gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_S_df:
- gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_U_df:
- gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRARI_df:
- gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLRI_df:
- gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
- tcg_temp_free_i32(tm);
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
-}
-
-static void gen_msa_3r(DisasContext *ctx)
-{
-#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tdf = tcg_const_i32(df);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
-
- switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_BINSL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BINSR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BCLR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BNEG_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BSET_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADD_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ADDV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVE_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVE_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVER_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_AVER_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CEQ_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLE_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLE_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLT_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_CLT_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DIV_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DIV_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MAX_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_A_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MIN_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MOD_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MOD_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MADDV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MSUBV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ASUB_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ASUB_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVEV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVOD_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_ILVR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_PCKEV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_PCKOD_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SLL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRA_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRAR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SRLR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBS_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_MULV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SLD_df:
- gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_VSHF_df:
- gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_SUBV_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SPLAT_df:
- gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_SUBSUS_U_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_SUBSUU_S_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
-
- case OPC_DOTP_S_df:
- case OPC_DOTP_U_df:
- case OPC_DPADD_S_df:
- case OPC_DPADD_U_df:
- case OPC_DPSUB_S_df:
- case OPC_HADD_S_df:
- case OPC_DPSUB_U_df:
- case OPC_HADD_U_df:
- case OPC_HSUB_S_df:
- case OPC_HSUB_U_df:
- if (df == DF_BYTE) {
- gen_reserved_instruction(ctx);
- break;
- }
- switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_HADD_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HADD_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HSUB_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_HSUB_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DOTP_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DOTP_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPADD_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPADD_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPSUB_S_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_DPSUB_U_df:
- switch (df) {
- case DF_HALF:
- gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
- tcg_temp_free_i32(tdf);
-}
-
-static void gen_msa_elm_3e(DisasContext *ctx)
-{
-#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
- uint8_t source = (ctx->opcode >> 11) & 0x1f;
- uint8_t dest = (ctx->opcode >> 6) & 0x1f;
- TCGv telm = tcg_temp_new();
- TCGv_i32 tsr = tcg_const_i32(source);
- TCGv_i32 tdt = tcg_const_i32(dest);
-
- switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
- case OPC_CTCMSA:
- gen_load_gpr(telm, source);
- gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
- break;
- case OPC_CFCMSA:
- gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
- gen_store_gpr(telm, dest);
- break;
- case OPC_MOVE_V:
- gen_helper_msa_move_v(cpu_env, tdt, tsr);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free(telm);
- tcg_temp_free_i32(tdt);
- tcg_temp_free_i32(tsr);
-}
-
-static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
-{
-#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tn = tcg_const_i32(n);
- TCGv_i32 tdf = tcg_const_i32(df);
-
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_SLDI_df:
- gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_SPLATI_df:
- gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_INSVE_df:
- gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_COPY_S_df:
- case OPC_COPY_U_df:
- case OPC_INSERT_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
- if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
- (df == DF_WORD)) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_COPY_S_df:
- if (likely(wd != 0)) {
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- }
- break;
- case OPC_COPY_U_df:
- if (likely(wd != 0)) {
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_WORD:
- gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- }
- break;
- case OPC_INSERT_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- }
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(tn);
- tcg_temp_free_i32(tdf);
-}
-
-static void gen_msa_elm(DisasContext *ctx)
-{
- uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
- uint32_t df = 0, n = 0;
-
- if ((dfn & 0x30) == 0x00) {
- n = dfn & 0x0f;
- df = DF_BYTE;
- } else if ((dfn & 0x38) == 0x20) {
- n = dfn & 0x07;
- df = DF_HALF;
- } else if ((dfn & 0x3c) == 0x30) {
- n = dfn & 0x03;
- df = DF_WORD;
- } else if ((dfn & 0x3e) == 0x38) {
- n = dfn & 0x01;
- df = DF_DOUBLE;
- } else if (dfn == 0x3E) {
- /* CTCMSA, CFCMSA, MOVE.V */
- gen_msa_elm_3e(ctx);
- return;
- } else {
- gen_reserved_instruction(ctx);
- return;
- }
-
- gen_msa_elm_df(ctx, df, n);
-}
-
-static void gen_msa_3rf(DisasContext *ctx)
-{
-#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
- uint8_t df = (ctx->opcode >> 21) & 0x1;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
- TCGv_i32 tdf = tcg_temp_new_i32();
-
- /* adjust df value for floating-point instruction */
- tcg_gen_movi_i32(tdf, df + 2);
-
- switch (MASK_MSA_3RF(ctx->opcode)) {
- case OPC_FCAF_df:
- gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FADD_df:
- gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUN_df:
- gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUB_df:
- gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCOR_df:
- gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCEQ_df:
- gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMUL_df:
- gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUNE_df:
- gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCUEQ_df:
- gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FDIV_df:
- gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCNE_df:
- gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCLT_df:
- gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMADD_df:
- gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MUL_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCULT_df:
- gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMSUB_df:
- gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MADD_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCLE_df:
- gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MSUB_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FCULE_df:
- gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FEXP2_df:
- gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSAF_df:
- gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FEXDO_df:
- gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUN_df:
- gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSOR_df:
- gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSEQ_df:
- gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FTQ_df:
- gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUNE_df:
- gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSUEQ_df:
- gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSNE_df:
- gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSLT_df:
- gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMIN_df:
- gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MULR_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSULT_df:
- gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMIN_A_df:
- gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MADDR_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSLE_df:
- gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMAX_df:
- gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_MSUBR_Q_df:
- tcg_gen_movi_i32(tdf, df + 1);
- gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FSULE_df:
- gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_FMAX_A_df:
- gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
- tcg_temp_free_i32(tdf);
-}
-
-static void gen_msa_2r(DisasContext *ctx)
-{
-#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0x7 << 18)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x3;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
- TCGv_i32 tdf = tcg_const_i32(df);
-
- switch (MASK_MSA_2R(ctx->opcode)) {
- case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
- break;
- case OPC_NLOC_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_nloc_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_nloc_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_nloc_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_nloc_d(cpu_env, twd, tws);
- break;
- }
- break;
- case OPC_NLZC_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_nlzc_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_nlzc_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_nlzc_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_nlzc_d(cpu_env, twd, tws);
- break;
- }
- break;
- case OPC_PCNT_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_pcnt_b(cpu_env, twd, tws);
- break;
- case DF_HALF:
- gen_helper_msa_pcnt_h(cpu_env, twd, tws);
- break;
- case DF_WORD:
- gen_helper_msa_pcnt_w(cpu_env, twd, tws);
- break;
- case DF_DOUBLE:
- gen_helper_msa_pcnt_d(cpu_env, twd, tws);
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
- tcg_temp_free_i32(tdf);
-}
-
-static void gen_msa_2rf(DisasContext *ctx)
-{
-#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0xf << 17)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x1;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
- /* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_const_i32(df + 2);
-
- switch (MASK_MSA_2RF(ctx->opcode)) {
- case OPC_FCLASS_df:
- gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_S_df:
- gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_U_df:
- gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FSQRT_df:
- gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRSQRT_df:
- gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRCP_df:
- gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRINT_df:
- gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FLOG2_df:
- gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPL_df:
- gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPR_df:
- gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQL_df:
- gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQR_df:
- gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_S_df:
- gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_U_df:
- gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_S_df:
- gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_U_df:
- gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
- tcg_temp_free_i32(tdf);
-}
-
-static void gen_msa_vec_v(DisasContext *ctx)
-{
-#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
-
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- gen_helper_msa_and_v(cpu_env, twd, tws, twt);
- break;
- case OPC_OR_V:
- gen_helper_msa_or_v(cpu_env, twd, tws, twt);
- break;
- case OPC_NOR_V:
- gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_XOR_V:
- gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMNZ_V:
- gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BMZ_V:
- gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
- break;
- case OPC_BSEL_V:
- gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
-}
-
-static void gen_msa_vec(DisasContext *ctx)
-{
- switch (MASK_MSA_VEC(ctx->opcode)) {
- case OPC_AND_V:
- case OPC_OR_V:
- case OPC_NOR_V:
- case OPC_XOR_V:
- case OPC_BMNZ_V:
- case OPC_BMZ_V:
- case OPC_BSEL_V:
- gen_msa_vec_v(ctx);
- break;
- case OPC_MSA_2R:
- gen_msa_2r(ctx);
- break;
- case OPC_MSA_2RF:
- gen_msa_2rf(ctx);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-}
-
-void gen_msa(DisasContext *ctx)
-{
- uint32_t opcode = ctx->opcode;
-
- check_msa_access(ctx);
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_I8_00:
- case OPC_MSA_I8_01:
- case OPC_MSA_I8_02:
- gen_msa_i8(ctx);
- break;
- case OPC_MSA_I5_06:
- case OPC_MSA_I5_07:
- gen_msa_i5(ctx);
- break;
- case OPC_MSA_BIT_09:
- case OPC_MSA_BIT_0A:
- gen_msa_bit(ctx);
- break;
- case OPC_MSA_3R_0D:
- case OPC_MSA_3R_0E:
- case OPC_MSA_3R_0F:
- case OPC_MSA_3R_10:
- case OPC_MSA_3R_11:
- case OPC_MSA_3R_12:
- case OPC_MSA_3R_13:
- case OPC_MSA_3R_14:
- case OPC_MSA_3R_15:
- gen_msa_3r(ctx);
- break;
- case OPC_MSA_ELM:
- gen_msa_elm(ctx);
- break;
- case OPC_MSA_3RF_1A:
- case OPC_MSA_3RF_1B:
- case OPC_MSA_3RF_1C:
- gen_msa_3rf(ctx);
- break;
- case OPC_MSA_VEC:
- gen_msa_vec(ctx);
- break;
- case OPC_LD_B:
- case OPC_LD_H:
- case OPC_LD_W:
- case OPC_LD_D:
- case OPC_ST_B:
- case OPC_ST_H:
- case OPC_ST_W:
- case OPC_ST_D:
- {
- int32_t s10 = sextract32(ctx->opcode, 16, 10);
- uint8_t rs = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 0) & 0x3;
-
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv taddr = tcg_temp_new();
- gen_base_offset_addr(ctx, taddr, rs, s10 << df);
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_LD_B:
- gen_helper_msa_ld_b(cpu_env, twd, taddr);
- break;
- case OPC_LD_H:
- gen_helper_msa_ld_h(cpu_env, twd, taddr);
- break;
- case OPC_LD_W:
- gen_helper_msa_ld_w(cpu_env, twd, taddr);
- break;
- case OPC_LD_D:
- gen_helper_msa_ld_d(cpu_env, twd, taddr);
- break;
- case OPC_ST_B:
- gen_helper_msa_st_b(cpu_env, twd, taddr);
- break;
- case OPC_ST_H:
- gen_helper_msa_st_h(cpu_env, twd, taddr);
- break;
- case OPC_ST_W:
- gen_helper_msa_st_w(cpu_env, twd, taddr);
- break;
- case OPC_ST_D:
- gen_helper_msa_st_d(cpu_env, twd, taddr);
- break;
- }
-
- tcg_temp_free_i32(twd);
- tcg_temp_free(taddr);
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
-}
-
static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
@@ -31577,24 +29346,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-void msa_translate_init(void)
-{
- int i;
-
- for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
-
- /*
- * The MSA vector registers are mapped on the
- * scalar floating-point unit (FPU) registers.
- */
- msa_wr_d[i * 2] = fpu_f64[i];
- off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
- msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
- }
-}
-
void mips_tcg_init(void)
{
int i;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 596eb1aeeb3..2aa4d81300b 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -8,6 +8,7 @@
'fpu_helper.c',
'lmmi_helper.c',
'msa_helper.c',
+ 'msa_translate.c',
'op_helper.c',
'tlb_helper.c',
'translate.c',
--
2.26.2
4:22 p.m.
New subject: [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson(a)linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-25-f4bug(a)amsat.org>
---
target/mips/msa_translate.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index a4f9a6c1285..52bd428759a 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -304,7 +304,8 @@ static inline int check_msa_access(DisasContext *ctx)
return 1;
}
-static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
+static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
+ TCGCond cond)
{
/* generates tcg ops to check if any element is 0 */
/* Note this function only works with MSA_WRLEN = 128 */
@@ -339,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t
wt)
tcg_gen_or_i64(t0, t0, t1);
/* if all bits are zero then all elements are not zero */
/* if some bit is non-zero then some element is zero */
- tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(tresult, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
@@ -378,10 +379,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16,
bool if_not)
return true;
}
- gen_check_zero_element(bcond, df, wt);
- if (if_not) {
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
- }
+ gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
--
2.26.2
4:22 p.m.
New subject: [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-20-f4bug(a)amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/translate.h | 3 +++
target/mips/msa32.decode | 24 ++++++++++++++++++++++++
target/mips/msa_translate.c | 36 ++++++++++++++++++++++++++++++++++++
target/mips/meson.build | 5 +++++
4 files changed, 68 insertions(+)
create mode 100644 target/mips/msa32.decode
diff --git a/target/mips/translate.h b/target/mips/translate.h
index c61c11978c2..858e47cf833 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -167,4 +167,7 @@ void msa_translate_init(void);
void gen_msa(DisasContext *ctx);
void gen_msa_branch(DisasContext *ctx, uint32_t op1);
+/* decodetree generated */
+bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
+
#endif
diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode
new file mode 100644
index 00000000000..d69675132b8
--- /dev/null
+++ b/target/mips/msa32.decode
@@ -0,0 +1,24 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS32 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00866-2B-MSA32-AFP-01.12)
+#
+
+&msa_bz df wt s16
+
+@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
+@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+
+BZ_V 010001 01011 ..... ................ @bz
+BNZ_V 010001 01111 ..... ................ @bz
+
+BZ_x 010001 110 .. ..... ................ @bz_df
+BNZ_x 010001 111 .. ..... ................ @bz_df
+
+MSA 011110 --------------------------
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 52bd428759a..5efb0a1fc8a 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
@@ -16,6 +17,9 @@
#include "fpu_helper.h"
#include "internal.h"
+/* Include the auto-generated decoder. */
+#include "decode-msa32.c.inc"
+
#define OPC_MSA (0x1E << 26)
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
@@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond
cond)
return true;
}
+static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+}
+
+static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+}
+
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
{
check_msa_access(ctx);
@@ -388,6 +402,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16,
bool if_not)
return true;
}
+static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+}
+
+static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+}
+
void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -2261,3 +2285,15 @@ void gen_msa(DisasContext *ctx)
break;
}
}
+
+static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
+{
+ gen_msa(ctx);
+
+ return true;
+}
+
+bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
+{
+ return decode_msa32(ctx, insn);
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 2aa4d81300b..e6285abd044 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,9 @@
+gen = [
+ decodetree.process('msa32.decode', extra_args: [
'--static-decode=decode_msa32' ]),
+]
+
mips_ss = ss.source_set()
+mips_ss.add(gen)
mips_ss.add(files(
'cpu.c',
'gdbstub.c',
--
2.26.2
4:22 p.m.
New subject: [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-21-f4bug(a)amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com>
---
target/mips/translate.h | 12 ------------
target/mips/msa_translate.c | 29 +----------------------------
target/mips/translate.c | 32 ++++++++++----------------------
3 files changed, 11 insertions(+), 62 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 858e47cf833..35e9c4cd135 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -82,8 +82,6 @@ enum {
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
@@ -93,14 +91,6 @@ enum {
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
};
#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
@@ -164,8 +154,6 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
-void gen_msa(DisasContext *ctx);
-void gen_msa_branch(DisasContext *ctx, uint32_t op1);
/* decodetree generated */
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 5efb0a1fc8a..8a48f889aa2 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -412,33 +412,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
}
-void gen_msa_branch(DisasContext *ctx, uint32_t op1)
-{
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- int64_t s16 = (int16_t)ctx->opcode;
-
- switch (op1) {
- case OPC_BZ_V:
- case OPC_BNZ_V:
- gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE);
- break;
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, false);
- break;
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, true);
- break;
- }
-}
-
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
@@ -2188,7 +2161,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-void gen_msa(DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 01fe4609c9d..3da12e31351 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -135,8 +136,6 @@ enum {
OPC_JIALC = (0x3E << 26),
/* MDMX ASE specific */
OPC_MDMX = (0x1E << 26),
- /* MSA ASE, same as MDMX */
- OPC_MSA = OPC_MDMX,
/* Cache and prefetch */
OPC_CACHE = (0x2F << 26),
OPC_PREF = (0x33 << 26),
@@ -28828,21 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
}
break;
}
- case OPC_BZ_V:
- case OPC_BNZ_V:
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- if (ase_msa_available(env)) {
- gen_msa_branch(ctx, op1);
- break;
- }
- /* fall through */
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@@ -29024,16 +29008,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MSA: /* OPC_MDMX */
+ case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+ gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
- if (ase_msa_available(env)) {
- gen_msa(ctx);
- }
}
break;
case OPC_PCREL:
@@ -29066,6 +29047,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_set_label(l1);
}
+ /* Transition to the auto-generated decoder. */
+
+ /* ISA extensions */
+ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
+ return;
+ }
+
if (!decode_opc_legacy(env, ctx)) {
gen_reserved_instruction(ctx);
}
--
2.26.2
4:22 p.m.
New subject: [PULL 54/66] target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-22-f4bug(a)amsat.org>
---
target/mips/translate.h | 6 +++
target/mips/translate.c | 35 ++---------------
target/mips/translate_addr_const.c | 61 ++++++++++++++++++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 72 insertions(+), 31 deletions(-)
create mode 100644 target/mips/translate_addr_const.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 35e9c4cd135..50281c93369 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -129,6 +129,12 @@ void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
+/*
+ * Address Computation and Large Constant Instructions
+ */
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa);
+
extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3da12e31351..e9730d95131 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6616,31 +6616,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int
rd)
tcg_temp_free(t0);
}
-static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int imm2)
-{
- TCGv t0;
- TCGv t1;
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, imm2 + 1);
- tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
- if (opc == OPC_LSA) {
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- }
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
- return;
-}
-
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
int rt, int bits)
{
@@ -16496,8 +16471,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext
*ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);
@@ -21460,8 +21434,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2) - 1);
+ gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
@@ -24347,7 +24320,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_LSA:
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case OPC_MULT:
case OPC_MULTU:
@@ -24401,7 +24374,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
#if defined(TARGET_MIPS64)
case OPC_DLSA:
check_mips_64(ctx);
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_DLSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_addr_const.c
new file mode 100644
index 00000000000..1c6f61c3dd2
--- /dev/null
+++ b/target/mips/translate_addr_const.c
@@ -0,0 +1,61 @@
+/*
+ * Address Computation and Large Constant Instructions
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
+ * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "translate.h"
+
+bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ check_mips_64(ctx);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index e6285abd044..9afee0ca955 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -17,6 +17,7 @@
'op_helper.c',
'tlb_helper.c',
'translate.c',
+ 'translate_addr_const.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
4:22 p.m.
New subject: [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-23-f4bug(a)amsat.org>
---
target/mips/msa32.decode | 4 ++++
target/mips/msa64.decode | 17 +++++++++++++++++
target/mips/msa_translate.c | 14 ++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 36 insertions(+)
create mode 100644 target/mips/msa64.decode
diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode
index d69675132b8..0b2f0863251 100644
--- a/target/mips/msa32.decode
+++ b/target/mips/msa32.decode
@@ -10,11 +10,15 @@
# (Document Number: MD00866-2B-MSA32-AFP-01.12)
#
+&lsa rd rt rs sa
&msa_bz df wt s16
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
diff --git a/target/mips/msa64.decode b/target/mips/msa64.decode
new file mode 100644
index 00000000000..8dcbbcd8538
--- /dev/null
+++ b/target/mips/msa64.decode
@@ -0,0 +1,17 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS64 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00868-1D-MSA64-AFP-01.12)
+#
+
+&lsa rd rt rs sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 8a48f889aa2..e97370e54c2 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -19,6 +19,7 @@
/* Include the auto-generated decoder. */
#include "decode-msa32.c.inc"
+#include "decode-msa64.c.inc"
#define OPC_MSA (0x1E << 26)
@@ -2266,7 +2267,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
{
+ if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) {
+ return true;
+ }
return decode_msa32(ctx, insn);
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9afee0ca955..21b75254047 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,5 +1,6 @@
gen = [
decodetree.process('msa32.decode', extra_args: [
'--static-decode=decode_msa32' ]),
+ decodetree.process('msa64.decode', extra_args: [
'--static-decode=decode_msa64' ]),
]
mips_ss = ss.source_set()
--
2.26.2
4:22 p.m.
New subject: [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201215225757.764263-24-f4bug(a)amsat.org>
---
target/mips/translate.h | 1 +
target/mips/mips32r6.decode | 17 +++++++++++++++++
target/mips/mips64r6.decode | 17 +++++++++++++++++
target/mips/rel6_translate.c | 37 ++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 5 +++++
target/mips/meson.build | 3 +++
6 files changed, 80 insertions(+)
create mode 100644 target/mips/mips32r6.decode
create mode 100644 target/mips/mips64r6.decode
create mode 100644 target/mips/rel6_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 50281c93369..11730f5b2e6 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -162,6 +162,7 @@ extern TCGv bcond;
void msa_translate_init(void);
/* decodetree generated */
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
new file mode 100644
index 00000000000..027585ee042
--- /dev/null
+++ b/target/mips/mips32r6.decode
@@ -0,0 +1,17 @@
+# MIPS32 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS32 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
+#
+
+&lsa rd rt rs sa
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
new file mode 100644
index 00000000000..e812224341e
--- /dev/null
+++ b/target/mips/mips64r6.decode
@@ -0,0 +1,17 @@
+# MIPS64 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
+#
+
+&lsa rd rt rs sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
new file mode 100644
index 00000000000..631d0b87748
--- /dev/null
+++ b/target/mips/rel6_translate.c
@@ -0,0 +1,37 @@
+/*
+ * MIPS emulation for QEMU - # Release 6 translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-mips32r6.c.inc"
+#include "decode-mips64r6.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
+{
+ if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
+ return true;
+ }
+ return decode_mips32r6(ctx, insn);
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e9730d95131..cd34b06faae 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29027,6 +29027,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
return;
}
+ /* ISA (from latest to oldest) */
+ if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx,
ctx->opcode)) {
+ return;
+ }
+
if (!decode_opc_legacy(env, ctx)) {
gen_reserved_instruction(ctx);
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 21b75254047..ab01123013a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,6 @@
gen = [
+ decodetree.process('mips32r6.decode', extra_args: [
'--static-decode=decode_mips32r6' ]),
+ decodetree.process('mips64r6.decode', extra_args: [
'--static-decode=decode_mips64r6' ]),
decodetree.process('msa32.decode', extra_args: [
'--static-decode=decode_msa32' ]),
decodetree.process('msa64.decode', extra_args: [
'--static-decode=decode_msa64' ]),
]
@@ -16,6 +18,7 @@
'msa_helper.c',
'msa_translate.c',
'op_helper.c',
+ 'rel6_translate.c',
'tlb_helper.c',
'translate.c',
'translate_addr_const.c',
--
2.26.2
4:22 p.m.
New subject: [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-6-f4bug(a)amsat.org>
---
target/mips/translate.c | 29 +++++------------------------
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cd34b06faae..f4481afb8de 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -280,9 +280,6 @@ enum {
R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
-
- OPC_LSA = 0x05 | OPC_SPECIAL,
- OPC_DLSA = 0x15 | OPC_SPECIAL,
};
/* Multiplication variants of the vr54xx. */
@@ -24319,9 +24316,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
- case OPC_LSA:
- gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
- break;
case OPC_MULT:
case OPC_MULTU:
case OPC_DIV:
@@ -24372,10 +24366,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext
*ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DLSA:
- check_mips_64(ctx);
- gen_DLSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
- break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
if (rt == 0 && sa == 1) {
@@ -24637,18 +24627,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1);
break;
- case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- } else {
- /* Pmon entry point, also R4010 selsl */
+ case OPC_PMON:
+ /* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
- MIPS_INVAL("PMON / selsl");
- gen_reserved_instruction(ctx);
+ MIPS_INVAL("PMON / selsl");
+ gen_reserved_instruction(ctx);
#else
- gen_helper_0e0i(pmon, sa);
+ gen_helper_0e0i(pmon, sa);
#endif
- }
break;
case OPC_SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL);
@@ -24739,11 +24725,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext
*ctx)
break;
}
break;
- case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- }
- break;
#endif
default:
if (ctx->insn_flags & ISA_MIPS_R6) {
--
2.26.2
4:22 p.m.
New subject: [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-7-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 2 ++
target/mips/rel6_translate.c | 7 +++++++
target/mips/translate.c | 2 --
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index 027585ee042..259bac612ab 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -15,3 +15,5 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
+REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
index 631d0b87748..51264f0ce92 100644
--- a/target/mips/rel6_translate.c
+++ b/target/mips/rel6_translate.c
@@ -18,6 +18,13 @@
#include "decode-mips32r6.c.inc"
#include "decode-mips64r6.c.inc"
+bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
+{
+ gen_reserved_instruction(ctx);
+
+ return true;
+}
+
static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
{
return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f4481afb8de..01c1ee546e2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27137,8 +27137,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env,
DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
-
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
--
2.26.2
4:22 p.m.
New subject: [PULL 59/66] target/mips: Convert Rel6 COP1X opcode to decodetree
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-8-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 2 ++
target/mips/translate.c | 1 -
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index 259bac612ab..7b12a1bff25 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -16,4 +16,6 @@
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
+
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 01c1ee546e2..52397bce84b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28827,7 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_CP3:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
--
2.26.2
4:22 p.m.
New subject: [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-9-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 3 +++
target/mips/translate.c | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index 7b12a1bff25..e3b3934539a 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -19,3 +19,6 @@ LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+
+REMOVED 101111 ----- ----- ---------------- # CACHE
+REMOVED 110011 ----- ----- ---------------- # PREF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 52397bce84b..e8389738c57 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28620,7 +28620,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case OPC_CACHE:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
@@ -28629,7 +28628,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
/* Treat as NOP. */
break;
case OPC_PREF:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
--
2.26.2
4:22 p.m.
New subject: [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-10-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 5 +++++
target/mips/translate.c | 5 +----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index e3b3934539a..89a0085fafd 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -20,5 +20,10 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X
(COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 100010 ----- ----- ---------------- # LWL
+REMOVED 100110 ----- ----- ---------------- # LWR
+REMOVED 101010 ----- ----- ---------------- # SWL
+REMOVED 101110 ----- ----- ---------------- # SWR
+
REMOVED 101111 ----- ----- ---------------- # CACHE
REMOVED 110011 ----- ----- ---------------- # PREF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e8389738c57..0d729293f6b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28589,11 +28589,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* Fallthrough */
case OPC_LB:
case OPC_LH:
case OPC_LW:
@@ -28604,8 +28603,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SWL:
case OPC_SWR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_SB:
case OPC_SH:
case OPC_SW:
--
2.26.2
4:22 p.m.
New subject: [PULL 62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-11-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 5 +++++
target/mips/translate.c | 4 ----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index 89a0085fafd..3ec50704cf2 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -20,6 +20,11 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X
(COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
+REMOVED 011111 ----- ----- ---------- 011001 # LWLE
+REMOVED 011111 ----- ----- ---------- 011010 # LWRE
+REMOVED 011111 ----- ----- ---------- 100001 # SWLE
+REMOVED 011111 ----- ----- ---------- 100010 # SWRE
+
REMOVED 100010 ----- ----- ---------------- # LWL
REMOVED 100110 ----- ----- ---------------- # LWR
REMOVED 101010 ----- ----- ---------------- # SWL
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0d729293f6b..73efbd24585 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28122,8 +28122,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
switch (op1) {
case OPC_LWLE:
case OPC_LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_LBUE:
case OPC_LHUE:
case OPC_LBE:
@@ -28135,8 +28133,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext
*ctx)
return;
case OPC_SWLE:
case OPC_SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_SBE:
case OPC_SHE:
case OPC_SWE:
--
2.26.2
4:22 p.m.
New subject: [PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-12-f4bug(a)amsat.org>
---
target/mips/mips64r6.decode | 6 ++++++
target/mips/translate.c | 5 +----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
index e812224341e..8c3fc5dae9c 100644
--- a/target/mips/mips64r6.decode
+++ b/target/mips/mips64r6.decode
@@ -10,8 +10,14 @@
# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
#
+&REMOVED !extern
&lsa rd rt rs sa !extern
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
+
+REMOVED 011010 ----- ----- ---------------- # LDL
+REMOVED 011011 ----- ----- ---------------- # LDR
+REMOVED 101100 ----- ----- ---------------- # SDL
+REMOVED 101101 ----- ----- ---------------- # SDR
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 73efbd24585..f46d7c5f80b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28871,11 +28871,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LDL:
case OPC_LDR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_LWU:
case OPC_LD:
check_insn(ctx, ISA_MIPS3);
@@ -28884,8 +28883,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SDL:
case OPC_SDR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
--
2.26.2
4:22 p.m.
New subject: [PULL 64/66] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-13-f4bug(a)amsat.org>
---
target/mips/mips64r6.decode | 3 +++
target/mips/translate.c | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
index 8c3fc5dae9c..609b8958d25 100644
--- a/target/mips/mips64r6.decode
+++ b/target/mips/mips64r6.decode
@@ -21,3 +21,6 @@ REMOVED 011010 ----- ----- ---------------- # LDL
REMOVED 011011 ----- ----- ---------------- # LDR
REMOVED 101100 ----- ----- ---------------- # SDL
REMOVED 101101 ----- ----- ---------------- # SDR
+
+REMOVED 110100 ----- ----- ---------------- # LLD
+REMOVED 111100 ----- ----- ---------------- # SCD
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f46d7c5f80b..9f717aab287 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28871,7 +28871,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LDL:
case OPC_LDR:
@@ -28889,7 +28888,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SCD:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_insn(ctx, ISA_MIPS3);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
--
2.26.2
4:22 p.m.
New subject: [PULL 65/66] target/mips: Convert Rel6 LL/SC opcodes to decodetree
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Richard Henderson <richard.henderson(a)linaro.org>
Message-Id: <20201208203704.243704-14-f4bug(a)amsat.org>
---
target/mips/mips32r6.decode | 2 ++
target/mips/translate.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index 3ec50704cf2..489c20aa4e9 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -31,4 +31,6 @@ REMOVED 101010 ----- ----- ---------------- # SWL
REMOVED 101110 ----- ----- ---------------- # SWR
REMOVED 101111 ----- ----- ---------------- # CACHE
+REMOVED 110000 ----- ----- ---------------- # LL
REMOVED 110011 ----- ----- ---------------- # PREF
+REMOVED 111000 ----- ----- ---------------- # SC
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9f717aab287..b5b7706a7c2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28585,7 +28585,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@@ -28606,7 +28605,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
--
2.26.2
4:22 p.m.
New subject: [PULL 66/66] docs/system: Remove deprecated 'fulong2e' machine alias
The 'fulong2e' machine alias has been marked as deprecated since
QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
Time to remove it now.
Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Huacai Chen <chenhuacai(a)kernel.org>
Reviewed-by: Thomas Huth <huth(a)tuxfamily.org>
Message-Id: <20210106184602.3771551-1-f4bug(a)amsat.org>
---
docs/system/deprecated.rst | 5 -----
docs/system/removed-features.rst | 5 +++++
hw/mips/fuloong2e.c | 1 -
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index bacd76d7a58..e20bfcb17a4 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -309,11 +309,6 @@ The 'scsi-disk' device is deprecated. Users should use
'scsi-hd' or
System emulator machines
------------------------
-mips ``fulong2e`` machine (since 5.1)
-'''''''''''''''''''''''''''''''''''''
-
-This machine has been renamed ``fuloong2e``.
-
``pc-1.0``, ``pc-1.1``, ``pc-1.2`` and ``pc-1.3`` (since 5.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst
index 8b20d78a4d0..430fc33ca18 100644
--- a/docs/system/removed-features.rst
+++ b/docs/system/removed-features.rst
@@ -120,6 +120,11 @@ mips ``r4k`` platform (removed in 5.2)
This machine type was very old and unmaintained. Users should use the ``malta``
machine type instead.
+mips ``fulong2e`` machine alias (removed in 6.0)
+''''''''''''''''''''''''''''''''''''''''''''''''
+
+This machine has been renamed ``fuloong2e``.
+
Related binaries
----------------
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 29805242caa..bac2adbd5ae 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -383,7 +383,6 @@ static void mips_fuloong2e_init(MachineState *machine)
static void mips_fuloong2e_machine_init(MachineClass *mc)
{
mc->desc = "Fuloong 2e mini pc";
- mc->alias = "fulong2e"; /* Incorrect name used up to QEMU
4.2 */
mc->init = mips_fuloong2e_init;
mc->block_default_type = IF_IDE;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");
--
2.26.2
4:34 p.m.
On 1/7/21 11:21 PM, Philippe Mathieu-Daudé wrote:
The following changes since commit
470dd6bd360782f5137f7e3376af6a44658eb1d3:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' into
staging (2021-01-06 22:18:36 +0000)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210107
for you to fetch changes up to f97d339d612b86d8d336a11f01719a10893d6707:
docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-07 22:57:49
+0100)
----------------------------------------------------------------
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
----------------------------------------------------------------
I forgot to mention there is a checkpatch.pl error with
patch 23 ("Move common helpers from helper.c to cpu.c")
due to code movement:
ERROR: space prohibited after that '&' (ctx:WxW)
#52: FILE: target/mips/cpu.c:53:
+ cu = (v >> CP0St_CU0) & 0xf;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#53: FILE: target/mips/cpu.c:54:
+ mx = (v >> CP0St_MX) & 0x1;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#54: FILE: target/mips/cpu.c:55:
+ ksu = (v >> CP0St_KSU) & 0x3;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#81: FILE: target/mips/cpu.c:82:
+ uint32_t ksux = (1 << CP0St_KX) & val;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#89: FILE: target/mips/cpu.c:90:
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#116: FILE: target/mips/cpu.c:117:
+ mask &= ~((1 << CP0Ca_WP) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#121: FILE: target/mips/cpu.c:122:
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#131: FILE: target/mips/cpu.c:132:
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
^
total: 8 errors, 0 warnings, 433 lines checked
4:52 p.m.
Patchew URL: https://patchew.org/QEMU/20210107222253.20382-1-f4bug@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210107222253.20382-1-f4bug(a)amsat.org
Subject: [PULL 00/66] MIPS patches for 2021-01-07
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
* [new tag]
patchew/20210107222253.20382-1-f4bug(a)amsat.org ->
patchew/20210107222253.20382-1-f4bug(a)amsat.org
Switched to a new branch 'test'
dd377f9 docs/system: Remove deprecated 'fulong2e' machine alias
46b7515 target/mips: Convert Rel6 LL/SC opcodes to decodetree
30b29c5 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
a3a47cc target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
d31fb71 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
4ef5b18 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
218216b target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
ce5072b target/mips: Convert Rel6 COP1X opcode to decodetree
1ac8160 target/mips: Convert Rel6 Special2 opcode to decodetree
02dbc3d target/mips: Remove now unreachable LSA/DLSA opcodes code
36d8c0e target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
b862386 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
992d01e target/mips: Extract LSA/DLSA translation generators
aa36e31 target/mips: Use decode_ase_msa() generated from decodetree
779aa4f target/mips: Introduce decode tree bindings for MSA ASE
e0b0e2b target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
e844e9c target/mips: Extract MSA translation routines
574002a target/mips: Declare gen_msa/_branch() in 'translate.h'
e2ebaf4 target/mips: Extract MSA helper definitions
5c3ca1b target/mips: Extract MSA helpers from op_helper.c
ff8dd85 target/mips: Move msa_reset() to msa_helper.c
187fc34 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
f6e81a3 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
5717a13 target/mips: Extract msa_translate_init() from mips_tcg_init()
b41e6f5 target/mips: Alias MSA vector registers on FPU scalar registers
5dca6da target/mips: Remove now unused ASE_MSA definition
279cca1 target/mips: Simplify MSA TCG logic
9be6e1d target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
dd2ba3a target/mips: Simplify msa_reset()
a6f9803 target/mips: Introduce ase_msa_available() helper
154d914 target/mips/translate: Expose check_mips_64() to 32-bit mode
4ad62c0 target/mips/translate: Extract decode_opc_legacy() from decode_opc()
ae2962d target/mips: Only build TCG code when CONFIG_TCG is set
bf286b1 target/mips: Extract FPU specific definitions to translate.h
d664570 target/mips: Declare generic FPU functions in 'translate.h'
7d45714 target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
4a7f56f target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
734af7c target/mips/translate: Add declarations for generic code
7dbaf2f target/mips/translate: Extract DisasContext structure
e31d0fb target/mips: Rename translate_init.c as cpu-defs.c
01c87b9 target/mips: Move mmu_init() functions to tlb_helper.c
bf9cbc3 target/mips: Fix code style for checkpatch.pl
597531a target/mips: Rename helper.c as tlb_helper.c
d1c9757 target/mips: Move common helpers from helper.c to cpu.c
514bb31 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
0a0492f target/mips: Add !CONFIG_USER_ONLY comment after #endif
304a3f9 target/mips: Extract FPU helpers to 'fpu_helper.h'
8967642 target/mips: Inline cpu_state_reset() in mips_cpu_reset()
fd2629f target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
68cef79 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
61f4a6e target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
befb8ce target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
cf55264 target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
6800c8b target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
64d02b6 target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
1917e3e target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
3440107 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
b88e862 target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
d34977c hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
43146ba target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
9be76d4 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
58b6d94 target/mips/mips-defs: Reorder CPU_MIPS5 definition
b57df71 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
aa10029 target/mips/addr: Add translation helpers for KSEG1
e8a10b7 target/mips: Replace CP0_Config0 magic values by proper definitions
e4db93c target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
=== OUTPUT BEGIN ===
1/66 Checking commit e4db93c23d92 (target/mips: Add CP0 Config0 register definitions for
MIPS3 ISA)
2/66 Checking commit e8a10b733538 (target/mips: Replace CP0_Config0 magic values by proper
definitions)
3/66 Checking commit aa1002921075 (target/mips/addr: Add translation helpers for KSEG1)
4/66 Checking commit b57df718455b (target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS
comment)
5/66 Checking commit 58b6d941ecc4 (target/mips/mips-defs: Reorder CPU_MIPS5 definition)
6/66 Checking commit 9be76d48e0fe (target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as
CPU_MIPSxxR1)
7/66 Checking commit 43146bacae19 (target/mips/mips-defs: Introduce CPU_MIPS64 and
cpu_type_is_64bit())
8/66 Checking commit d34977c07407 (hw/mips/boston: Check 64-bit support with
cpu_type_is_64bit())
9/66 Checking commit b88e8622d21f (target/mips/mips-defs: Use ISA_MIPS32 definition to
check Release 1)
10/66 Checking commit 3440107bbb6f (target/mips/mips-defs: Use ISA_MIPS32R2 definition to
check Release 2)
11/66 Checking commit 1917e3ef23d8 (target/mips/mips-defs: Use ISA_MIPS32R3 definition to
check Release 3)
12/66 Checking commit 64d02b692008 (target/mips/mips-defs: Use ISA_MIPS32R5 definition to
check Release 5)
13/66 Checking commit 6800c8b5c12e (target/mips/mips-defs: Use ISA_MIPS32R6 definition to
check Release 6)
14/66 Checking commit cf552649ce52 (target/mips/mips-defs: Rename ISA_MIPS32 as
ISA_MIPS_R1)
15/66 Checking commit befb8ceccf7f (target/mips/mips-defs: Rename ISA_MIPS32R2 as
ISA_MIPS_R2)
16/66 Checking commit 61f4a6e201e4 (target/mips/mips-defs: Rename ISA_MIPS32R3 as
ISA_MIPS_R3)
17/66 Checking commit 68cef795e767 (target/mips/mips-defs: Rename ISA_MIPS32R5 as
ISA_MIPS_R5)
18/66 Checking commit fd2629f0f0d4 (target/mips/mips-defs: Rename ISA_MIPS32R6 as
ISA_MIPS_R6)
19/66 Checking commit 89676429d275 (target/mips: Inline cpu_state_reset() in
mips_cpu_reset())
20/66 Checking commit 304a3f9d18a1 (target/mips: Extract FPU helpers to
'fpu_helper.h')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 193 lines checked
Patch 20/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/66 Checking commit 0a0492fcd800 (target/mips: Add !CONFIG_USER_ONLY comment after
#endif)
22/66 Checking commit 514bb3169df2 (target/mips: Remove consecutive CONFIG_USER_ONLY
ifdefs)
23/66 Checking commit d1c975707e12 (target/mips: Move common helpers from helper.c to
cpu.c)
ERROR: space prohibited after that '&' (ctx:WxW)
#40: FILE: target/mips/cpu.c:53:
+ cu = (v >> CP0St_CU0) & 0xf;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#41: FILE: target/mips/cpu.c:54:
+ mx = (v >> CP0St_MX) & 0x1;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#42: FILE: target/mips/cpu.c:55:
+ ksu = (v >> CP0St_KSU) & 0x3;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#69: FILE: target/mips/cpu.c:82:
+ uint32_t ksux = (1 << CP0St_KX) & val;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#77: FILE: target/mips/cpu.c:90:
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#104: FILE: target/mips/cpu.c:117:
+ mask &= ~((1 << CP0Ca_WP) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#109: FILE: target/mips/cpu.c:122:
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#119: FILE: target/mips/cpu.c:132:
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
^
total: 8 errors, 0 warnings, 433 lines checked
Patch 23/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/66 Checking commit 597531ae621e (target/mips: Rename helper.c as tlb_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33:
rename from target/mips/helper.c
total: 0 errors, 1 warnings, 17 lines checked
Patch 24/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
25/66 Checking commit bf9cbc309ca7 (target/mips: Fix code style for checkpatch.pl)
26/66 Checking commit 01c87b9da531 (target/mips: Move mmu_init() functions to
tlb_helper.c)
27/66 Checking commit e31d0fb8b891 (target/mips: Rename translate_init.c as cpu-defs.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17:
rename from target/mips/translate_init.c.inc
total: 0 errors, 1 warnings, 8 lines checked
Patch 27/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
28/66 Checking commit 7dbaf2f8475b (target/mips/translate: Extract DisasContext
structure)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#73:
new file mode 100644
total: 0 errors, 1 warnings, 100 lines checked
Patch 28/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/66 Checking commit 734af7c7cd5f (target/mips/translate: Add declarations for generic
code)
30/66 Checking commit 4a7f56f756f1 (target/mips: Replace gen_exception_err(err=0) by
gen_exception_end())
31/66 Checking commit 7d45714935f0 (target/mips: Replace gen_exception_end(EXCP_RI) by
gen_rsvd_instruction)
32/66 Checking commit d664570b4d0e (target/mips: Declare generic FPU functions in
'translate.h')
33/66 Checking commit bf286b108260 (target/mips: Extract FPU specific definitions to
translate.h)
34/66 Checking commit ae2962d6ae59 (target/mips: Only build TCG code when CONFIG_TCG is
set)
35/66 Checking commit 4ad62c011a12 (target/mips/translate: Extract decode_opc_legacy()
from decode_opc())
36/66 Checking commit 154d914967f5 (target/mips/translate: Expose check_mips_64() to
32-bit mode)
37/66 Checking commit a6f9803fd299 (target/mips: Introduce ase_msa_available() helper)
38/66 Checking commit dd2ba3abe7b4 (target/mips: Simplify msa_reset())
39/66 Checking commit 9be6e1d7f765 (target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA)
40/66 Checking commit 279cca136d3f (target/mips: Simplify MSA TCG logic)
41/66 Checking commit 5dca6da28810 (target/mips: Remove now unused ASE_MSA definition)
42/66 Checking commit b41e6f53d419 (target/mips: Alias MSA vector registers on FPU scalar
registers)
43/66 Checking commit 5717a131e32b (target/mips: Extract msa_translate_init() from
mips_tcg_init())
44/66 Checking commit f6e81a3cc0c8 (target/mips: Remove CPUMIPSState* argument from
gen_msa*() methods)
45/66 Checking commit 187fc3480672 (target/mips: Explode gen_msa_branch() as
gen_msa_BxZ_V/BxZ())
46/66 Checking commit ff8dd8556127 (target/mips: Move msa_reset() to msa_helper.c)
47/66 Checking commit 5c3ca1b4d69d (target/mips: Extract MSA helpers from op_helper.c)
48/66 Checking commit e2ebaf4ae29e (target/mips: Extract MSA helper definitions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#461:
new file mode 100644
total: 0 errors, 1 warnings, 883 lines checked
Patch 48/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
49/66 Checking commit 574002aa479c (target/mips: Declare gen_msa/_branch() in
'translate.h')
50/66 Checking commit e844e9c880a9 (target/mips: Extract MSA translation routines)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 4551 lines checked
Patch 50/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
51/66 Checking commit e0b0e2b8f499 (target/mips: Pass TCGCond argument to MSA
gen_check_zero_element())
52/66 Checking commit 779aa4f7226b (target/mips: Introduce decode tree bindings for MSA
ASE)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35:
new file mode 100644
total: 0 errors, 1 warnings, 103 lines checked
Patch 52/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
53/66 Checking commit aa36e31acb54 (target/mips: Use decode_ase_msa() generated from
decodetree)
54/66 Checking commit 992d01ed4aaa (target/mips: Extract LSA/DLSA translation generators)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#119:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 54/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
55/66 Checking commit b862386020fc (target/mips: Introduce decodetree helpers for MSA
LSA/DLSA opcodes)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 65 lines checked
Patch 55/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
56/66 Checking commit 36d8c0ede396 (target/mips: Introduce decodetree helpers for Release6
LSA/DLSA opcodes)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36:
new file mode 100644
WARNING: line over 80 characters
#133: FILE: target/mips/translate.c:29031:
+ if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx,
ctx->opcode)) {
total: 0 errors, 2 warnings, 102 lines checked
Patch 56/66 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
57/66 Checking commit 02dbc3d3d79b (target/mips: Remove now unreachable LSA/DLSA opcodes
code)
58/66 Checking commit 1ac816021bc6 (target/mips: Convert Rel6 Special2 opcode to
decodetree)
59/66 Checking commit ce5072b957f9 (target/mips: Convert Rel6 COP1X opcode to decodetree)
60/66 Checking commit 218216b9e8dd (target/mips: Convert Rel6 CACHE/PREF opcodes to
decodetree)
61/66 Checking commit 4ef5b183d3bb (target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to
decodetree)
62/66 Checking commit d31fb7133964 (target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes
to decodetree)
63/66 Checking commit a3a47cc9c1fc (target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to
decodetree)
64/66 Checking commit 30b29c544e10 (target/mips: Convert Rel6 LLD/SCD opcodes to
decodetree)
65/66 Checking commit 46b75150a917 (target/mips: Convert Rel6 LL/SC opcodes to
decodetree)
66/66 Checking commit dd377f9d6f40 (docs/system: Remove deprecated 'fulong2e'
machine alias)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210107222253.20382-1-f4bug@amsat.org/testing.ch....
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel(a)redhat.com
4:35 a.m.
On Thu, 7 Jan 2021 at 22:25, Philippe Mathieu-Daudé <f4bug(a)amsat.org> wrote:
The following changes since commit 470dd6bd360782f5137f7e3376af6a44658eb1d3:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-060121-4' into
staging (2021-01-06 22:18:36 +0000)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210107
for you to fetch changes up to f97d339d612b86d8d336a11f01719a10893d6707:
docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-07 22:57:49
+0100)
----------------------------------------------------------------
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
Hi; this failed to build on some of my hosts:
[1/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc'.
FAILED: libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
/usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
../../target/mips/mips64r6.decode --static-deco
de=decode_mips64r6 -o libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
Traceback (most recent call last):
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1397, in <module>
main()
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1308, in main
parse_file(f, toppat)
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
80: ordinal not in range(128)
[2/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc'.
FAILED: libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
/usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
../../target/mips/msa64.decode --static-decode=
decode_msa64 -o libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
Traceback (most recent call last):
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1397, in <module>
main()
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1308, in main
parse_file(f, toppat)
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
93: ordinal not in range(128)
etc.
Looks like decodetree fails to cope with non-ASCII characters in
its input file -- probably this depends on the host locale settings:
I think these hosts run in the 'C' locale.
thanks
-- PMM
5:28 a.m.
Hi Peter,
Le ven. 8 janv. 2021 11:35, Peter Maydell <peter.maydell(a)linaro.org> a
écrit :
On Thu, 7 Jan 2021 at 22:25, Philippe Mathieu-Daudé
<f4bug(a)amsat.org wrote:
> The following changes since commit
470dd6bd360782f5137f7e3376af6a44658eb1d3:
> Merge remote-tracking branch
'remotes/stsquad/tags/pull-testing-060121-4' into staging (2021-01-06
22:18:36 +0000)
> are available in the Git repository at:
> https://gitlab.com/philmd/qemu.git tags/mips-20210107
> for you to fetch changes up to
f97d339d612b86d8d336a11f01719a10893d6707:
> docs/system: Remove deprecated 'fulong2e'
machine alias (2021-01-07
22:57:49 +0100)
>
----------------------------------------------------------------
> MIPS patches queue
> - Simplify CPU/ISA definitions
> - Various maintenance code movements in translate.c
> - Convert part of the MSA ASE instructions to decodetree
> - Convert some instructions removed from Release 6 to decodetree
> - Remove deprecated 'fulong2e' machine alias
Hi; this failed to build on some of my hosts:
[1/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc'.
FAILED: libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
/usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
../../target/mips/mips64r6.decode --static-deco
de=decode_mips64r6 -o libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
Traceback (most recent call last):
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1397, in <module main()
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1308, in main
parse_file(f, toppat)
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
80: ordinal not in range(128)
My lastname in the copyright line =)
[2/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc'.
FAILED: libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
/usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
../../target/mips/msa64.decode --static-decode=
decode_msa64 -o libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
Traceback (most recent call last):
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1397, in <module main()
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
1308, in main
parse_file(f, toppat)
File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
93: ordinal not in range(128)
etc.
Looks like decodetree fails to cope with non-ASCII characters in
its input file -- probably this depends on the host locale settings:
I think these hosts run in the 'C' locale.
Can you provide more information on your host so we can cover it in
Gitlab-CI?
Thanks,
Phil.
5:54 a.m.
On Fri, 8 Jan 2021 at 11:28, Philippe Mathieu-Daudé <f4bug(a)amsat.org> wrote:
Le ven. 8 janv. 2021 11:35, Peter Maydell
<peter.maydell(a)linaro.org> a écrit :
> Looks like decodetree fails to cope with non-ASCII characters in
> its input file -- probably this depends on the host locale settings:
> I think these hosts run in the 'C' locale.
Can you provide more information on your host so we can cover it in Gitlab-CI?
It's just the windows crossbuilds on x86-64 Linux, and also the
aarch32-on-aarch64 chroot. I'm pretty sure that the only relevant
detail here is going to be the host LANG/etc environment variable
settings when 'make' is run, though.
thanks
-- PMM
9:22 a.m.
On Fri, Jan 8, 2021 at 3:31 AM Philippe Mathieu-Daudé <f4bug(a)amsat.org>
wrote:
Hi Peter,
Le ven. 8 janv. 2021 11:35, Peter Maydell <peter.maydell(a)linaro.org> a
écrit
:
>
> On Thu, 7 Jan 2021 at 22:25, Philippe Mathieu-Daudé <f4bug(a)amsat.org>
wrote:
> >
> > The following changes since commit
470dd6bd360782f5137f7e3376af6a44658eb1d3:
> >
> > Merge remote-tracking branch
'remotes/stsquad/tags/pull-testing-060121-4' into staging (2021-01-06
22:18:36 +0000)
> >
> > are available in the Git repository at:
> >
> > https://gitlab.com/philmd/qemu.git tags/mips-20210107
> >
> > for you to fetch changes up to
f97d339d612b86d8d336a11f01719a10893d6707:
> >
> > docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-07
22:57:49 +0100)
> >
> > ----------------------------------------------------------------
> > MIPS patches queue
> >
> > - Simplify CPU/ISA definitions
> > - Various maintenance code movements in translate.c
> > - Convert part of the MSA ASE instructions to decodetree
> > - Convert some instructions removed from Release 6 to decodetree
> > - Remove deprecated 'fulong2e' machine alias
>
> Hi; this failed to build on some of my hosts:
>
> [1/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc'.
> FAILED: libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
> /usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
> ../../target/mips/mips64r6.decode --static-deco
> de=decode_mips64r6 -o libqemu-mipsel-softmmu.fa.p/decode-mips64r6.c.inc
> Traceback (most recent call last):
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 1397, in <module>
> main()
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 1308, in main
> parse_file(f, toppat)
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 994, in parse_file
> for line in f:
> File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
> return codecs.ascii_decode(input, self.errors)[0]
> UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
> 80: ordinal not in range(128)
Can we always reading file in decodetree with
utf8 encoding
And convert all decodetree to utf8 encoding, and the problem should
resolved.
```
scripts/decodetree.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 47aa9caf6d..8c9eb365ac 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -1304,7 +1304,7 @@ def main():
for filename in args:
input_file = filename
- f = open(filename, 'r')
+ f = open(filename, 'r', encoding="utf8")
parse_file(f, toppat)
f.close()
```
My lastname in the copyright line =)
> [2/4674] Generating 'libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc'.
> FAILED: libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
> /usr/bin/python3 /home/petmay01/qemu-for-merges/scripts/decodetree.py
> ../../target/mips/msa64.decode --static-decode=
> decode_msa64 -o libqemu-mipsel-softmmu.fa.p/decode-msa64.c.inc
> Traceback (most recent call last):
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 1397, in <module>
> main()
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 1308, in main
> parse_file(f, toppat)
> File "/home/petmay01/qemu-for-merges/scripts/decodetree.py", line
> 994, in parse_file
> for line in f:
> File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
> return codecs.ascii_decode(input, self.errors)[0]
> UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position
> 93: ordinal not in range(128)
>
> etc.
>
> Looks like decodetree fails to cope with non-ASCII characters in
> its input file -- probably this depends on the host locale settings:
> I think these hosts run in the 'C' locale.
Can you provide more information on your host so we can cover it in
Gitlab-CI?
Thanks,
Phil.
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
12:48 p.m.
On 1/8/21 5:22 AM, 罗勇刚(Yonggang Luo) wrote:
>> UnicodeDecodeError: 'ascii' codec can't decode
byte 0xc3 in position
>> 80: ordinal not in range(128)
Can we always reading file in decodetree with utf8 encoding
And convert all decodetree to utf8 encoding, and the problem should resolved.
```
scripts/decodetree.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 47aa9caf6d..8c9eb365ac 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -1304,7 +1304,7 @@ def main():
for filename in args:
input_file = filename
- f = open(filename, 'r')
+ f = open(filename, 'r', encoding="utf8")
parse_file(f, toppat)
f.close()
```
Thanks. Would you like to send a formal patch?
r~
1450
days inactive
1451
days old
73 comments
5 participants
participants (5)
-
no-reply＠patchew.org -
Peter Maydell -
Philippe Mathieu-Daudé -
Richard Henderson -
罗勇刚(Yonggang Luo)