5:13 a.m.
Christian Ehrhardt (1):
cpu_map: Add more -noTSX x86 CPU models
Jiri Denemark (3):
cpu_map: Add <decode> element to x86 CPU model definitions
cpu_x86: Honor CPU models' <decode> element
cpu_map: Don't use new noTSX models for host-model CPUs
src/cpu/cpu_x86.c | 65 ++++++++++++-
src/cpu_map/Makefile.inc.am | 5 +
src/cpu_map/index.xml | 5 +
src/cpu_map/x86_486.xml | 1 +
src/cpu_map/x86_Broadwell-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX.xml | 1 +
src/cpu_map/x86_Broadwell.xml | 1 +
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 79 ++++++++++++++++
src/cpu_map/x86_Cascadelake-Server.xml | 1 +
src/cpu_map/x86_Conroe.xml | 1 +
src/cpu_map/x86_Dhyana.xml | 1 +
src/cpu_map/x86_EPYC-IBPB.xml | 1 +
src/cpu_map/x86_EPYC.xml | 1 +
src/cpu_map/x86_Haswell-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX.xml | 1 +
src/cpu_map/x86_Haswell.xml | 1 +
src/cpu_map/x86_Icelake-Client-noTSX.xml | 82 +++++++++++++++++
src/cpu_map/x86_Icelake-Client.xml | 1 +
src/cpu_map/x86_Icelake-Server-noTSX.xml | 91 +++++++++++++++++++
src/cpu_map/x86_Icelake-Server.xml | 1 +
src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
src/cpu_map/x86_IvyBridge.xml | 1 +
src/cpu_map/x86_Nehalem-IBRS.xml | 1 +
src/cpu_map/x86_Nehalem.xml | 1 +
src/cpu_map/x86_Opteron_G1.xml | 1 +
src/cpu_map/x86_Opteron_G2.xml | 1 +
src/cpu_map/x86_Opteron_G3.xml | 1 +
src/cpu_map/x86_Opteron_G4.xml | 1 +
src/cpu_map/x86_Opteron_G5.xml | 1 +
src/cpu_map/x86_Penryn.xml | 1 +
src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
src/cpu_map/x86_SandyBridge.xml | 1 +
src/cpu_map/x86_Skylake-Client-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 74 +++++++++++++++
src/cpu_map/x86_Skylake-Client.xml | 1 +
src/cpu_map/x86_Skylake-Server-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 76 ++++++++++++++++
src/cpu_map/x86_Skylake-Server.xml | 1 +
src/cpu_map/x86_Westmere-IBRS.xml | 1 +
src/cpu_map/x86_Westmere.xml | 1 +
src/cpu_map/x86_athlon.xml | 1 +
src/cpu_map/x86_core2duo.xml | 1 +
src/cpu_map/x86_coreduo.xml | 1 +
src/cpu_map/x86_cpu64-rhel5.xml | 1 +
src/cpu_map/x86_cpu64-rhel6.xml | 1 +
src/cpu_map/x86_kvm32.xml | 1 +
src/cpu_map/x86_kvm64.xml | 1 +
src/cpu_map/x86_n270.xml | 1 +
src/cpu_map/x86_pentium.xml | 1 +
src/cpu_map/x86_pentium2.xml | 1 +
src/cpu_map/x86_pentium3.xml | 1 +
src/cpu_map/x86_pentiumpro.xml | 1 +
src/cpu_map/x86_phenom.xml | 1 +
src/cpu_map/x86_qemu32.xml | 1 +
src/cpu_map/x86_qemu64.xml | 1 +
.../x86_64-cpuid-Core-i7-8550U-host.xml | 11 +--
.../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 5 +
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 5 +
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 5 +
.../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 5 +
.../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 5 +
tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 5 +
64 files changed, 552 insertions(+), 15 deletions(-)
create mode 100644 src/cpu_map/x86_Cascadelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Client-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
create mode 100644 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
--
2.25.1
5:13 a.m.
New subject: [libvirt PATCH 1/4] cpu_map: Add more -noTSX x86 CPU models
From: Christian Ehrhardt <christian.ehrhardt(a)canonical.com>
One of the mitigation methods for TAA[1] is to disable TSX
support on the host system. Linux added a mechanism to disable
TSX globally through the kernel command line, and many Linux
distributions now default to tsx=off. This makes existing CPU
models that have HLE and RTM enabled not usable anymore.
Add new versions of all CPU models that have the HLE and RTM
features enabled, that can be used when TSX is disabled in the
host system.
On systems disabling the features without those types defined
in cpu-maps users end up without modern CPU types in the list
of usable CPUs to use in the likes of virsh domcapabilities
or tools higher in the stack like virt-manager.
This adds:
-Cascadelake-Server-noTSX
-Icelake-Client-noTSX
-Icelake-Server-noTSX
-Skylake-Server-noTSX-IBRS
-Skylake-Client-noTSX-IBRS
Introduced in QEMU by commit v4.2.0-rc2-3-g9ab2237f19 (function)
and commit v4.2.0-rc2-4-g02fa60d101 (names)
References:
[1] TAA, TSX asynchronous Abort:
https://software.intel.com/security-software-guidance/insights/deep-dive-...
https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abor...
Fixes: https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1853200
Signed-off-by: Christian Ehrhardt <christian.ehrhardt(a)canonical.com>
Message-Id: <20200310104806.2723-2-christian.ehrhardt(a)canonical.com>
Reviewed-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/Makefile.inc.am | 5 ++
src/cpu_map/index.xml | 5 ++
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 78 ++++++++++++++++
src/cpu_map/x86_Icelake-Client-noTSX.xml | 81 +++++++++++++++++
src/cpu_map/x86_Icelake-Server-noTSX.xml | 90 +++++++++++++++++++
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 73 +++++++++++++++
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 75 ++++++++++++++++
.../x86_64-cpuid-Core-i7-8550U-guest.xml | 4 +-
.../x86_64-cpuid-Core-i7-8550U-host.xml | 11 +--
.../x86_64-cpuid-Core-i7-8550U-json.xml | 4 +-
.../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 5 ++
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 5 ++
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 5 ++
.../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 5 ++
.../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 5 ++
tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 5 ++
16 files changed, 440 insertions(+), 16 deletions(-)
create mode 100644 src/cpu_map/x86_Cascadelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Client-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
create mode 100644 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
diff --git a/src/cpu_map/Makefile.inc.am b/src/cpu_map/Makefile.inc.am
index e935178304..be64c9a0d4 100644
--- a/src/cpu_map/Makefile.inc.am
+++ b/src/cpu_map/Makefile.inc.am
@@ -20,6 +20,7 @@ cpumap_DATA = \
cpu_map/x86_Broadwell-noTSX.xml \
cpu_map/x86_Broadwell-noTSX-IBRS.xml \
cpu_map/x86_Cascadelake-Server.xml \
+ cpu_map/x86_Cascadelake-Server-noTSX.xml \
cpu_map/x86_Conroe.xml \
cpu_map/x86_core2duo.xml \
cpu_map/x86_coreduo.xml \
@@ -33,7 +34,9 @@ cpumap_DATA = \
cpu_map/x86_Haswell-noTSX.xml \
cpu_map/x86_Haswell-noTSX-IBRS.xml \
cpu_map/x86_Icelake-Client.xml \
+ cpu_map/x86_Icelake-Client-noTSX.xml \
cpu_map/x86_Icelake-Server.xml \
+ cpu_map/x86_Icelake-Server-noTSX.xml \
cpu_map/x86_IvyBridge.xml \
cpu_map/x86_IvyBridge-IBRS.xml \
cpu_map/x86_kvm32.xml \
@@ -58,8 +61,10 @@ cpumap_DATA = \
cpu_map/x86_SandyBridge-IBRS.xml \
cpu_map/x86_Skylake-Client.xml \
cpu_map/x86_Skylake-Client-IBRS.xml \
+ cpu_map/x86_Skylake-Client-noTSX-IBRS.xml \
cpu_map/x86_Skylake-Server.xml \
cpu_map/x86_Skylake-Server-IBRS.xml \
+ cpu_map/x86_Skylake-Server-noTSX-IBRS.xml \
cpu_map/x86_Westmere.xml \
cpu_map/x86_Westmere-IBRS.xml \
$(NULL)
diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml
index ffb2f6fe1b..50b030de29 100644
--- a/src/cpu_map/index.xml
+++ b/src/cpu_map/index.xml
@@ -44,11 +44,16 @@
<include filename="x86_Broadwell-IBRS.xml"/>
<include filename="x86_Skylake-Client.xml"/>
<include filename="x86_Skylake-Client-IBRS.xml"/>
+ <include filename="x86_Skylake-Client-noTSX-IBRS.xml"/>
<include filename="x86_Skylake-Server.xml"/>
<include filename="x86_Skylake-Server-IBRS.xml"/>
+ <include filename="x86_Skylake-Server-noTSX-IBRS.xml"/>
<include filename="x86_Cascadelake-Server.xml"/>
+ <include filename="x86_Cascadelake-Server-noTSX.xml"/>
<include filename="x86_Icelake-Client.xml"/>
+ <include filename="x86_Icelake-Client-noTSX.xml"/>
<include filename="x86_Icelake-Server.xml"/>
+ <include filename="x86_Icelake-Server-noTSX.xml"/>
<!-- AMD CPUs -->
<include filename="x86_athlon.xml"/>
diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
new file mode 100644
index 0000000000..d24415ebce
--- /dev/null
+++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
@@ -0,0 +1,78 @@
+<cpus>
+ <model name='Cascadelake-Server-noTSX'>
+ <signature family='6' model='85'/> <!-- 050654 -->
+ <vendor name='Intel'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='aes'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='avx512bw'/>
+ <feature name='avx512cd'/>
+ <feature name='avx512dq'/>
+ <feature name='avx512f'/>
+ <feature name='avx512vl'/>
+ <feature name='avx512vnni'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='clflushopt'/>
+ <feature name='clwb'/>
+ <feature name='cmov'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='erms'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='invpcid'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='mmx'/>
+ <feature name='movbe'/>
+ <feature name='mpx'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pcid'/>
+ <feature name='pclmuldq'/>
+ <feature name='pdpe1gb'/>
+ <feature name='pge'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='spec-ctrl'/>
+ <feature name='ssbd'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='ssse3'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='tsc-deadline'/>
+ <feature name='vme'/>
+ <feature name='x2apic'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/src/cpu_map/x86_Icelake-Client-noTSX.xml
b/src/cpu_map/x86_Icelake-Client-noTSX.xml
new file mode 100644
index 0000000000..cd51881f40
--- /dev/null
+++ b/src/cpu_map/x86_Icelake-Client-noTSX.xml
@@ -0,0 +1,81 @@
+<cpus>
+ <model name='Icelake-Client-noTSX'>
+ <signature family='6' model='126'/> <!-- 0706e0 -->
+ <vendor name='Intel'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='aes'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='avx512-vpopcntdq'/>
+ <feature name='avx512bitalg'/>
+ <feature name='avx512vbmi'/>
+ <feature name='avx512vbmi2'/>
+ <feature name='avx512vnni'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='cmov'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='erms'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='gfni'/>
+ <feature name='intel-pt'/>
+ <feature name='invpcid'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='mmx'/>
+ <feature name='movbe'/>
+ <feature name='mpx'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pcid'/>
+ <feature name='pclmuldq'/>
+ <feature name='pge'/>
+ <feature name='pku'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='spec-ctrl'/>
+ <feature name='ssbd'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='ssse3'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='tsc-deadline'/>
+ <feature name='umip'/>
+ <feature name='vaes'/>
+ <feature name='vme'/>
+ <feature name='vpclmulqdq'/>
+ <feature name='wbnoinvd'/>
+ <feature name='x2apic'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml
b/src/cpu_map/x86_Icelake-Server-noTSX.xml
new file mode 100644
index 0000000000..538c656712
--- /dev/null
+++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml
@@ -0,0 +1,90 @@
+<cpus>
+ <model name='Icelake-Server-noTSX'>
+ <signature family='6' model='134'/> <!-- 080660 -->
+ <vendor name='Intel'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='aes'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='avx512-vpopcntdq'/>
+ <feature name='avx512bitalg'/>
+ <feature name='avx512bw'/>
+ <feature name='avx512cd'/>
+ <feature name='avx512dq'/>
+ <feature name='avx512f'/>
+ <feature name='avx512vbmi'/>
+ <feature name='avx512vbmi2'/>
+ <feature name='avx512vl'/>
+ <feature name='avx512vnni'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='clflushopt'/>
+ <feature name='clwb'/>
+ <feature name='cmov'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='erms'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='gfni'/>
+ <feature name='intel-pt'/>
+ <feature name='invpcid'/>
+ <feature name='la57'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='mmx'/>
+ <feature name='movbe'/>
+ <feature name='mpx'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pcid'/>
+ <feature name='pclmuldq'/>
+ <feature name='pdpe1gb'/>
+ <feature name='pge'/>
+ <feature name='pku'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='spec-ctrl'/>
+ <feature name='ssbd'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='ssse3'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='tsc-deadline'/>
+ <feature name='umip'/>
+ <feature name='vaes'/>
+ <feature name='vme'/>
+ <feature name='vpclmulqdq'/>
+ <feature name='wbnoinvd'/>
+ <feature name='x2apic'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
new file mode 100644
index 0000000000..3d2976692f
--- /dev/null
+++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
@@ -0,0 +1,73 @@
+<cpus>
+ <model name='Skylake-Client-noTSX-IBRS'>
+ <signature family='6' model='94'/> <!-- 0506e0 -->
+ <signature family='6' model='78'/> <!-- 0406e0 -->
+ <!-- These are Kaby Lake and Coffee Lake successors to Skylake,
+ but we don't have specific models for them. -->
+ <signature family='6' model='142'/> <!-- 0806e0 -->
+ <signature family='6' model='158'/> <!-- 0906e0 -->
+ <vendor name='Intel'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='aes'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='cmov'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='erms'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='invpcid'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='mmx'/>
+ <feature name='movbe'/>
+ <feature name='mpx'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pcid'/>
+ <feature name='pclmuldq'/>
+ <feature name='pge'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='spec-ctrl'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='ssse3'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='tsc-deadline'/>
+ <feature name='vme'/>
+ <feature name='x2apic'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
new file mode 100644
index 0000000000..455a072119
--- /dev/null
+++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
@@ -0,0 +1,75 @@
+<cpus>
+ <model name='Skylake-Server-noTSX-IBRS'>
+ <signature family='6' model='85'/> <!-- 050654 -->
+ <vendor name='Intel'/>
+ <feature name='3dnowprefetch'/>
+ <feature name='abm'/>
+ <feature name='adx'/>
+ <feature name='aes'/>
+ <feature name='apic'/>
+ <feature name='arat'/>
+ <feature name='avx'/>
+ <feature name='avx2'/>
+ <feature name='avx512bw'/>
+ <feature name='avx512cd'/>
+ <feature name='avx512dq'/>
+ <feature name='avx512f'/>
+ <feature name='avx512vl'/>
+ <feature name='bmi1'/>
+ <feature name='bmi2'/>
+ <feature name='clflush'/>
+ <feature name='clwb'/>
+ <feature name='cmov'/>
+ <feature name='cx16'/>
+ <feature name='cx8'/>
+ <feature name='de'/>
+ <feature name='erms'/>
+ <feature name='f16c'/>
+ <feature name='fma'/>
+ <feature name='fpu'/>
+ <feature name='fsgsbase'/>
+ <feature name='fxsr'/>
+ <feature name='invpcid'/>
+ <feature name='lahf_lm'/>
+ <feature name='lm'/>
+ <feature name='mca'/>
+ <feature name='mce'/>
+ <feature name='mmx'/>
+ <feature name='movbe'/>
+ <feature name='mpx'/>
+ <feature name='msr'/>
+ <feature name='mtrr'/>
+ <feature name='nx'/>
+ <feature name='pae'/>
+ <feature name='pat'/>
+ <feature name='pcid'/>
+ <feature name='pclmuldq'/>
+ <feature name='pdpe1gb'/>
+ <feature name='pge'/>
+ <feature name='pni'/>
+ <feature name='popcnt'/>
+ <feature name='pse'/>
+ <feature name='pse36'/>
+ <feature name='rdrand'/>
+ <feature name='rdseed'/>
+ <feature name='rdtscp'/>
+ <feature name='sep'/>
+ <feature name='smap'/>
+ <feature name='smep'/>
+ <feature name='spec-ctrl'/>
+ <feature name='sse'/>
+ <feature name='sse2'/>
+ <feature name='sse4.1'/>
+ <feature name='sse4.2'/>
+ <feature name='ssse3'/>
+ <feature name='syscall'/>
+ <feature name='tsc'/>
+ <feature name='tsc-deadline'/>
+ <feature name='vme'/>
+ <feature name='x2apic'/>
+ <feature name='xgetbv1'/>
+ <feature name='xsave'/>
+ <feature name='xsavec'/>
+ <feature name='xsaveopt'/>
+ </model>
+</cpus>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
index 92404e4d03..e03c4a06ba 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
@@ -1,5 +1,5 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <model fallback='forbid'>Skylake-Client-noTSX-IBRS</model>
<vendor>Intel</vendor>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
@@ -26,6 +26,4 @@
<feature policy='require' name='pdpe1gb'/>
<feature policy='require' name='invtsc'/>
<feature policy='require' name='skip-l1dfl-vmentry'/>
- <feature policy='disable' name='hle'/>
- <feature policy='disable' name='rtm'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-host.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-host.xml
index 808a8ff969..7f6fe2eac3 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-host.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-host.xml
@@ -1,8 +1,7 @@
<cpu>
<arch>x86_64</arch>
- <model>Broadwell-noTSX-IBRS</model>
+ <model>Skylake-Client-noTSX-IBRS</model>
<vendor>Intel</vendor>
- <feature name='vme'/>
<feature name='ds'/>
<feature name='acpi'/>
<feature name='ss'/>
@@ -18,22 +17,14 @@
<feature name='xtpr'/>
<feature name='pdcm'/>
<feature name='osxsave'/>
- <feature name='f16c'/>
- <feature name='rdrand'/>
- <feature name='arat'/>
<feature name='tsc_adjust'/>
- <feature name='mpx'/>
<feature name='clflushopt'/>
<feature name='intel-pt'/>
<feature name='md-clear'/>
<feature name='stibp'/>
<feature name='ssbd'/>
- <feature name='xsaveopt'/>
- <feature name='xsavec'/>
- <feature name='xgetbv1'/>
<feature name='xsaves'/>
<feature name='pdpe1gb'/>
- <feature name='abm'/>
<feature name='invtsc'/>
<feature name='skip-l1dfl-vmentry'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
index 645c0934c2..3d8e6775bf 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
@@ -1,5 +1,5 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-IBRS</model>
+ <model fallback='forbid'>Skylake-Client-noTSX-IBRS</model>
<vendor>Intel</vendor>
<feature policy='require' name='ss'/>
<feature policy='require' name='vmx'/>
@@ -14,6 +14,4 @@
<feature policy='require' name='xsaves'/>
<feature policy='require' name='pdpe1gb'/>
<feature policy='require' name='skip-l1dfl-vmentry'/>
- <feature policy='disable' name='hle'/>
- <feature policy='disable' name='rtm'/>
</cpu>
diff --git a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
index eaa3b75695..1b8b8be2f5 100644
--- a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
+++ b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
@@ -63,8 +63,10 @@
<model usable='no'>athlon</model>
<model usable='yes'>Westmere-IBRS</model>
<model usable='yes'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='yes'>Skylake-Client-noTSX-IBRS</model>
<model usable='yes'>Skylake-Client-IBRS</model>
<model usable='yes'>Skylake-Client</model>
<model usable='yes'>SandyBridge-IBRS</model>
@@ -79,7 +81,9 @@
<model usable='yes'>Nehalem</model>
<model usable='yes'>IvyBridge-IBRS</model>
<model usable='yes'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='yes'>Haswell-noTSX-IBRS</model>
<model usable='yes'>Haswell-noTSX</model>
@@ -89,6 +93,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='yes'>Broadwell-noTSX-IBRS</model>
<model usable='yes'>Broadwell-noTSX</model>
diff --git a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml
b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml
index af482e3821..a348c7f2fc 100644
--- a/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml
+++ b/tests/domaincapsdata/qemu_4.2.0-tcg.x86_64.xml
@@ -73,8 +73,10 @@
<model usable='yes'>athlon</model>
<model usable='no'>Westmere-IBRS</model>
<model usable='no'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='no'>Skylake-Client-noTSX-IBRS</model>
<model usable='no'>Skylake-Client-IBRS</model>
<model usable='no'>Skylake-Client</model>
<model usable='no'>SandyBridge-IBRS</model>
@@ -89,7 +91,9 @@
<model usable='no'>Nehalem</model>
<model usable='no'>IvyBridge-IBRS</model>
<model usable='no'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='no'>Haswell-noTSX-IBRS</model>
<model usable='no'>Haswell-noTSX</model>
@@ -99,6 +103,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='no'>Broadwell-noTSX-IBRS</model>
<model usable='no'>Broadwell-noTSX</model>
diff --git a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml
b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml
index c82d12d3ce..213dcc5a08 100644
--- a/tests/domaincapsdata/qemu_4.2.0.x86_64.xml
+++ b/tests/domaincapsdata/qemu_4.2.0.x86_64.xml
@@ -62,8 +62,10 @@
<model usable='no'>athlon</model>
<model usable='yes'>Westmere-IBRS</model>
<model usable='yes'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='yes'>Skylake-Client-noTSX-IBRS</model>
<model usable='yes'>Skylake-Client-IBRS</model>
<model usable='yes'>Skylake-Client</model>
<model usable='yes'>SandyBridge-IBRS</model>
@@ -78,7 +80,9 @@
<model usable='yes'>Nehalem</model>
<model usable='yes'>IvyBridge-IBRS</model>
<model usable='yes'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='yes'>Haswell-noTSX-IBRS</model>
<model usable='yes'>Haswell-noTSX</model>
@@ -88,6 +92,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='yes'>Broadwell-noTSX-IBRS</model>
<model usable='yes'>Broadwell-noTSX</model>
diff --git a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml
b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml
index d60ea85ffc..45c3e00b1e 100644
--- a/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml
+++ b/tests/domaincapsdata/qemu_5.0.0-q35.x86_64.xml
@@ -63,8 +63,10 @@
<model usable='no'>athlon</model>
<model usable='yes'>Westmere-IBRS</model>
<model usable='yes'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='yes'>Skylake-Client-noTSX-IBRS</model>
<model usable='yes'>Skylake-Client-IBRS</model>
<model usable='yes'>Skylake-Client</model>
<model usable='yes'>SandyBridge-IBRS</model>
@@ -79,7 +81,9 @@
<model usable='yes'>Nehalem</model>
<model usable='yes'>IvyBridge-IBRS</model>
<model usable='yes'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='yes'>Haswell-noTSX-IBRS</model>
<model usable='yes'>Haswell-noTSX</model>
@@ -89,6 +93,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='yes'>Broadwell-noTSX-IBRS</model>
<model usable='yes'>Broadwell-noTSX</model>
diff --git a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml
b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml
index 6c9ab40ca4..d567863f49 100644
--- a/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml
+++ b/tests/domaincapsdata/qemu_5.0.0-tcg.x86_64.xml
@@ -72,8 +72,10 @@
<model usable='yes'>athlon</model>
<model usable='no'>Westmere-IBRS</model>
<model usable='yes'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='no'>Skylake-Client-noTSX-IBRS</model>
<model usable='no'>Skylake-Client-IBRS</model>
<model usable='no'>Skylake-Client</model>
<model usable='no'>SandyBridge-IBRS</model>
@@ -88,7 +90,9 @@
<model usable='yes'>Nehalem</model>
<model usable='no'>IvyBridge-IBRS</model>
<model usable='no'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='no'>Haswell-noTSX-IBRS</model>
<model usable='no'>Haswell-noTSX</model>
@@ -98,6 +102,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='no'>Broadwell-noTSX-IBRS</model>
<model usable='no'>Broadwell-noTSX</model>
diff --git a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml
b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml
index 6b5f175614..d2a884eed1 100644
--- a/tests/domaincapsdata/qemu_5.0.0.x86_64.xml
+++ b/tests/domaincapsdata/qemu_5.0.0.x86_64.xml
@@ -62,8 +62,10 @@
<model usable='no'>athlon</model>
<model usable='yes'>Westmere-IBRS</model>
<model usable='yes'>Westmere</model>
+ <model usable='no'>Skylake-Server-noTSX-IBRS</model>
<model usable='no'>Skylake-Server-IBRS</model>
<model usable='no'>Skylake-Server</model>
+ <model usable='yes'>Skylake-Client-noTSX-IBRS</model>
<model usable='yes'>Skylake-Client-IBRS</model>
<model usable='yes'>Skylake-Client</model>
<model usable='yes'>SandyBridge-IBRS</model>
@@ -78,7 +80,9 @@
<model usable='yes'>Nehalem</model>
<model usable='yes'>IvyBridge-IBRS</model>
<model usable='yes'>IvyBridge</model>
+ <model usable='no'>Icelake-Server-noTSX</model>
<model usable='no'>Icelake-Server</model>
+ <model usable='no'>Icelake-Client-noTSX</model>
<model usable='no'>Icelake-Client</model>
<model usable='yes'>Haswell-noTSX-IBRS</model>
<model usable='yes'>Haswell-noTSX</model>
@@ -88,6 +92,7 @@
<model usable='no'>EPYC</model>
<model usable='no'>Dhyana</model>
<model usable='yes'>Conroe</model>
+ <model usable='no'>Cascadelake-Server-noTSX</model>
<model usable='no'>Cascadelake-Server</model>
<model usable='yes'>Broadwell-noTSX-IBRS</model>
<model usable='yes'>Broadwell-noTSX</model>
--
2.25.1
5:13 a.m.
New subject: [libvirt PATCH 2/4] cpu_map: Add <decode> element to x86 CPU model definitions
The element specifies whether a particular CPU model can be used when
creating a CPU definition from raw CPUID/MSR data. The @host attribute
determines whether the CPU model can be used (host='on') for creating
CPU definition for host capabilities. Usability of the model for domain
capabilities and host-model CPU definitions is controlled by the @guest
attribute.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 43 +++++++++++++++++++
src/cpu_map/x86_486.xml | 1 +
src/cpu_map/x86_Broadwell-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX.xml | 1 +
src/cpu_map/x86_Broadwell.xml | 1 +
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 1 +
src/cpu_map/x86_Cascadelake-Server.xml | 1 +
src/cpu_map/x86_Conroe.xml | 1 +
src/cpu_map/x86_Dhyana.xml | 1 +
src/cpu_map/x86_EPYC-IBPB.xml | 1 +
src/cpu_map/x86_EPYC.xml | 1 +
src/cpu_map/x86_Haswell-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX.xml | 1 +
src/cpu_map/x86_Haswell.xml | 1 +
src/cpu_map/x86_Icelake-Client-noTSX.xml | 1 +
src/cpu_map/x86_Icelake-Client.xml | 1 +
src/cpu_map/x86_Icelake-Server-noTSX.xml | 1 +
src/cpu_map/x86_Icelake-Server.xml | 1 +
src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
src/cpu_map/x86_IvyBridge.xml | 1 +
src/cpu_map/x86_Nehalem-IBRS.xml | 1 +
src/cpu_map/x86_Nehalem.xml | 1 +
src/cpu_map/x86_Opteron_G1.xml | 1 +
src/cpu_map/x86_Opteron_G2.xml | 1 +
src/cpu_map/x86_Opteron_G3.xml | 1 +
src/cpu_map/x86_Opteron_G4.xml | 1 +
src/cpu_map/x86_Opteron_G5.xml | 1 +
src/cpu_map/x86_Penryn.xml | 1 +
src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
src/cpu_map/x86_SandyBridge.xml | 1 +
src/cpu_map/x86_Skylake-Client-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Client.xml | 1 +
src/cpu_map/x86_Skylake-Server-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Server.xml | 1 +
src/cpu_map/x86_Westmere-IBRS.xml | 1 +
src/cpu_map/x86_Westmere.xml | 1 +
src/cpu_map/x86_athlon.xml | 1 +
src/cpu_map/x86_core2duo.xml | 1 +
src/cpu_map/x86_coreduo.xml | 1 +
src/cpu_map/x86_cpu64-rhel5.xml | 1 +
src/cpu_map/x86_cpu64-rhel6.xml | 1 +
src/cpu_map/x86_kvm32.xml | 1 +
src/cpu_map/x86_kvm64.xml | 1 +
src/cpu_map/x86_n270.xml | 1 +
src/cpu_map/x86_pentium.xml | 1 +
src/cpu_map/x86_pentium2.xml | 1 +
src/cpu_map/x86_pentium3.xml | 1 +
src/cpu_map/x86_pentiumpro.xml | 1 +
src/cpu_map/x86_phenom.xml | 1 +
src/cpu_map/x86_qemu32.xml | 1 +
src/cpu_map/x86_qemu64.xml | 1 +
55 files changed, 97 insertions(+)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 7a8a2e3f3b..366337ef57 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -125,6 +125,8 @@ typedef struct _virCPUx86Model virCPUx86Model;
typedef virCPUx86Model *virCPUx86ModelPtr;
struct _virCPUx86Model {
char *name;
+ bool decodeHost;
+ bool decodeGuest;
virCPUx86VendorPtr vendor;
size_t nsignatures;
uint32_t *signatures;
@@ -1347,6 +1349,44 @@ x86ModelCompare(virCPUx86ModelPtr model1,
}
+static int
+x86ModelParseDecode(virCPUx86ModelPtr model,
+ xmlXPathContextPtr ctxt)
+{
+ g_autofree char *host = NULL;
+ g_autofree char *guest = NULL;
+ int val;
+
+ if ((host = virXPathString("string(./decode/@host)", ctxt)))
+ val = virTristateSwitchTypeFromString(host);
+ else
+ val = VIR_TRISTATE_SWITCH_ABSENT;
+
+ if (val <= 0) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("invalid or missing decode/host attribute in CPU model
%s"),
+ model->name);
+ return -1;
+ }
+ model->decodeHost = val == VIR_TRISTATE_SWITCH_ON;
+
+ if ((guest = virXPathString("string(./decode/@guest)", ctxt)))
+ val = virTristateSwitchTypeFromString(guest);
+ else
+ val = VIR_TRISTATE_SWITCH_ABSENT;
+
+ if (val <= 0) {
+ virReportError(VIR_ERR_INTERNAL_ERROR,
+ _("invalid or missing decode/guest attribute in CPU model
%s"),
+ model->name);
+ return -1;
+ }
+ model->decodeGuest = val == VIR_TRISTATE_SWITCH_ON;
+
+ return 0;
+}
+
+
static int
x86ModelParseAncestor(virCPUx86ModelPtr model,
xmlXPathContextPtr ctxt,
@@ -1521,6 +1561,9 @@ x86ModelParse(xmlXPathContextPtr ctxt,
model->name = g_strdup(name);
+ if (x86ModelParseDecode(model, ctxt) < 0)
+ goto cleanup;
+
if (x86ModelParseAncestor(model, ctxt, map) < 0)
goto cleanup;
diff --git a/src/cpu_map/x86_486.xml b/src/cpu_map/x86_486.xml
index 61fa3797e8..d05b277392 100644
--- a/src/cpu_map/x86_486.xml
+++ b/src/cpu_map/x86_486.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='486'>
+ <decode host='on' guest='on'/>
<feature name='fpu'/>
<feature name='pse'/>
<feature name='vme'/>
diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
index 4600cacec0..9033d5fcd5 100644
--- a/src/cpu_map/x86_Broadwell-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Broadwell-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='61'/> <!-- 0306d0 -->
<signature family='6' model='71'/> <!-- 040670 -->
<signature family='6' model='79'/> <!-- 0406f0 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
index b3fc0b726a..c044b60e36 100644
--- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Broadwell-noTSX-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='61'/> <!-- 0306d0 -->
<signature family='6' model='71'/> <!-- 040670 -->
<signature family='6' model='79'/> <!-- 0406f0 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
index ad932d0853..637f29ba1c 100644
--- a/src/cpu_map/x86_Broadwell-noTSX.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Broadwell-noTSX'>
+ <decode host='on' guest='on'/>
<signature family='6' model='61'/> <!-- 0306d0 -->
<signature family='6' model='71'/> <!-- 040670 -->
<signature family='6' model='79'/> <!-- 0406f0 -->
diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
index 6de9227322..82939a4509 100644
--- a/src/cpu_map/x86_Broadwell.xml
+++ b/src/cpu_map/x86_Broadwell.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Broadwell'>
+ <decode host='on' guest='on'/>
<signature family='6' model='61'/> <!-- 0306d0 -->
<signature family='6' model='71'/> <!-- 040670 -->
<signature family='6' model='79'/> <!-- 0406f0 -->
diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
index d24415ebce..5adea664e9 100644
--- a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Cascadelake-Server-noTSX'>
+ <decode host='on' guest='on'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Cascadelake-Server.xml
b/src/cpu_map/x86_Cascadelake-Server.xml
index b69ac198b6..d7ec42f57e 100644
--- a/src/cpu_map/x86_Cascadelake-Server.xml
+++ b/src/cpu_map/x86_Cascadelake-Server.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Cascadelake-Server'>
+ <decode host='on' guest='on'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Conroe.xml b/src/cpu_map/x86_Conroe.xml
index 89fe0ad2cf..4cacee6142 100644
--- a/src/cpu_map/x86_Conroe.xml
+++ b/src/cpu_map/x86_Conroe.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Conroe'>
+ <decode host='on' guest='on'/>
<signature family='6' model='15'/> <!-- 0006f0 -->
<signature family='6' model='22'/> <!-- 010660 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Dhyana.xml b/src/cpu_map/x86_Dhyana.xml
index cbc8020a94..689daf8649 100644
--- a/src/cpu_map/x86_Dhyana.xml
+++ b/src/cpu_map/x86_Dhyana.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Dhyana'>
+ <decode host='on' guest='on'/>
<signature family='24' model='0'/> <!-- 900f00 -->
<vendor name='Hygon'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_EPYC-IBPB.xml b/src/cpu_map/x86_EPYC-IBPB.xml
index 283697ebd1..983c5f4445 100644
--- a/src/cpu_map/x86_EPYC-IBPB.xml
+++ b/src/cpu_map/x86_EPYC-IBPB.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='EPYC-IBPB'>
+ <decode host='on' guest='on'/>
<signature family='23' model='1'/> <!-- 800f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_EPYC.xml b/src/cpu_map/x86_EPYC.xml
index f0601392fd..3ebba9f4ed 100644
--- a/src/cpu_map/x86_EPYC.xml
+++ b/src/cpu_map/x86_EPYC.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='EPYC'>
+ <decode host='on' guest='on'/>
<signature family='23' model='1'/> <!-- 800f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBRS.xml
index 4f86db838f..0ffe2bae0d 100644
--- a/src/cpu_map/x86_Haswell-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Haswell-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='60'/> <!-- 0306c0 -->
<signature family='6' model='63'/> <!-- 0306f0 -->
<signature family='6' model='69'/> <!-- 040650 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
index 47318be6d5..75d709c009 100644
--- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Haswell-noTSX-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='60'/> <!-- 0306c0 -->
<signature family='6' model='63'/> <!-- 0306f0 -->
<signature family='6' model='69'/> <!-- 040650 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-noTSX.xml
index efd10c47de..b0a0faa856 100644
--- a/src/cpu_map/x86_Haswell-noTSX.xml
+++ b/src/cpu_map/x86_Haswell-noTSX.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Haswell-noTSX'>
+ <decode host='on' guest='on'/>
<signature family='6' model='60'/> <!-- 0306c0 -->
<signature family='6' model='63'/> <!-- 0306f0 -->
<signature family='6' model='69'/> <!-- 040650 -->
diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml
index ac358d7967..ee16b30f19 100644
--- a/src/cpu_map/x86_Haswell.xml
+++ b/src/cpu_map/x86_Haswell.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Haswell'>
+ <decode host='on' guest='on'/>
<signature family='6' model='60'/> <!-- 0306c0 -->
<signature family='6' model='63'/> <!-- 0306f0 -->
<signature family='6' model='69'/> <!-- 040650 -->
diff --git a/src/cpu_map/x86_Icelake-Client-noTSX.xml
b/src/cpu_map/x86_Icelake-Client-noTSX.xml
index cd51881f40..540732af6f 100644
--- a/src/cpu_map/x86_Icelake-Client-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Client-noTSX.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Icelake-Client-noTSX'>
+ <decode host='on' guest='on'/>
<signature family='6' model='126'/> <!-- 0706e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Icelake-Client.xml b/src/cpu_map/x86_Icelake-Client.xml
index fbd53bbe11..5cf32e91fa 100644
--- a/src/cpu_map/x86_Icelake-Client.xml
+++ b/src/cpu_map/x86_Icelake-Client.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Icelake-Client'>
+ <decode host='on' guest='on'/>
<signature family='6' model='126'/> <!-- 0706e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml
b/src/cpu_map/x86_Icelake-Server-noTSX.xml
index 538c656712..5a53da23c7 100644
--- a/src/cpu_map/x86_Icelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Icelake-Server-noTSX'>
+ <decode host='on' guest='on'/>
<signature family='6' model='134'/> <!-- 080660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Icelake-Server.xml b/src/cpu_map/x86_Icelake-Server.xml
index a565371977..367ade7240 100644
--- a/src/cpu_map/x86_Icelake-Server.xml
+++ b/src/cpu_map/x86_Icelake-Server.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Icelake-Server'>
+ <decode host='on' guest='on'/>
<signature family='6' model='134'/> <!-- 080660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge-IBRS.xml
index e0f2adfa82..430bc3232d 100644
--- a/src/cpu_map/x86_IvyBridge-IBRS.xml
+++ b/src/cpu_map/x86_IvyBridge-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='IvyBridge-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='58'/> <!-- 0306a0 -->
<signature family='6' model='62'/> <!-- 0306e0 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml
index 16213dbc62..eaf5d02e82 100644
--- a/src/cpu_map/x86_IvyBridge.xml
+++ b/src/cpu_map/x86_IvyBridge.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='IvyBridge'>
+ <decode host='on' guest='on'/>
<signature family='6' model='58'/> <!-- 0306a0 -->
<signature family='6' model='62'/> <!-- 0306e0 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBRS.xml
index 8cc19eff03..00d0d2fe51 100644
--- a/src/cpu_map/x86_Nehalem-IBRS.xml
+++ b/src/cpu_map/x86_Nehalem-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Nehalem-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='26'/> <!-- 0106a0 -->
<signature family='6' model='30'/> <!-- 0106e0 -->
<signature family='6' model='31'/> <!-- 0106f0 -->
diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml
index 530e5e8a0d..9968001fe7 100644
--- a/src/cpu_map/x86_Nehalem.xml
+++ b/src/cpu_map/x86_Nehalem.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Nehalem'>
+ <decode host='on' guest='on'/>
<signature family='6' model='26'/> <!-- 0106a0 -->
<signature family='6' model='30'/> <!-- 0106e0 -->
<signature family='6' model='31'/> <!-- 0106f0 -->
diff --git a/src/cpu_map/x86_Opteron_G1.xml b/src/cpu_map/x86_Opteron_G1.xml
index 73cf1de71e..57648ca93f 100644
--- a/src/cpu_map/x86_Opteron_G1.xml
+++ b/src/cpu_map/x86_Opteron_G1.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Opteron_G1'>
+ <decode host='on' guest='on'/>
<signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Opteron_G2.xml b/src/cpu_map/x86_Opteron_G2.xml
index 342105730e..db961b0067 100644
--- a/src/cpu_map/x86_Opteron_G2.xml
+++ b/src/cpu_map/x86_Opteron_G2.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Opteron_G2'>
+ <decode host='on' guest='on'/>
<signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='apic'/>
diff --git a/src/cpu_map/x86_Opteron_G3.xml b/src/cpu_map/x86_Opteron_G3.xml
index 7fbf8ac9e9..dab59d4f82 100644
--- a/src/cpu_map/x86_Opteron_G3.xml
+++ b/src/cpu_map/x86_Opteron_G3.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Opteron_G3'>
+ <decode host='on' guest='on'/>
<signature family='15' model='6'/> <!-- 100e60 -->
<vendor name='AMD'/>
<feature name='abm'/>
diff --git a/src/cpu_map/x86_Opteron_G4.xml b/src/cpu_map/x86_Opteron_G4.xml
index 463b3676a0..a7fc8d5828 100644
--- a/src/cpu_map/x86_Opteron_G4.xml
+++ b/src/cpu_map/x86_Opteron_G4.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Opteron_G4'>
+ <decode host='on' guest='on'/>
<signature family='21' model='1'/> <!-- 600f10 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Opteron_G5.xml b/src/cpu_map/x86_Opteron_G5.xml
index 0f8fe32c87..ff775bdcef 100644
--- a/src/cpu_map/x86_Opteron_G5.xml
+++ b/src/cpu_map/x86_Opteron_G5.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Opteron_G5'>
+ <decode host='on' guest='on'/>
<signature family='21' model='2'/> <!-- 600f20 -->
<vendor name='AMD'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Penryn.xml b/src/cpu_map/x86_Penryn.xml
index 279bb05570..29d4cd635b 100644
--- a/src/cpu_map/x86_Penryn.xml
+++ b/src/cpu_map/x86_Penryn.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Penryn'>
+ <decode host='on' guest='on'/>
<signature family='6' model='23'/> <!-- 010670 -->
<signature family='6' model='29'/> <!-- 0106d0 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBridge-IBRS.xml
index 7d1342ec6f..fbdb4f2bf6 100644
--- a/src/cpu_map/x86_SandyBridge-IBRS.xml
+++ b/src/cpu_map/x86_SandyBridge-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='SandyBridge-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='42'/> <!-- 0206a0 -->
<signature family='6' model='45'/> <!-- 0206d0 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.xml
index 48e4ac8082..7c85ed42df 100644
--- a/src/cpu_map/x86_SandyBridge.xml
+++ b/src/cpu_map/x86_SandyBridge.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='SandyBridge'>
+ <decode host='on' guest='on'/>
<signature family='6' model='42'/> <!-- 0206a0 -->
<signature family='6' model='45'/> <!-- 0206d0 -->
<vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-IBRS.xml
index 4440313fc4..5709e7c2f9 100644
--- a/src/cpu_map/x86_Skylake-Client-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Client-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='94'/> <!-- 0506e0 -->
<signature family='6' model='78'/> <!-- 0406e0 -->
<!-- These are Kaby Lake and Coffee Lake successors to Skylake,
diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
index 3d2976692f..0c2f1e6ac4 100644
--- a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Client-noTSX-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='94'/> <!-- 0506e0 -->
<signature family='6' model='78'/> <!-- 0406e0 -->
<!-- These are Kaby Lake and Coffee Lake successors to Skylake,
diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-Client.xml
index 1053fa4a04..14cd57e176 100644
--- a/src/cpu_map/x86_Skylake-Client.xml
+++ b/src/cpu_map/x86_Skylake-Client.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Client'>
+ <decode host='on' guest='on'/>
<signature family='6' model='94'/> <!-- 0506e0 -->
<signature family='6' model='78'/> <!-- 0406e0 -->
<!-- These are Kaby Lake and Coffee Lake successors to Skylake,
diff --git a/src/cpu_map/x86_Skylake-Server-IBRS.xml
b/src/cpu_map/x86_Skylake-Server-IBRS.xml
index 71179f9f74..bd6b6457ad 100644
--- a/src/cpu_map/x86_Skylake-Server-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Server-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
index 455a072119..91a206f575 100644
--- a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Server-noTSX-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Skylake-Server.xml b/src/cpu_map/x86_Skylake-Server.xml
index 2da69e0dfc..f96875a85f 100644
--- a/src/cpu_map/x86_Skylake-Server.xml
+++ b/src/cpu_map/x86_Skylake-Server.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Skylake-Server'>
+ <decode host='on' guest='on'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Westmere-IBRS.xml b/src/cpu_map/x86_Westmere-IBRS.xml
index 3baf56f47a..c7898f0c22 100644
--- a/src/cpu_map/x86_Westmere-IBRS.xml
+++ b/src/cpu_map/x86_Westmere-IBRS.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Westmere-IBRS'>
+ <decode host='on' guest='on'/>
<signature family='6' model='44'/> <!-- 0206c0 -->
<vendor name='Intel'/>
<feature name='aes'/>
diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml
index 95c1d690c8..16e4ad6c30 100644
--- a/src/cpu_map/x86_Westmere.xml
+++ b/src/cpu_map/x86_Westmere.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='Westmere'>
+ <decode host='on' guest='on'/>
<signature family='6' model='44'/> <!-- 0206c0 -->
<signature family='6' model='47'/> <!-- 0206f0 -->
<signature family='6' model='37'/> <!-- 020650 -->
diff --git a/src/cpu_map/x86_athlon.xml b/src/cpu_map/x86_athlon.xml
index 0d44508e20..81c43c81e8 100644
--- a/src/cpu_map/x86_athlon.xml
+++ b/src/cpu_map/x86_athlon.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='athlon'>
+ <decode host='on' guest='on'/>
<vendor name='AMD'/>
<feature name='3dnow'/>
<feature name='3dnowext'/>
diff --git a/src/cpu_map/x86_core2duo.xml b/src/cpu_map/x86_core2duo.xml
index 3c9a148f3c..412039fe55 100644
--- a/src/cpu_map/x86_core2duo.xml
+++ b/src/cpu_map/x86_core2duo.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='core2duo'>
+ <decode host='on' guest='on'/>
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_coreduo.xml b/src/cpu_map/x86_coreduo.xml
index 676e846920..e2fda9a1d4 100644
--- a/src/cpu_map/x86_coreduo.xml
+++ b/src/cpu_map/x86_coreduo.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='coreduo'>
+ <decode host='on' guest='on'/>
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_cpu64-rhel5.xml b/src/cpu_map/x86_cpu64-rhel5.xml
index 670a92f274..be6bcdb7a6 100644
--- a/src/cpu_map/x86_cpu64-rhel5.xml
+++ b/src/cpu_map/x86_cpu64-rhel5.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='cpu64-rhel5'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='clflush'/>
<feature name='cmov'/>
diff --git a/src/cpu_map/x86_cpu64-rhel6.xml b/src/cpu_map/x86_cpu64-rhel6.xml
index 3cae0f00c2..c62b1b5575 100644
--- a/src/cpu_map/x86_cpu64-rhel6.xml
+++ b/src/cpu_map/x86_cpu64-rhel6.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='cpu64-rhel6'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='clflush'/>
<feature name='cmov'/>
diff --git a/src/cpu_map/x86_kvm32.xml b/src/cpu_map/x86_kvm32.xml
index 5f08a5e7fc..9dd96d5b56 100644
--- a/src/cpu_map/x86_kvm32.xml
+++ b/src/cpu_map/x86_kvm32.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='kvm32'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='clflush'/>
<feature name='cmov'/>
diff --git a/src/cpu_map/x86_kvm64.xml b/src/cpu_map/x86_kvm64.xml
index 80b24e2a49..185af06f78 100644
--- a/src/cpu_map/x86_kvm64.xml
+++ b/src/cpu_map/x86_kvm64.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='kvm64'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='clflush'/>
<feature name='cmov'/>
diff --git a/src/cpu_map/x86_n270.xml b/src/cpu_map/x86_n270.xml
index cb359d968e..5507d2ea3b 100644
--- a/src/cpu_map/x86_n270.xml
+++ b/src/cpu_map/x86_n270.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='n270'>
+ <decode host='on' guest='on'/>
<vendor name='Intel'/>
<feature name='apic'/>
<feature name='clflush'/>
diff --git a/src/cpu_map/x86_pentium.xml b/src/cpu_map/x86_pentium.xml
index d44c1399b0..f0a8982115 100644
--- a/src/cpu_map/x86_pentium.xml
+++ b/src/cpu_map/x86_pentium.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='pentium'>
+ <decode host='on' guest='on'/>
<feature name='cx8'/>
<feature name='de'/>
<feature name='fpu'/>
diff --git a/src/cpu_map/x86_pentium2.xml b/src/cpu_map/x86_pentium2.xml
index 0d772bad2f..aeba082297 100644
--- a/src/cpu_map/x86_pentium2.xml
+++ b/src/cpu_map/x86_pentium2.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='pentium2'>
+ <decode host='on' guest='on'/>
<feature name='cmov'/>
<feature name='cx8'/>
<feature name='de'/>
diff --git a/src/cpu_map/x86_pentium3.xml b/src/cpu_map/x86_pentium3.xml
index 24eb227c28..ab85d2967f 100644
--- a/src/cpu_map/x86_pentium3.xml
+++ b/src/cpu_map/x86_pentium3.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='pentium3'>
+ <decode host='on' guest='on'/>
<feature name='cmov'/>
<feature name='cx8'/>
<feature name='de'/>
diff --git a/src/cpu_map/x86_pentiumpro.xml b/src/cpu_map/x86_pentiumpro.xml
index 9f7a610a87..b6e061187c 100644
--- a/src/cpu_map/x86_pentiumpro.xml
+++ b/src/cpu_map/x86_pentiumpro.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='pentiumpro'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='cmov'/>
<feature name='cx8'/>
diff --git a/src/cpu_map/x86_phenom.xml b/src/cpu_map/x86_phenom.xml
index 71f004057b..f0f8ece57a 100644
--- a/src/cpu_map/x86_phenom.xml
+++ b/src/cpu_map/x86_phenom.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='phenom'>
+ <decode host='on' guest='on'/>
<vendor name='AMD'/>
<feature name='3dnow'/>
<feature name='3dnowext'/>
diff --git a/src/cpu_map/x86_qemu32.xml b/src/cpu_map/x86_qemu32.xml
index 3c9cdec981..f3fb1959be 100644
--- a/src/cpu_map/x86_qemu32.xml
+++ b/src/cpu_map/x86_qemu32.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='qemu32'>
+ <decode host='on' guest='on'/>
<feature name='apic'/>
<feature name='cmov'/>
<feature name='cx8'/>
diff --git a/src/cpu_map/x86_qemu64.xml b/src/cpu_map/x86_qemu64.xml
index a8e8dfe58d..0fe207a2b4 100644
--- a/src/cpu_map/x86_qemu64.xml
+++ b/src/cpu_map/x86_qemu64.xml
@@ -1,5 +1,6 @@
<cpus>
<model name='qemu64'>
+ <decode host='on' guest='on'/>
<!-- These are supported only by TCG. KVM supports them only if the
host does. So we leave them out:
--
2.25.1
5:13 a.m.
New subject: [libvirt PATCH 3/4] cpu_x86: Honor CPU models' <decode> element
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu/cpu_x86.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c
index 366337ef57..ce15bb0454 100644
--- a/src/cpu/cpu_x86.c
+++ b/src/cpu/cpu_x86.c
@@ -2044,10 +2044,23 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current,
virCPUx86ModelPtr candidate,
virCPUDefPtr cpuCandidate,
uint32_t signature,
- const char *preferred,
- bool checkPolicy)
+ const char *preferred)
{
- if (checkPolicy) {
+ if (cpuCandidate->type == VIR_CPU_TYPE_HOST &&
+ !candidate->decodeHost) {
+ VIR_DEBUG("%s is not supposed to be used for host CPU definition",
+ cpuCandidate->model);
+ return 0;
+ }
+
+ if (cpuCandidate->type == VIR_CPU_TYPE_GUEST &&
+ !candidate->decodeGuest) {
+ VIR_DEBUG("%s is not supposed to be used for guest CPU definition",
+ cpuCandidate->model);
+ return 0;
+ }
+
+ if (cpuCandidate->type == VIR_CPU_TYPE_HOST) {
size_t i;
for (i = 0; i < cpuCandidate->nfeatures; i++) {
if (cpuCandidate->features[i].policy == VIR_CPU_FEATURE_DISABLE)
@@ -2209,8 +2222,7 @@ x86Decode(virCPUDefPtr cpu,
if ((rc = x86DecodeUseCandidate(model, cpuModel,
candidate, cpuCandidate,
- signature, preferred,
- cpu->type == VIR_CPU_TYPE_HOST))) {
+ signature, preferred))) {
virCPUDefFree(cpuModel);
cpuModel = cpuCandidate;
model = candidate;
--
2.25.1
5:13 a.m.
New subject: [libvirt PATCH 4/4] cpu_map: Don't use new noTSX models for host-model CPUs
Host-model CPU definitions (and domain capabilities) will use the
original CPU models (without noTSX in their name) and explicitly disable
hle and rtm features. This way domains with host-model CPUs will be
migratable even to older versions of libvirt which do not support the
noTSX model variants.
The new models will be advertised in host capabilities and they may
be used explicitly with custom CPUs.
Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com>
---
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 2 +-
src/cpu_map/x86_Icelake-Client-noTSX.xml | 2 +-
src/cpu_map/x86_Icelake-Server-noTSX.xml | 2 +-
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 2 +-
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 2 +-
tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml | 4 +++-
tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml | 4 +++-
7 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
index 5adea664e9..459174a30d 100644
--- a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Cascadelake-Server-noTSX'>
- <decode host='on' guest='on'/>
+ <decode host='on' guest='off'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Icelake-Client-noTSX.xml
b/src/cpu_map/x86_Icelake-Client-noTSX.xml
index 540732af6f..65e648ae21 100644
--- a/src/cpu_map/x86_Icelake-Client-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Client-noTSX.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Icelake-Client-noTSX'>
- <decode host='on' guest='on'/>
+ <decode host='on' guest='off'/>
<signature family='6' model='126'/> <!-- 0706e0 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml
b/src/cpu_map/x86_Icelake-Server-noTSX.xml
index 5a53da23c7..2fd6906406 100644
--- a/src/cpu_map/x86_Icelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Icelake-Server-noTSX'>
- <decode host='on' guest='on'/>
+ <decode host='on' guest='off'/>
<signature family='6' model='134'/> <!-- 080660 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
index 0c2f1e6ac4..ffba34502a 100644
--- a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Client-noTSX-IBRS'>
- <decode host='on' guest='on'/>
+ <decode host='on' guest='off'/>
<signature family='6' model='94'/> <!-- 0506e0 -->
<signature family='6' model='78'/> <!-- 0406e0 -->
<!-- These are Kaby Lake and Coffee Lake successors to Skylake,
diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
index 91a206f575..c2b7de40e8 100644
--- a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
@@ -1,6 +1,6 @@
<cpus>
<model name='Skylake-Server-noTSX-IBRS'>
- <decode host='on' guest='on'/>
+ <decode host='on' guest='off'/>
<signature family='6' model='85'/> <!-- 050654 -->
<vendor name='Intel'/>
<feature name='3dnowprefetch'/>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
index e03c4a06ba..92404e4d03 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-guest.xml
@@ -1,5 +1,5 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-noTSX-IBRS</model>
+ <model fallback='forbid'>Skylake-Client-IBRS</model>
<vendor>Intel</vendor>
<feature policy='require' name='ds'/>
<feature policy='require' name='acpi'/>
@@ -26,4 +26,6 @@
<feature policy='require' name='pdpe1gb'/>
<feature policy='require' name='invtsc'/>
<feature policy='require' name='skip-l1dfl-vmentry'/>
+ <feature policy='disable' name='hle'/>
+ <feature policy='disable' name='rtm'/>
</cpu>
diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
index 3d8e6775bf..645c0934c2 100644
--- a/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
+++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8550U-json.xml
@@ -1,5 +1,5 @@
<cpu mode='custom' match='exact'>
- <model fallback='forbid'>Skylake-Client-noTSX-IBRS</model>
+ <model fallback='forbid'>Skylake-Client-IBRS</model>
<vendor>Intel</vendor>
<feature policy='require' name='ss'/>
<feature policy='require' name='vmx'/>
@@ -14,4 +14,6 @@
<feature policy='require' name='xsaves'/>
<feature policy='require' name='pdpe1gb'/>
<feature policy='require' name='skip-l1dfl-vmentry'/>
+ <feature policy='disable' name='hle'/>
+ <feature policy='disable' name='rtm'/>
</cpu>
--
2.25.1
9:57 a.m.
On Wed, Mar 18, 2020 at 11:13 AM Jiri Denemark <jdenemar(a)redhat.com> wrote:
Christian Ehrhardt (1):
cpu_map: Add more -noTSX x86 CPU models
Jiri Denemark (3):
cpu_map: Add <decode> element to x86 CPU model definitions
cpu_x86: Honor CPU models' <decode> element
cpu_map: Don't use new noTSX models for host-model CPUs
Hi,
for the Ubuntu bug that got all of this started I applied your patches,
built in a PPA and tested the case.
#1 virsh capabilities
Before:
Broadwell-noTSX-IBRS + 33 features
After:
Skylake-Client-noTSX-IBRS +24 features
=> good
#2 virsh domcapabilities
Before:
Skylake-Client-IBRS + 16 features
After:
Skylake-Client-IBRS + 16 features (unchanged as intended for compatibility)
=> good
#3 usable models
Before:
only older types
After:
now added "Skylake-Client-noTSX-IBRS" which is a more modern IBRS type than
the others I had
=> good
#4 use the new types
My system isn't new enough to get the others added, but that is fine as a
test.
Also the type "Skylake-Server-noTSX-IBRS" worked, auto-disabling the avx
features my chip is missing.
I started a guest with such a type through libvirt and it looks as expected:
-cpu Skylake-Client-noTSX-IBRS
=> good
#5 and finally the adapted tests still ran fien at build time.
Thank you Jiri for the changes, please feel free to add my:
Reviewed-by: Christian Ehrhardt <christian.ehrhardt(a)canonical.com>
Tested-by: Christian Ehrhardt <christian.ehrhardt(a)canonical.com>
src/cpu/cpu_x86.c | 65 ++++++++++++-
src/cpu_map/Makefile.inc.am | 5 +
src/cpu_map/index.xml | 5 +
src/cpu_map/x86_486.xml | 1 +
src/cpu_map/x86_Broadwell-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Broadwell-noTSX.xml | 1 +
src/cpu_map/x86_Broadwell.xml | 1 +
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 79 ++++++++++++++++
src/cpu_map/x86_Cascadelake-Server.xml | 1 +
src/cpu_map/x86_Conroe.xml | 1 +
src/cpu_map/x86_Dhyana.xml | 1 +
src/cpu_map/x86_EPYC-IBPB.xml | 1 +
src/cpu_map/x86_EPYC.xml | 1 +
src/cpu_map/x86_Haswell-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 1 +
src/cpu_map/x86_Haswell-noTSX.xml | 1 +
src/cpu_map/x86_Haswell.xml | 1 +
src/cpu_map/x86_Icelake-Client-noTSX.xml | 82 +++++++++++++++++
src/cpu_map/x86_Icelake-Client.xml | 1 +
src/cpu_map/x86_Icelake-Server-noTSX.xml | 91 +++++++++++++++++++
src/cpu_map/x86_Icelake-Server.xml | 1 +
src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
src/cpu_map/x86_IvyBridge.xml | 1 +
src/cpu_map/x86_Nehalem-IBRS.xml | 1 +
src/cpu_map/x86_Nehalem.xml | 1 +
src/cpu_map/x86_Opteron_G1.xml | 1 +
src/cpu_map/x86_Opteron_G2.xml | 1 +
src/cpu_map/x86_Opteron_G3.xml | 1 +
src/cpu_map/x86_Opteron_G4.xml | 1 +
src/cpu_map/x86_Opteron_G5.xml | 1 +
src/cpu_map/x86_Penryn.xml | 1 +
src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
src/cpu_map/x86_SandyBridge.xml | 1 +
src/cpu_map/x86_Skylake-Client-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 74 +++++++++++++++
src/cpu_map/x86_Skylake-Client.xml | 1 +
src/cpu_map/x86_Skylake-Server-IBRS.xml | 1 +
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 76 ++++++++++++++++
src/cpu_map/x86_Skylake-Server.xml | 1 +
src/cpu_map/x86_Westmere-IBRS.xml | 1 +
src/cpu_map/x86_Westmere.xml | 1 +
src/cpu_map/x86_athlon.xml | 1 +
src/cpu_map/x86_core2duo.xml | 1 +
src/cpu_map/x86_coreduo.xml | 1 +
src/cpu_map/x86_cpu64-rhel5.xml | 1 +
src/cpu_map/x86_cpu64-rhel6.xml | 1 +
src/cpu_map/x86_kvm32.xml | 1 +
src/cpu_map/x86_kvm64.xml | 1 +
src/cpu_map/x86_n270.xml | 1 +
src/cpu_map/x86_pentium.xml | 1 +
src/cpu_map/x86_pentium2.xml | 1 +
src/cpu_map/x86_pentium3.xml | 1 +
src/cpu_map/x86_pentiumpro.xml | 1 +
src/cpu_map/x86_phenom.xml | 1 +
src/cpu_map/x86_qemu32.xml | 1 +
src/cpu_map/x86_qemu64.xml | 1 +
.../x86_64-cpuid-Core-i7-8550U-host.xml | 11 +--
.../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 5 +
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 5 +
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 5 +
.../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 5 +
.../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 5 +
tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 5 +
64 files changed, 552 insertions(+), 15 deletions(-)
create mode 100644 src/cpu_map/x86_Cascadelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Client-noTSX.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-noTSX.xml
create mode 100644 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
create mode 100644 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
--
2.25.1
--
Christian Ehrhardt
Staff Engineer, Ubuntu Server
Canonical Ltd
1705
days inactive
1710
days old
5 comments
2 participants
participants (2)
-
Christian Ehrhardt -
Jiri Denemark