4:37 p.m.
On 2/15/24 3:23 PM, Jim Fehlig wrote:
Hi Jonathon,
I don't have any expertise in this area of libvirt, but I have been
experimenting with your patches and fairly recent snp-enabled
kernel+ovmf+qemu referenced from AMD's AMDSEV repo
https://github.com/AMDESE/AMDSEV/blob/snp-latest/stable-commits
With your patches and 2 preliminarly SNP patches on top, I'm able to
start SNP guests using
<cpu>
<model>EPYC-v4</model>
</cpu>
A git branch containing the work on fairly recent libvirt.git master is
here
https://gitlab.com/jfehlig/libvirt/-/tree/cpu-versions-plus-snp?ref_type=...
I can take a closer look at the series when I return next week, but so
far functional testing has been positive.
Regards,
Jim
Thanks for the feedback.
FYI, I do also have a WIP sev-snp branch for libvirt in my personal
repository as well. I haven't posted any patches here yet because it's
still in progress and because it builds on some qemu stuff that's not
upstream yet (both the AMD repo and some coconut-svsm stuff). But it's
here if you're interested:
https://gitlab.com/jjongsma/libvirt/-/tree/sev-snp?ref_type=heads
Jonathon
On 12/15/23 15:11, Jonathon Jongsma wrote:
> For SEV-SNP support we will need to be able to specify versioned CPU
> models
> that are not yet available in libvirt. Rather than just adding a
> versioned CPU
> or two that would satisfy that immediate need, I decided to try to add
> versioned CPUs in a more standard way. This series generates CPU
> definitions
> for all cpu versions that are defined in upstream qemu (at least for
> recent Intel and AMD CPUs).
>
> libvirt already provides a select subset of these versions as
> configurable CPU
> models. But we only include the ones that have defined aliases in
> qemu, such as
> EPYC-IBPB. After this patchset, all verisioned cpu models supported by
> qemu
> will be available in libvirt.
>
> In addition to adding these new versioned models, based on feedback
> from Daniel
> Berrange, I've also translated all CPU model aliases to a specific
> version when
> specifying a CPU model to qemu. This means that we will no longer
> specify e.g.
> '-cpu EPYC' to qemu, but will rather specify '-cpu EPYC-v1'
>
> Changes in v3:
> - handle unversioned aliases
>
> Changes in v2:
> - don't make any changes to existing CPU models
> - drop concept of aliases from libvirt and only provide new
> versioned models
> that aren't already available via their qemu alias.
>
> Jonathon Jongsma (12):
> cpu_map: update script to handle versioned CPUs
> cpu_map: add canonical names to existing CPU models
> cpu: parse the canonical name from the cpu model
> qemu: use canonical name for CPU models
> cpu_map: Add versioned EPYC CPUs
> cpu_map: Add versioned Intel Skylake CPUs
> cpu_map: Add versioned Intel Cascadelake CPUs
> cpu_map: Add versioned Intel Icelake CPUs
> cpu_map: Add versioned Intel Cooperlake CPUs
> cpu_map: Add versioned Intel Snowridge CPUs
> cpu_map: Add versioned Intel SapphireRapids CPUs
> cpu_map: Add versioned Dhyana CPUs
>
> src/conf/cpu_conf.c | 3 +
> src/conf/cpu_conf.h | 1 +
> src/cpu/cpu_x86.c | 24 ++++
> src/cpu_map/index.xml | 22 +++
> src/cpu_map/meson.build | 22 +++
> src/cpu_map/sync_qemu_models_i386.py | 42 ++++--
> src/cpu_map/x86_Broadwell-IBRS.xml | 1 +
> src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 1 +
> src/cpu_map/x86_Broadwell-noTSX.xml | 1 +
> src/cpu_map/x86_Broadwell.xml | 1 +
> src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 1 +
> src/cpu_map/x86_Cascadelake-Server-v2.xml | 93 +++++++++++++
> src/cpu_map/x86_Cascadelake-Server-v4.xml | 91 +++++++++++++
> src/cpu_map/x86_Cascadelake-Server-v5.xml | 92 +++++++++++++
> src/cpu_map/x86_Cascadelake-Server.xml | 1 +
> src/cpu_map/x86_Cooperlake-v2.xml | 98 ++++++++++++++
> src/cpu_map/x86_Cooperlake.xml | 1 +
> src/cpu_map/x86_Dhyana-v2.xml | 81 ++++++++++++
> src/cpu_map/x86_Dhyana.xml | 1 +
> src/cpu_map/x86_EPYC-IBPB.xml | 1 +
> src/cpu_map/x86_EPYC-Milan-v2.xml | 108 +++++++++++++++
> src/cpu_map/x86_EPYC-Milan.xml | 1 +
> src/cpu_map/x86_EPYC-Rome-v2.xml | 93 +++++++++++++
> src/cpu_map/x86_EPYC-Rome-v3.xml | 95 +++++++++++++
> src/cpu_map/x86_EPYC-Rome-v4.xml | 94 +++++++++++++
> src/cpu_map/x86_EPYC-Rome.xml | 1 +
> src/cpu_map/x86_EPYC-v3.xml | 87 ++++++++++++
> src/cpu_map/x86_EPYC-v4.xml | 88 ++++++++++++
> src/cpu_map/x86_EPYC.xml | 1 +
> src/cpu_map/x86_Haswell-IBRS.xml | 1 +
> src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 1 +
> src/cpu_map/x86_Haswell-noTSX.xml | 1 +
> src/cpu_map/x86_Haswell.xml | 1 +
> src/cpu_map/x86_Icelake-Server-noTSX.xml | 1 +
> src/cpu_map/x86_Icelake-Server-v3.xml | 103 +++++++++++++++
> src/cpu_map/x86_Icelake-Server-v4.xml | 108 +++++++++++++++
> src/cpu_map/x86_Icelake-Server-v5.xml | 109 +++++++++++++++
> src/cpu_map/x86_Icelake-Server-v6.xml | 109 +++++++++++++++
> src/cpu_map/x86_Icelake-Server.xml | 1 +
> src/cpu_map/x86_IvyBridge-IBRS.xml | 1 +
> src/cpu_map/x86_IvyBridge.xml | 1 +
> src/cpu_map/x86_Nehalem-IBRS.xml | 1 +
> src/cpu_map/x86_Nehalem.xml | 1 +
> src/cpu_map/x86_SandyBridge-IBRS.xml | 1 +
> src/cpu_map/x86_SandyBridge.xml | 1 +
> src/cpu_map/x86_SapphireRapids-v2.xml | 125 ++++++++++++++++++
> src/cpu_map/x86_SapphireRapids.xml | 1 +
> src/cpu_map/x86_Skylake-Client-IBRS.xml | 1 +
> src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 +
> src/cpu_map/x86_Skylake-Client-v4.xml | 77 +++++++++++
> src/cpu_map/x86_Skylake-Client.xml | 1 +
> src/cpu_map/x86_Skylake-Server-IBRS.xml | 1 +
> src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 +
> src/cpu_map/x86_Skylake-Server-v4.xml | 83 ++++++++++++
> src/cpu_map/x86_Skylake-Server-v5.xml | 85 ++++++++++++
> src/cpu_map/x86_Skylake-Server.xml | 1 +
> src/cpu_map/x86_Snowridge-v2.xml | 78 +++++++++++
> src/cpu_map/x86_Snowridge-v3.xml | 80 +++++++++++
> src/cpu_map/x86_Snowridge-v4.xml | 78 +++++++++++
> src/cpu_map/x86_Snowridge.xml | 1 +
> src/cpu_map/x86_Westmere-IBRS.xml | 1 +
> src/cpu_map/x86_Westmere.xml | 1 +
> src/qemu/qemu_command.c | 5 +-
> .../x86_64-cpuid-Atom-P5362-guest.xml | 3 +-
> .../x86_64-cpuid-Atom-P5362-json.xml | 3 +-
> .../x86_64-cpuid-Cooperlake-host.xml | 3 +-
> .../x86_64-cpuid-EPYC-7502-32-Core-host.xml | 5 +-
> .../x86_64-cpuid-EPYC-7601-32-Core-guest.xml | 9 +-
> ...6_64-cpuid-EPYC-7601-32-Core-ibpb-host.xml | 8 +-
> ..._64-cpuid-Hygon-C86-7185-32-core-guest.xml | 5 +-
> ...6_64-cpuid-Hygon-C86-7185-32-core-host.xml | 5 +-
> ...6_64-cpuid-Hygon-C86-7185-32-core-json.xml | 6 +-
> ...4-cpuid-Ryzen-7-1800X-Eight-Core-guest.xml | 9 +-
> .../x86_64-cpuid-Xeon-Platinum-8268-guest.xml | 9 +-
> .../x86_64-cpuid-Xeon-Platinum-8268-host.xml | 9 +-
> .../x86_64-cpuid-Xeon-Platinum-9242-guest.xml | 9 +-
> .../x86_64-cpuid-Xeon-Platinum-9242-host.xml | 9 +-
> .../x86_64-cpuid-Xeon-Platinum-9242-json.xml | 9 +-
> ..._64-cpuid-baseline-Cascadelake+Icelake.xml | 9 +-
> ...-cpuid-baseline-Cooperlake+Cascadelake.xml | 9 +-
> ...6_64-cpuid-baseline-Cooperlake+Icelake.xml | 9 +-
> .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 2 +
> .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 2 +
> tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 2 +
> .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 4 +
> .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 4 +
> tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 4 +
> .../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 7 +
> .../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 7 +
> tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 7 +
> .../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 7 +
> .../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 7 +
> tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 7 +
> .../domaincapsdata/qemu_6.0.0-q35.x86_64.xml | 8 ++
> .../domaincapsdata/qemu_6.0.0-tcg.x86_64.xml | 8 ++
> tests/domaincapsdata/qemu_6.0.0.x86_64.xml | 8 ++
> .../domaincapsdata/qemu_6.1.0-q35.x86_64.xml | 15 +++
> .../domaincapsdata/qemu_6.1.0-tcg.x86_64.xml | 15 +++
> tests/domaincapsdata/qemu_6.1.0.x86_64.xml | 15 +++
> .../domaincapsdata/qemu_6.2.0-q35.x86_64.xml | 16 +++
> .../domaincapsdata/qemu_6.2.0-tcg.x86_64.xml | 16 +++
> tests/domaincapsdata/qemu_6.2.0.x86_64.xml | 16 +++
> .../domaincapsdata/qemu_7.0.0-q35.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_7.0.0-tcg.x86_64.xml | 17 +++
> tests/domaincapsdata/qemu_7.0.0.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_7.1.0-q35.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_7.1.0-tcg.x86_64.xml | 17 +++
> tests/domaincapsdata/qemu_7.1.0.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_7.2.0-q35.x86_64.xml | 17 +++
> .../qemu_7.2.0-tcg.x86_64+hvf.xml | 17 +++
> .../domaincapsdata/qemu_7.2.0-tcg.x86_64.xml | 17 +++
> tests/domaincapsdata/qemu_7.2.0.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_8.0.0-q35.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_8.0.0-tcg.x86_64.xml | 17 +++
> tests/domaincapsdata/qemu_8.0.0.x86_64.xml | 17 +++
> .../domaincapsdata/qemu_8.1.0-q35.x86_64.xml | 27 +++-
> .../domaincapsdata/qemu_8.1.0-tcg.x86_64.xml | 22 +++
> tests/domaincapsdata/qemu_8.1.0.x86_64.xml | 27 +++-
> .../domaincapsdata/qemu_8.2.0-q35.x86_64.xml | 27 +++-
> .../domaincapsdata/qemu_8.2.0-tcg.x86_64.xml | 22 +++
> tests/domaincapsdata/qemu_8.2.0.x86_64.xml | 27 +++-
> .../cpu-Haswell-noTSX.x86_64-latest.args | 2 +-
> .../cpu-Haswell.x86_64-latest.args | 2 +-
> .../cpu-Haswell2.x86_64-latest.args | 2 +-
> .../cpu-Haswell3.x86_64-latest.args | 2 +-
> ...-Icelake-Server-pconfig.x86_64-latest.args | 2 +-
> .../cpu-cache-disable3.x86_64-latest.args | 2 +-
> ...u-check-default-partial.x86_64-latest.args | 2 +-
> .../cpu-fallback.x86_64-5.2.0.args | 2 +-
> .../cpu-fallback.x86_64-8.0.0.args | 2 +-
> .../cpu-host-model-cmt.x86_64-latest.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-4.2.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-5.0.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-5.1.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-5.2.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-6.0.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-6.1.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-6.2.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-7.0.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-7.1.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-7.2.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-8.0.0.args | 2 +-
> ...-host-model-fallback-kvm.x86_64-8.1.0.args | 2 +-
> ...host-model-fallback-kvm.x86_64-latest.args | 2 +-
> ...-host-model-fallback-tcg.x86_64-7.2.0.args | 2 +-
> ...-host-model-fallback-tcg.x86_64-8.0.0.args | 2 +-
> ...-host-model-fallback-tcg.x86_64-8.1.0.args | 2 +-
> ...host-model-fallback-tcg.x86_64-latest.args | 2 +-
> .../cpu-host-model-kvm.x86_64-4.2.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-5.0.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-5.1.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-5.2.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-6.0.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-6.1.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-6.2.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-7.0.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-7.1.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-7.2.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-8.0.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-8.1.0.args | 2 +-
> .../cpu-host-model-kvm.x86_64-latest.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-4.2.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-5.0.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-5.1.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-5.2.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-6.0.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-6.1.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-6.2.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-7.0.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-7.1.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-7.2.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-8.0.0.args | 2 +-
> ...ost-model-nofallback-kvm.x86_64-8.1.0.args | 2 +-
> ...st-model-nofallback-kvm.x86_64-latest.args | 2 +-
> ...ost-model-nofallback-tcg.x86_64-7.2.0.args | 2 +-
> ...ost-model-nofallback-tcg.x86_64-8.0.0.args | 2 +-
> ...ost-model-nofallback-tcg.x86_64-8.1.0.args | 2 +-
> ...st-model-nofallback-tcg.x86_64-latest.args | 2 +-
> .../cpu-host-model-tcg.x86_64-7.2.0.args | 2 +-
> .../cpu-host-model-tcg.x86_64-8.0.0.args | 2 +-
> .../cpu-host-model-tcg.x86_64-8.1.0.args | 2 +-
> .../cpu-host-model-tcg.x86_64-latest.args | 2 +-
> .../cpu-host-model-vendor.x86_64-latest.args | 2 +-
> .../cpu-minimum1.x86_64-latest.args | 2 +-
> .../cpu-minimum2.x86_64-latest.args | 2 +-
> .../cpu-nofallback.x86_64-8.0.0.args | 2 +-
> .../cpu-phys-bits-emulate2.x86_64-latest.args | 2 +-
> .../cpu-strict1.x86_64-latest.args | 2 +-
> .../cpu-translation.x86_64-latest.args | 2 +-
> .../cpu-tsc-frequency.x86_64-latest.args | 2 +-
> 190 files changed, 2837 insertions(+), 187 deletions(-)
> create mode 100644 src/cpu_map/x86_Cascadelake-Server-v2.xml
> create mode 100644 src/cpu_map/x86_Cascadelake-Server-v4.xml
> create mode 100644 src/cpu_map/x86_Cascadelake-Server-v5.xml
> create mode 100644 src/cpu_map/x86_Cooperlake-v2.xml
> create mode 100644 src/cpu_map/x86_Dhyana-v2.xml
> create mode 100644 src/cpu_map/x86_EPYC-Milan-v2.xml
> create mode 100644 src/cpu_map/x86_EPYC-Rome-v2.xml
> create mode 100644 src/cpu_map/x86_EPYC-Rome-v3.xml
> create mode 100644 src/cpu_map/x86_EPYC-Rome-v4.xml
> create mode 100644 src/cpu_map/x86_EPYC-v3.xml
> create mode 100644 src/cpu_map/x86_EPYC-v4.xml
> create mode 100644 src/cpu_map/x86_Icelake-Server-v3.xml
> create mode 100644 src/cpu_map/x86_Icelake-Server-v4.xml
> create mode 100644 src/cpu_map/x86_Icelake-Server-v5.xml
> create mode 100644 src/cpu_map/x86_Icelake-Server-v6.xml
> create mode 100644 src/cpu_map/x86_SapphireRapids-v2.xml
> create mode 100644 src/cpu_map/x86_Skylake-Client-v4.xml
> create mode 100644 src/cpu_map/x86_Skylake-Server-v4.xml
> create mode 100644 src/cpu_map/x86_Skylake-Server-v5.xml
> create mode 100644 src/cpu_map/x86_Snowridge-v2.xml
> create mode 100644 src/cpu_map/x86_Snowridge-v3.xml
> create mode 100644 src/cpu_map/x86_Snowridge-v4.xml
>