[libvirt] [PATCH 1/2] Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell"

This reverts commit 13704e4c455770d500d6b87b117e32f0d01252c9. With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So instead of making the CPU model results confusing by making it depend on the machine-type, keep HLE and RTM on the existing Haswell and Broadwell CPU models. The plan is to introduce "Haswell-noTSX" and "Broadwell-noTSX" CPU models later, for people who have CPUs that don't have TSX feature available. Signed-off-by: Eduardo Habkost <ehabkost(a)redhat.com&gt; --- hw/i386/pc_piix.c | 4 ---- hw/i386/pc_q35.c | 4 ---- target-i386/cpu.c | 9 +++++---- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8eab4ba..0e32afa 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -331,10 +331,6 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); - x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); - x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index c0f21fe..5a7b11c 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -310,10 +310,6 @@ static void pc_compat_2_2(MachineState *machine) x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); - x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); - x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX, - CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0); } static void pc_compat_2_1(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ed7e5d5..de3cdce 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1099,8 +1099,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | - CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .xlevel = 0x8000000A, @@ -1133,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | - CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | - CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, -- 2.1.0