[PATCH v2 09/16] hw/ssi/xilinx_spips: Make device endianness configurable
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-Daudé <philmd(a)linaro.org>
---
include/hw/ssi/xilinx_spips.h | 1 +
hw/arm/xilinx_zynq.c | 1 +
hw/ssi/xilinx_spips.c | 46 ++++++++++++++++++++++++++---------
3 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index 7a754bf67a..451c3758b3 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -101,6 +101,7 @@ typedef struct XilinxQSPIPS XilinxQSPIPS;
struct XlnxZynqMPQSPIPS {
XilinxQSPIPS parent_obj;
+ bool little_endian_model;
StreamSink *dma;
int gqspi_irqline;
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index fde4d946b7..bcc0022c17 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -142,6 +142,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq
irq,
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
+ qdev_prop_set_bit(dev, "little-endian", true);
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index aeb462c3ce..5c6f0dd079 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -1251,17 +1251,32 @@ static MemTxResult lqspi_write(void *opaque, hwaddr offset,
uint64_t value,
return MEMTX_ERROR;
}
-static const MemoryRegionOps lqspi_ops = {
- .read_with_attrs = lqspi_read,
- .write_with_attrs = lqspi_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .impl = {
- .min_access_size = 4,
- .max_access_size = 4,
+static const MemoryRegionOps lqspi_ops[2] = {
+ {
+ .read_with_attrs = lqspi_read,
+ .write_with_attrs = lqspi_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ },
},
- .valid = {
- .min_access_size = 1,
- .max_access_size = 4
+ {
+ .read_with_attrs = lqspi_read,
+ .write_with_attrs = lqspi_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
}
};
@@ -1325,8 +1340,9 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
s->num_txrx_bytes = 4;
xilinx_spips_realize(dev, errp);
- memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s,
"lqspi",
- (1 << LQSPI_ADDRESS_BITS) * 2);
+ memory_region_init_io(&s->mmlqspi, OBJECT(s),
+ &lqspi_ops[s->little_endian_model],
+ s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2);
sysbus_init_mmio(sbd, &s->mmlqspi);
q->lqspi_cached_addr = ~0ULL;
@@ -1432,12 +1448,18 @@ static Property xilinx_spips_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static Property xilinx_qspips_properties[] = {
+ DEFINE_PROP_BOOL("little-endian", XilinxQSPIPS, little_endian_model,
true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
dc->realize = xilinx_qspips_realize;
+ device_class_set_props(dc, xilinx_qspips_properties);
xsc->reg_ops = &qspips_ops;
xsc->reg_size = XLNX_SPIPS_R_MAX * 4;
xsc->rx_fifo_size = RXFF_A_Q;
--
2.45.2