On 11/20/20 5:48 PM, Peter Maydell wrote:
On Fri, 20 Nov 2020 at 15:21, Philippe Mathieu-Daudé
<f4bug(a)amsat.org> wrote:
>
> Document the following Raspberry Pi models:
>
> - raspi0 Raspberry Pi Zero (revision 1.2)
> - raspi1ap Raspberry Pi A+ (revision 1.1)
> - raspi2b Raspberry Pi 2B (revision 1.1)
> - raspi3ap Raspberry Pi 3A+ (revision 1.0)
> - raspi3b Raspberry Pi 3B (revision 1.2)
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
> ---
> docs/system/arm/raspi.rst | 44 ++++++++++++++++++++++++++++++++++++++
> docs/system/target-arm.rst | 1 +
> 2 files changed, 45 insertions(+)
> create mode 100644 docs/system/arm/raspi.rst
>
> diff --git a/docs/system/arm/raspi.rst b/docs/system/arm/raspi.rst
> new file mode 100644
> index 00000000000..b19284e4481
> --- /dev/null
> +++ b/docs/system/arm/raspi.rst
> @@ -0,0 +1,44 @@
> +Raspberry Pi boards (``raspi0``, ``raspi1ap``, ``raspi2b``, ``raspi3ap``,
``raspi3b``)
>
+======================================================================================
> +
> +
> +QEMU provides models the following Raspberry Pi boards:
"models of"
> +
> +``raspi0`` and ``raspi1ap``
> + ARM1176JZF-S core, 512 MiB of RAM
> +``raspi2b``
> + Cortex-A7 (4 cores), 1 GiB of RAM
> +``raspi3ap``
> + Cortex-A53 (4 cores), 512 MiB of RAM
> +``raspi3b``
> + Cortex-A53 (4 cores), 1 GiB of RAM
> +
> +
> +Implemented devices
> +-------------------
> +
> + * ARM1176JZF-S, Cortex-A7 or Cortex-A53 CPU
> + * Interrupt controller
> + * DMA controller
> + * Clock and reset controller (CPRMAN)
> + * System Timer
> + * GPIO controller
> + * Serial ports (BCM2835 AUX - 16550 based - and PL011)
> + * Random Number Generator (RNG)
> + * Frame Buffer
> + * USB host (USBH)
> + * GPIO controller
> + * SD/MMC host controller
> + * SoC thermal sensor
> + * USB2 host controller (DWC2 and MPHI)
> + * MailBox controller (MBOX)
> + * VideoCore firmware (property)
> +
> +
> +Missing devices
> +---------------
> +
> + * Peripheral SPI controller (SPI)
> + * Analog to Digital Converter (ADC)
> + * Pulse Width Modulation (PWM)
> + * Security features
"Security features" is a bit vague; could we be more precise?
I used Nuvoton as template. I'll remove :)
Otherwise
Reviewed-by: Peter Maydell <peter.maydell(a)linaro.org>
thanks
-- PMM