<feature name='dca'> <!-- CPUID_EXT_DCA --> <cpuid function='0x00000001' ecx='0x00040000'/> </feature> + <feature name='sse4.1'> <!-- CPUID_EXT_SSE41 --> + <cpuid function='0x00000001' ecx='0x00080000'/> + </feature> + <feature name='sse4.2'> <!-- CPUID_EXT_SSE42 --> + <cpuid function='0x00000001' ecx='0x00100000'/> + </feature> <feature name='x2apic'> <!-- CPUID_EXT_X2APIC --> <cpuid function='0x00000001' ecx='0x00200000'/> </feature>
I had to do a quick google check to validate that these look correct (http://www.powerbasic.com/support/pbforums/showthread.php?p=342233 was the first link I found that had some code to confirm my suspicions, but it isn't the most canonical source). Adding a URL to your commit message of an official Intel or AMD site on SSE would clinch it, but don't let it hold up your commit if you can't quickly find one.
I did that to match qemu's definition and relied on them having it right (although I double checked their definitions in the past). The official Intel document resides at http://www.intel.com/support/processors/sb/cs-009861.htm but I don't think it deserves its place in git log :-)
ACK.
Thanks, pushed. Jirka