[libvirt] [PATCH 11/17] cpu: Add Haswell-noTSX-IBRS CPU model

This is a variant of Haswell-noTSX with indirect branch prediction protection. The only difference between Haswell-noTSX and Haswell-noTSX-IBRS is the added "spec-ctrl" feature. The Haswell-noTSX-IBRS model in QEMU is a bit different since Haswell-noTSX got several additional features since we added it in cpu_map.xml: arat, abm, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: Jiri Denemark <jdenemar(a)redhat.com&gt; --- src/cpu/cpu_map.xml | 54 ++++++++++++++++++++++ .../x86_64-cpuid-Xeon-E5-2609-v3-guest.xml | 3 +- .../x86_64-cpuid-Xeon-E5-2609-v3-host.xml | 3 +- .../x86_64-cpuid-Xeon-E5-2609-v3-json.xml | 3 +- 4 files changed, 57 insertions(+), 6 deletions(-) diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml index 0e88d2dd9d..6d4b31c507 100644 --- a/src/cpu/cpu_map.xml +++ b/src/cpu/cpu_map.xml @@ -1226,6 +1226,60 @@ <feature name='xsave'/> </model> + <model name='Haswell-noTSX-IBRS'> + <signature family='6' model='60'/> + <vendor name='Intel'/> + <feature name='aes'/> + <feature name='apic'/> + <feature name='avx'/> + <feature name='avx2'/> + <feature name='bmi1'/> + <feature name='bmi2'/> + <feature name='clflush'/> + <feature name='cmov'/> + <feature name='cx16'/> + <feature name='cx8'/> + <feature name='de'/> + <feature name='erms'/> + <feature name='fma'/> + <feature name='fpu'/> + <feature name='fsgsbase'/> + <feature name='fxsr'/> + <feature name='invpcid'/> + <feature name='lahf_lm'/> + <feature name='lm'/> + <feature name='mca'/> + <feature name='mce'/> + <feature name='mmx'/> + <feature name='movbe'/> + <feature name='msr'/> + <feature name='mtrr'/> + <feature name='nx'/> + <feature name='pae'/> + <feature name='pat'/> + <feature name='pcid'/> + <feature name='pclmuldq'/> + <feature name='pge'/> + <feature name='pni'/> + <feature name='popcnt'/> + <feature name='pse'/> + <feature name='pse36'/> + <feature name='rdtscp'/> + <feature name='sep'/> + <feature name='smep'/> + <feature name='spec-ctrl'/> + <feature name='sse'/> + <feature name='sse2'/> + <feature name='sse4.1'/> + <feature name='sse4.2'/> + <feature name='ssse3'/> + <feature name='syscall'/> + <feature name='tsc'/> + <feature name='tsc-deadline'/> + <feature name='x2apic'/> + <feature name='xsave'/> + </model> + <model name='Haswell'> <signature family='6' model='60'/> <vendor name='Intel'/> diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-guest.xml index 923efead4a..a66c7a5644 100644 --- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-guest.xml +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-guest.xml @@ -1,5 +1,5 @@ <cpu mode='custom' match='exact'> - <model fallback='forbid'>Haswell-noTSX</model> + <model fallback='forbid'>Haswell-noTSX-IBRS</model> <vendor>Intel</vendor> <feature policy='require' name='vme'/> <feature policy='require' name='ds'/> @@ -24,7 +24,6 @@ <feature policy='require' name='arat'/> <feature policy='require' name='tsc_adjust'/> <feature policy='require' name='cmt'/> - <feature policy='require' name='spec-ctrl'/> <feature policy='require' name='xsaveopt'/> <feature policy='require' name='pdpe1gb'/> <feature policy='require' name='abm'/> diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-host.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-host.xml index 96fee7a46d..624d71db20 100644 --- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-host.xml +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-host.xml @@ -1,6 +1,6 @@ <cpu> <arch>x86_64</arch> - <model>Haswell-noTSX</model> + <model>Haswell-noTSX-IBRS</model> <vendor>Intel</vendor> <feature name='vme'/> <feature name='ds'/> @@ -25,7 +25,6 @@ <feature name='arat'/> <feature name='tsc_adjust'/> <feature name='cmt'/> - <feature name='spec-ctrl'/> <feature name='xsaveopt'/> <feature name='pdpe1gb'/> <feature name='abm'/> diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-json.xml index 42e971f675..20e24c387d 100644 --- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-json.xml +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2609-v3-json.xml @@ -1,5 +1,5 @@ <cpu mode='custom' match='exact'> - <model fallback='forbid'>Haswell-noTSX</model> + <model fallback='forbid'>Haswell-noTSX-IBRS</model> <vendor>Intel</vendor> <feature policy='require' name='vme'/> <feature policy='require' name='ss'/> @@ -8,7 +8,6 @@ <feature policy='require' name='hypervisor'/> <feature policy='require' name='arat'/> <feature policy='require' name='tsc_adjust'/> - <feature policy='require' name='spec-ctrl'/> <feature policy='require' name='xsaveopt'/> <feature policy='require' name='pdpe1gb'/> <feature policy='require' name='abm'/> -- 2.15.1