Re: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. Add kvm_riscv.h to place riscv specific interface. In addition, PLIC is created without M-mode PLIC contexts when KVM is enabled. Signed-off-by: Yifei Jiang <jiangyifei(a)huawei.com&gt; Signed-off-by: Mingwang Li <limingwang(a)huawei.com&gt; Reviewed-by: Alistair Francis <alistair.francis(a)wdc.com&gt; --- hw/intc/sifive_plic.c | 21 +++++++--- hw/riscv/boot.c | 16 +++++++- hw/riscv/virt.c | 83 ++++++++++++++++++++++++++++------------ include/hw/riscv/boot.h | 1 + target/riscv/cpu.c | 8 ++++ target/riscv/cpu.h | 3 ++ target/riscv/kvm-stub.c | 25 ++++++++++++ target/riscv/kvm.c | 14 +++++++ target/riscv/kvm_riscv.h | 24 ++++++++++++ target/riscv/meson.build | 2 +- 10 files changed, 164 insertions(+), 33 deletions(-) create mode 100644 target/riscv/kvm-stub.c create mode 100644 target/riscv/kvm_riscv.h diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 877e76877c..58c16881cb 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -30,6 +30,7 @@ #include "target/riscv/cpu.h" #include "migration/vmstate.h" #include "hw/irq.h" +#include "sysemu/kvm.h" #define RISCV_DEBUG_PLIC 0 @@ -533,6 +534,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, { DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); int i; + SiFivePLICState *plic; + int s_count = 0, m_count = 0; assert(enable_stride == (enable_stride & -enable_stride)); assert(context_stride == (context_stride & -context_stride)); @@ -550,13 +553,19 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); - for (i = 0; i < num_harts; i++) { - CPUState *cpu = qemu_get_cpu(hartid_base + i); + plic = SIFIVE_PLIC(dev); + for (i = 0; i < plic->num_addrs; i++) { + CPUState *cpu = qemu_get_cpu(plic->addr_config[i].hartid); - qdev_connect_gpio_out(dev, i, - qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); - qdev_connect_gpio_out(dev, num_harts + i, - qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); + if (plic->addr_config[i].mode == PLICMode_S) { + qdev_connect_gpio_out(dev, s_count++, + qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); + } + + if (plic->addr_config[i].mode == PLICMode_M) { + qdev_connect_gpio_out(dev, num_harts + m_count++, + qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); + } }