4:21 p.m.
This is not necessarily intended as a finished proposal, but as a discussion
starter. I mentioned in an email last week that for SEV-SNP support we will
need to be able to specify versioned CPU models that are not yet supported by
libvirt. Rather than just adding a versioned CPU or two that would satisfy my
immediate need, I decided to try to add versioned CPUs in a standard way. This
involves adding the concept of an 'alias' for a CPU model in libvirt. Qemu
already has the concept of a CPU alias for a versioned CPU. In fact, libvirt
already provides a select subset of these as configurable CPU models (e.g.
'EPYC-IBPB'). After this patchset, these aliased CPU versions would be
configurable by either their versioned name ('EPYC-v2') or their alias
('EPYC-IBPB'). And it would also provide non-aliased CPU versions as options
within libvirt ('EPYC-v4').
Assuming that we want to offer all versioned CPUs like this, there are two
approaches to naming. I chose to maintain the existing names (e.g. EPYC-IBPB)
as the primary name where available, and use the versioned name (EPYC-v2) as
the alias. However, some CPU models don't have an alias, so their versioned
name would be their primary name. So we have the following set of 'EPYC' CPU
models:
- EPYC (alias = EPYC-v1)
- EPYC-IBPB (alias = EPYC-v2)
- EPYC-v3 (no alias)
- EPYC-v4 (no alias)
An alternative approach is something more like:
- EPYC-v1 (alias = EPYC)
- EPYC-v2 (alias = EPYC-IBPB)
- EPYC-v3 (no alias)
- EPYC-v4 (no alias)
The naming of the second set is more consistent, but it could result in slight
changes to behavior. For example, any call to cpuDecode() that returned
EPYC-IBPB in the past might now return EPYC-v2. These two CPUs are just two
different names for the same model, so I'm not sure it would result in any
issues. But in this patch series I went with the first approach since it
maintained stability and resulted in less churn in the test output.
Note also that there are a couple of patches that update existing CPU models by
re-running this script against the current qemu source code. For example, the
patch "cpu_map: Update EPYC cpu definitions from qemu" results in some minor
changes to the existing EPYC CPUs by adding a couple of feature flags. In
theory, it seems like a good idea for our libvirt models to match how the model
is defined in qemu, but I admit that I don't have a great understanding of
whether this will result in undesirable side-effects. I'm hoping those of you
with deeper knowledge will tell me why this is or is not a good idea. In the
same vein, I've included the last patch of the series showing what it would
look like if we regenerated all of the other CPU definitions from the qemu
source code.
Jonathon Jongsma (19):
cpu_map: update script to generate versioned CPUs
cpu: handle aliases in CPU definitions
cpu_map: Update EPYC cpu definitions from qemu
cpu_map: Add versioned EPYC CPUs
cpu_map: Add versioned Intel Nehalem CPUs
cpu_map: Add versioned Intel Westmere CPUs
cpu_map: Add versioned Intel SandyBridge CPUs
cpu_map: Add versioned Intel IvyBridge CPUs
cpu_map: Add versioned Intel Haswell CPUs
cpu_map: Add versioned Intel Broadwell CPUs
cpu_map: Add versioned Intel Skylake CPUs
cpu_map: Add versioned Intel Cascadelake CPUs
cpu_map: Add versioned Intel Icelake CPUs
cpu_map: Add versioned Intel Cooperlake CPUs
cpu_map: Add versioned Intel Snowridge CPUs
cpu_map: Add versioned Intel SapphireRapids CPUs
cpu_map: Add versioned Dhyana CPUs
cpu: advertise CPU aliases
NOMERGE: RFC: regenerate all cpu definitions
src/cpu/cpu_x86.c | 88 ++++++++----
src/cpu_map/index.xml | 22 +++
src/cpu_map/meson.build | 22 +++
src/cpu_map/sync_qemu_models_i386.py | 44 ++++--
src/cpu_map/x86_Broadwell-IBRS.xml | 19 ++-
src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 19 ++-
src/cpu_map/x86_Broadwell-noTSX.xml | 19 ++-
src/cpu_map/x86_Broadwell.xml | 18 ++-
src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 19 ++-
src/cpu_map/x86_Cascadelake-Server-v2.xml | 93 +++++++++++++
src/cpu_map/x86_Cascadelake-Server-v4.xml | 91 +++++++++++++
src/cpu_map/x86_Cascadelake-Server-v5.xml | 92 +++++++++++++
src/cpu_map/x86_Cascadelake-Server.xml | 11 +-
src/cpu_map/x86_Cooperlake-v2.xml | 98 ++++++++++++++
src/cpu_map/x86_Cooperlake.xml | 9 +-
src/cpu_map/x86_Dhyana-v2.xml | 81 ++++++++++++
src/cpu_map/x86_Dhyana.xml | 13 +-
src/cpu_map/x86_EPYC-Genoa.xml | 7 +
src/cpu_map/x86_EPYC-IBPB.xml | 14 +-
src/cpu_map/x86_EPYC-Milan-v2.xml | 108 +++++++++++++++
src/cpu_map/x86_EPYC-Milan.xml | 8 ++
src/cpu_map/x86_EPYC-Rome-v2.xml | 93 +++++++++++++
src/cpu_map/x86_EPYC-Rome-v3.xml | 95 +++++++++++++
src/cpu_map/x86_EPYC-Rome-v4.xml | 94 +++++++++++++
src/cpu_map/x86_EPYC-Rome.xml | 9 ++
src/cpu_map/x86_EPYC-v3.xml | 87 ++++++++++++
src/cpu_map/x86_EPYC-v4.xml | 88 ++++++++++++
src/cpu_map/x86_EPYC.xml | 13 +-
src/cpu_map/x86_Haswell-IBRS.xml | 20 ++-
src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 20 ++-
src/cpu_map/x86_Haswell-noTSX.xml | 20 ++-
src/cpu_map/x86_Haswell.xml | 18 ++-
src/cpu_map/x86_Icelake-Server-noTSX.xml | 14 +-
src/cpu_map/x86_Icelake-Server-v3.xml | 103 +++++++++++++++
src/cpu_map/x86_Icelake-Server-v4.xml | 108 +++++++++++++++
src/cpu_map/x86_Icelake-Server-v5.xml | 109 +++++++++++++++
src/cpu_map/x86_Icelake-Server-v6.xml | 109 +++++++++++++++
src/cpu_map/x86_Icelake-Server.xml | 11 +-
src/cpu_map/x86_IvyBridge-IBRS.xml | 13 +-
src/cpu_map/x86_IvyBridge.xml | 12 +-
src/cpu_map/x86_Nehalem-IBRS.xml | 14 +-
src/cpu_map/x86_Nehalem.xml | 13 +-
src/cpu_map/x86_SandyBridge-IBRS.xml | 14 +-
src/cpu_map/x86_SandyBridge.xml | 13 +-
src/cpu_map/x86_SapphireRapids-v2.xml | 125 ++++++++++++++++++
src/cpu_map/x86_SapphireRapids.xml | 7 +
src/cpu_map/x86_Skylake-Client-IBRS.xml | 16 ++-
src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 18 +--
src/cpu_map/x86_Skylake-Client-v4.xml | 77 +++++++++++
src/cpu_map/x86_Skylake-Client.xml | 15 ++-
src/cpu_map/x86_Skylake-Server-IBRS.xml | 12 +-
src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 14 +-
src/cpu_map/x86_Skylake-Server-v4.xml | 83 ++++++++++++
src/cpu_map/x86_Skylake-Server-v5.xml | 85 ++++++++++++
src/cpu_map/x86_Skylake-Server.xml | 12 +-
src/cpu_map/x86_Snowridge-v2.xml | 78 +++++++++++
src/cpu_map/x86_Snowridge-v3.xml | 80 +++++++++++
src/cpu_map/x86_Snowridge-v4.xml | 78 +++++++++++
src/cpu_map/x86_Snowridge.xml | 10 +-
src/cpu_map/x86_Westmere-IBRS.xml | 13 +-
src/cpu_map/x86_Westmere.xml | 14 +-
...4-baseline-Westmere+Nehalem-migratable.xml | 4 +-
...86_64-baseline-Westmere+Nehalem-result.xml | 4 +-
.../x86_64-baseline-features-expanded.xml | 1 +
.../x86_64-baseline-features-result.xml | 2 -
.../x86_64-baseline-simple-expanded.xml | 3 +
.../x86_64-cpuid-Atom-P5362-guest.xml | 3 +-
.../x86_64-cpuid-Atom-P5362-host.xml | 3 -
.../x86_64-cpuid-Atom-P5362-json.xml | 3 +-
.../x86_64-cpuid-Cooperlake-host.xml | 3 +-
.../x86_64-cpuid-Core-i5-2500-guest.xml | 3 -
.../x86_64-cpuid-Core-i5-2500-host.xml | 3 -
.../x86_64-cpuid-Core-i5-2500-json.xml | 3 -
.../x86_64-cpuid-Core-i5-2540M-guest.xml | 3 -
.../x86_64-cpuid-Core-i5-2540M-host.xml | 3 -
.../x86_64-cpuid-Core-i5-2540M-json.xml | 3 -
.../x86_64-cpuid-Core-i5-4670T-guest.xml | 6 +-
.../x86_64-cpuid-Core-i5-4670T-host.xml | 19 ++-
.../x86_64-cpuid-Core-i5-4670T-json.xml | 6 +-
.../x86_64-cpuid-Core-i5-650-guest.xml | 3 -
.../x86_64-cpuid-Core-i5-650-host.xml | 3 -
.../x86_64-cpuid-Core-i5-650-json.xml | 3 -
.../x86_64-cpuid-Core-i5-6600-guest.xml | 1 +
.../x86_64-cpuid-Core-i5-6600-host.xml | 1 +
.../x86_64-cpuid-Core-i5-6600-json.xml | 1 +
.../x86_64-cpuid-Core-i7-2600-guest.xml | 3 -
.../x86_64-cpuid-Core-i7-2600-host.xml | 3 -
.../x86_64-cpuid-Core-i7-2600-json.xml | 3 -
...6_64-cpuid-Core-i7-2600-xsaveopt-guest.xml | 2 -
...86_64-cpuid-Core-i7-2600-xsaveopt-host.xml | 9 +-
...86_64-cpuid-Core-i7-2600-xsaveopt-json.xml | 2 -
.../x86_64-cpuid-Core-i7-3520M-guest.xml | 2 -
.../x86_64-cpuid-Core-i7-3520M-host.xml | 2 -
.../x86_64-cpuid-Core-i7-3740QM-guest.xml | 2 +-
.../x86_64-cpuid-Core-i7-3740QM-host.xml | 13 +-
.../x86_64-cpuid-Core-i7-3740QM-json.xml | 2 +-
.../x86_64-cpuid-Core-i7-3770-guest.xml | 2 -
.../x86_64-cpuid-Core-i7-3770-host.xml | 2 -
.../x86_64-cpuid-Core-i7-3770-json.xml | 2 +-
.../x86_64-cpuid-Core-i7-4510U-guest.xml | 6 -
.../x86_64-cpuid-Core-i7-4510U-host.xml | 3 -
.../x86_64-cpuid-Core-i7-4510U-json.xml | 6 -
.../x86_64-cpuid-Core-i7-4600U-guest.xml | 6 -
.../x86_64-cpuid-Core-i7-4600U-host.xml | 6 -
.../x86_64-cpuid-Core-i7-4600U-json.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-arat-guest.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-arat-host.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-arat-json.xml | 6 +-
.../x86_64-cpuid-Core-i7-5600U-guest.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-host.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-ibrs-guest.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-ibrs-host.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-ibrs-json.xml | 6 -
.../x86_64-cpuid-Core-i7-5600U-json.xml | 6 -
.../x86_64-cpuid-Core-i7-7600U-guest.xml | 1 +
.../x86_64-cpuid-Core-i7-7600U-host.xml | 1 +
.../x86_64-cpuid-Core-i7-7600U-json.xml | 1 +
.../x86_64-cpuid-Core-i7-7700-guest.xml | 1 +
.../x86_64-cpuid-Core-i7-7700-host.xml | 1 +
.../x86_64-cpuid-Core-i7-7700-json.xml | 1 +
.../x86_64-cpuid-Core-i7-8550U-guest.xml | 5 +-
.../x86_64-cpuid-Core-i7-8550U-host.xml | 4 +-
.../x86_64-cpuid-Core-i7-8550U-json.xml | 5 +-
.../x86_64-cpuid-Core-i7-8700-guest.xml | 1 +
.../x86_64-cpuid-Core-i7-8700-host.xml | 1 +
.../x86_64-cpuid-Core-i7-8700-json.xml | 1 +
.../x86_64-cpuid-EPYC-7502-32-Core-guest.xml | 1 -
.../x86_64-cpuid-EPYC-7502-32-Core-host.xml | 5 +-
.../x86_64-cpuid-EPYC-7502-32-Core-json.xml | 1 -
.../x86_64-cpuid-EPYC-7601-32-Core-guest.xml | 9 +-
.../x86_64-cpuid-EPYC-7601-32-Core-host.xml | 2 -
..._64-cpuid-EPYC-7601-32-Core-ibpb-guest.xml | 2 -
...6_64-cpuid-EPYC-7601-32-Core-ibpb-host.xml | 8 +-
...6_64-cpuid-EPYC-7601-32-Core-ibpb-json.xml | 3 -
.../x86_64-cpuid-EPYC-7601-32-Core-json.xml | 3 -
..._64-cpuid-Hygon-C86-7185-32-core-guest.xml | 5 +-
...6_64-cpuid-Hygon-C86-7185-32-core-host.xml | 5 +-
...6_64-cpuid-Hygon-C86-7185-32-core-json.xml | 3 -
.../x86_64-cpuid-Ice-Lake-Server-guest.xml | 1 +
.../x86_64-cpuid-Ice-Lake-Server-host.xml | 1 +
.../x86_64-cpuid-Ice-Lake-Server-json.xml | 2 +-
.../x86_64-cpuid-Pentium-P6100-guest.xml | 10 +-
...4-cpuid-Ryzen-7-1800X-Eight-Core-guest.xml | 9 +-
...64-cpuid-Ryzen-7-1800X-Eight-Core-host.xml | 2 -
...64-cpuid-Ryzen-7-1800X-Eight-Core-json.xml | 3 -
...6_64-cpuid-Ryzen-9-3900X-12-Core-guest.xml | 1 -
...86_64-cpuid-Ryzen-9-3900X-12-Core-host.xml | 1 -
...86_64-cpuid-Ryzen-9-3900X-12-Core-json.xml | 1 -
.../x86_64-cpuid-Xeon-E3-1225-v5-guest.xml | 1 +
.../x86_64-cpuid-Xeon-E3-1225-v5-host.xml | 1 +
.../x86_64-cpuid-Xeon-E3-1225-v5-json.xml | 1 +
.../x86_64-cpuid-Xeon-E3-1245-v5-guest.xml | 1 +
.../x86_64-cpuid-Xeon-E3-1245-v5-host.xml | 1 +
.../x86_64-cpuid-Xeon-E3-1245-v5-json.xml | 1 +
.../x86_64-cpuid-Xeon-E5-2609-v3-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2609-v3-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2609-v3-json.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2623-v4-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2623-v4-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2623-v4-json.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2630-v3-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2630-v3-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2630-v3-json.xml | 6 +-
.../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2630-v4-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2650-guest.xml | 3 -
.../x86_64-cpuid-Xeon-E5-2650-host.xml | 3 -
.../x86_64-cpuid-Xeon-E5-2650-json.xml | 3 -
.../x86_64-cpuid-Xeon-E5-2650-v3-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2650-v3-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2650-v3-json.xml | 6 +-
.../x86_64-cpuid-Xeon-E5-2650-v4-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2650-v4-host.xml | 6 -
.../x86_64-cpuid-Xeon-E5-2650-v4-json.xml | 6 -
.../x86_64-cpuid-Xeon-E7-4820-guest.xml | 3 -
.../x86_64-cpuid-Xeon-E7-4820-host.xml | 3 -
.../x86_64-cpuid-Xeon-E7-4820-json.xml | 4 +-
.../x86_64-cpuid-Xeon-E7-4830-guest.xml | 3 -
.../x86_64-cpuid-Xeon-E7-4830-host.xml | 3 -
.../x86_64-cpuid-Xeon-E7-4830-json.xml | 3 -
.../x86_64-cpuid-Xeon-E7-8890-v3-guest.xml | 6 -
.../x86_64-cpuid-Xeon-E7-8890-v3-host.xml | 6 -
.../x86_64-cpuid-Xeon-E7-8890-v3-json.xml | 6 -
.../x86_64-cpuid-Xeon-E7540-guest.xml | 1 -
.../x86_64-cpuid-Xeon-E7540-host.xml | 1 -
.../x86_64-cpuid-Xeon-E7540-json.xml | 1 -
.../x86_64-cpuid-Xeon-Gold-5115-guest.xml | 2 +-
.../x86_64-cpuid-Xeon-Gold-5115-host.xml | 2 +-
.../x86_64-cpuid-Xeon-Gold-5115-json.xml | 2 +
.../x86_64-cpuid-Xeon-Gold-6130-guest.xml | 2 +-
.../x86_64-cpuid-Xeon-Gold-6130-host.xml | 2 +-
.../x86_64-cpuid-Xeon-Gold-6130-json.xml | 2 +-
.../x86_64-cpuid-Xeon-Gold-6148-guest.xml | 3 +-
.../x86_64-cpuid-Xeon-Gold-6148-host.xml | 3 +-
.../x86_64-cpuid-Xeon-Gold-6148-json.xml | 3 +-
.../x86_64-cpuid-Xeon-Platinum-8268-guest.xml | 9 +-
.../x86_64-cpuid-Xeon-Platinum-8268-host.xml | 9 +-
.../x86_64-cpuid-Xeon-Platinum-8268-json.xml | 2 +-
.../x86_64-cpuid-Xeon-Platinum-9242-guest.xml | 9 +-
.../x86_64-cpuid-Xeon-Platinum-9242-host.xml | 9 +-
.../x86_64-cpuid-Xeon-Platinum-9242-json.xml | 9 +-
.../x86_64-cpuid-Xeon-W3520-guest.xml | 1 -
.../x86_64-cpuid-Xeon-W3520-host.xml | 1 -
.../x86_64-cpuid-Xeon-W3520-json.xml | 1 -
...id-baseline-Broadwell-IBRS+Cascadelake.xml | 6 -
..._64-cpuid-baseline-Cascadelake+Icelake.xml | 9 +-
...puid-baseline-Cascadelake+Skylake-IBRS.xml | 2 +-
..._64-cpuid-baseline-Cascadelake+Skylake.xml | 3 +-
...-cpuid-baseline-Cooperlake+Cascadelake.xml | 9 +-
...6_64-cpuid-baseline-Cooperlake+Icelake.xml | 9 +-
.../x86_64-cpuid-baseline-EPYC+Rome.xml | 3 -
.../x86_64-cpuid-baseline-Haswell+Skylake.xml | 6 -
...-baseline-Haswell-noTSX-IBRS+Broadwell.xml | 6 -
...seline-Haswell-noTSX-IBRS+Skylake-IBRS.xml | 6 -
...id-baseline-Haswell-noTSX-IBRS+Skylake.xml | 6 -
.../x86_64-cpuid-baseline-Ryzen+Rome.xml | 3 -
...4-cpuid-baseline-Skylake-Client+Server.xml | 1 +
.../domaincapsdata/qemu_4.2.0-q35.x86_64.xml | 33 +++++
.../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml | 32 +++++
tests/domaincapsdata/qemu_4.2.0.x86_64.xml | 33 +++++
.../domaincapsdata/qemu_5.0.0-q35.x86_64.xml | 37 ++++++
.../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml | 36 +++++
tests/domaincapsdata/qemu_5.0.0.x86_64.xml | 37 ++++++
.../domaincapsdata/qemu_5.1.0-q35.x86_64.xml | 40 +++++-
.../domaincapsdata/qemu_5.1.0-tcg.x86_64.xml | 39 ++++++
tests/domaincapsdata/qemu_5.1.0.x86_64.xml | 40 +++++-
.../domaincapsdata/qemu_5.2.0-q35.x86_64.xml | 40 +++++-
.../domaincapsdata/qemu_5.2.0-tcg.x86_64.xml | 39 ++++++
tests/domaincapsdata/qemu_5.2.0.x86_64.xml | 40 +++++-
.../domaincapsdata/qemu_6.0.0-q35.x86_64.xml | 42 +++++-
.../domaincapsdata/qemu_6.0.0-tcg.x86_64.xml | 41 ++++++
tests/domaincapsdata/qemu_6.0.0.x86_64.xml | 42 +++++-
.../domaincapsdata/qemu_6.1.0-q35.x86_64.xml | 49 ++++++-
.../domaincapsdata/qemu_6.1.0-tcg.x86_64.xml | 48 +++++++
tests/domaincapsdata/qemu_6.1.0.x86_64.xml | 49 ++++++-
.../domaincapsdata/qemu_6.2.0-q35.x86_64.xml | 50 ++++++-
.../domaincapsdata/qemu_6.2.0-tcg.x86_64.xml | 49 +++++++
tests/domaincapsdata/qemu_6.2.0.x86_64.xml | 50 ++++++-
.../domaincapsdata/qemu_7.0.0-q35.x86_64.xml | 51 ++++++-
.../domaincapsdata/qemu_7.0.0-tcg.x86_64.xml | 50 +++++++
tests/domaincapsdata/qemu_7.0.0.x86_64.xml | 51 ++++++-
.../domaincapsdata/qemu_7.1.0-q35.x86_64.xml | 51 ++++++-
.../domaincapsdata/qemu_7.1.0-tcg.x86_64.xml | 50 +++++++
tests/domaincapsdata/qemu_7.1.0.x86_64.xml | 51 ++++++-
.../domaincapsdata/qemu_7.2.0-q35.x86_64.xml | 51 ++++++-
.../qemu_7.2.0-tcg.x86_64+hvf.xml | 51 ++++++-
.../domaincapsdata/qemu_7.2.0-tcg.x86_64.xml | 51 ++++++-
tests/domaincapsdata/qemu_7.2.0.x86_64.xml | 51 ++++++-
.../domaincapsdata/qemu_8.0.0-q35.x86_64.xml | 52 +++++++-
.../domaincapsdata/qemu_8.0.0-tcg.x86_64.xml | 52 +++++++-
tests/domaincapsdata/qemu_8.0.0.x86_64.xml | 52 +++++++-
.../domaincapsdata/qemu_8.1.0-q35.x86_64.xml | 61 ++++++++-
.../domaincapsdata/qemu_8.1.0-tcg.x86_64.xml | 57 +++++++-
tests/domaincapsdata/qemu_8.1.0.x86_64.xml | 61 ++++++++-
.../domaincapsdata/qemu_8.2.0-q35.x86_64.xml | 61 ++++++++-
.../domaincapsdata/qemu_8.2.0-tcg.x86_64.xml | 57 +++++++-
tests/domaincapsdata/qemu_8.2.0.x86_64.xml | 61 ++++++++-
...-Icelake-Server-pconfig.x86_64-latest.args | 2 +-
.../cpu-fallback.x86_64-5.2.0.args | 2 +-
.../cpu-fallback.x86_64-8.0.0.args | 2 +-
tests/qemuxml2argvdata/cpu-fallback.xml | 1 -
.../cpu-host-model-fallback.x86_64-7.2.0.args | 2 +-
.../cpu-host-model-fallback.x86_64-8.0.0.args | 2 +-
...cpu-host-model-fallback.x86_64-latest.args | 2 +-
...pu-host-model-nofallback.x86_64-7.2.0.args | 2 +-
...pu-host-model-nofallback.x86_64-8.0.0.args | 2 +-
...u-host-model-nofallback.x86_64-latest.args | 2 +-
.../cpu-host-model.x86_64-4.2.0.args | 2 +-
.../cpu-host-model.x86_64-5.0.0.args | 2 +-
.../cpu-host-model.x86_64-5.1.0.args | 2 +-
.../cpu-host-model.x86_64-5.2.0.args | 2 +-
.../cpu-host-model.x86_64-6.0.0.args | 2 +-
.../cpu-host-model.x86_64-6.1.0.args | 2 +-
.../cpu-host-model.x86_64-6.2.0.args | 2 +-
.../cpu-host-model.x86_64-7.0.0.args | 2 +-
.../cpu-host-model.x86_64-7.1.0.args | 2 +-
.../cpu-host-model.x86_64-7.2.0.args | 2 +-
.../cpu-host-model.x86_64-8.0.0.args | 2 +-
.../cpu-host-model.x86_64-latest.args | 2 +-
.../cpu-nofallback.x86_64-8.0.0.args | 2 +-
tests/qemuxml2argvdata/cpu-nofallback.xml | 1 -
282 files changed, 4591 insertions(+), 692 deletions(-)
create mode 100644 src/cpu_map/x86_Cascadelake-Server-v2.xml
create mode 100644 src/cpu_map/x86_Cascadelake-Server-v4.xml
create mode 100644 src/cpu_map/x86_Cascadelake-Server-v5.xml
create mode 100644 src/cpu_map/x86_Cooperlake-v2.xml
create mode 100644 src/cpu_map/x86_Dhyana-v2.xml
create mode 100644 src/cpu_map/x86_EPYC-Milan-v2.xml
create mode 100644 src/cpu_map/x86_EPYC-Rome-v2.xml
create mode 100644 src/cpu_map/x86_EPYC-Rome-v3.xml
create mode 100644 src/cpu_map/x86_EPYC-Rome-v4.xml
create mode 100644 src/cpu_map/x86_EPYC-v3.xml
create mode 100644 src/cpu_map/x86_EPYC-v4.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-v3.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-v4.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-v5.xml
create mode 100644 src/cpu_map/x86_Icelake-Server-v6.xml
create mode 100644 src/cpu_map/x86_SapphireRapids-v2.xml
create mode 100644 src/cpu_map/x86_Skylake-Client-v4.xml
create mode 100644 src/cpu_map/x86_Skylake-Server-v4.xml
create mode 100644 src/cpu_map/x86_Skylake-Server-v5.xml
create mode 100644 src/cpu_map/x86_Snowridge-v2.xml
create mode 100644 src/cpu_map/x86_Snowridge-v3.xml
create mode 100644 src/cpu_map/x86_Snowridge-v4.xml
--
2.41.0