-----Original Message-----
From: Alistair Francis [mailto:alistair23@gmail.com]
Sent: Tuesday, January 11, 2022 7:07 AM
To: Jiangyifei <jiangyifei(a)huawei.com>
Cc: qemu-devel(a)nongnu.org Developers <qemu-devel(a)nongnu.org>; open
list:RISC-V <qemu-riscv(a)nongnu.org>; kvm-riscv(a)lists.infradead.org; open
list:Overall <kvm(a)vger.kernel.org>; libvir-list(a)redhat.com; Anup Patel
<anup(a)brainfault.org>; Palmer Dabbelt <palmer(a)dabbelt.com>; Alistair
Francis <Alistair.Francis(a)wdc.com>; Bin Meng <bin.meng(a)windriver.com>;
Fanliang (EulerOS) <fanliang(a)huawei.com>; Wubin (H)
<wu.wubin(a)huawei.com>; Wanghaibin (D) <wanghaibin.wang(a)huawei.com>;
wanbo (G) <wanbo13(a)huawei.com>; limingwang (A)
<limingwang(a)huawei.com>; Anup Patel <anup.patel(a)wdc.com>
Subject: Re: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
On Mon, Jan 10, 2022 at 11:57 AM Yifei Jiang via <qemu-devel(a)nongnu.org>
wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang <jiangyifei(a)huawei.com>
> Signed-off-by: Mingwang Li <limingwang(a)huawei.com>
> Reviewed-by: Alistair Francis <alistair.francis(a)wdc.com>
> Reviewed-by: Anup Patel <anup.patel(a)wdc.com>
> ---
> target/riscv/kvm.c | 104
> ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 103 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> 6d4df0ef6d..e695b91dc7 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -73,6 +73,14 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env,
uint64_t type, uint64_t idx
> } \
> } while(0)
>
> +#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
> + do { \
> + int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
> + if (ret) { \
> + return ret; \
> + } \
> + } while(0)
This fails checkpatch. I know there is lots of QEMU code like this, but it probably
should be `while (0)` to keep checkpatch happy.
Please run checkpatch on all the patches.
Alistair
OK, it will be modified in the next series.
Yifei