With the current setup, a 10nm Icelake CPU, such as the Intel Xeon Gold 6338, will be incorrectly recognized by libvirt as a 14nm broadwell CPU due to the mpx label. See https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1978064. When adding the removed tag to mpx in the Icelake xml definition, it is then correctly determined. Would there be a better way of going about making this distinction for 10nm Icelake processors?

Thanks,
Lena Voytek

On Tue, Aug 16, 2022 at 1:59 AM Jiri Denemark <jdenemar@redhat.com> wrote:
On Tue, Aug 16, 2022 at 10:01:16 +0200, Peter Krempa wrote:
> On Mon, Aug 15, 2022 at 14:11:49 -0700, Lena Voytek wrote:
> > Intel has removed MPX capabilities from 10nm Icelake CPUs[1], which is
> > reflected by the new models through the line marking mpx as removed.
> >
> > The original Icelake Server models have been left alone to avoid regressions.
> >
> > This adds:
> > -Icelake-Server-noMPX
> > -Icelake-Server-noTSX-noMPX
>
> I didn't find this model in qemu, so this looks like you are inventing a
> new model in libvirt.
>
> While I'm not libvirt's expert on CPUs, but as far as I know libvirt
> does not invent our own CPU model names.
>
> In case of the 'noTSX' versions they were present named in such way in
> qemu. The only reason we keep them is historical, but in qemu such
> naming was already deprecated.
>
> > References:
> >
> >     [1] Memory Protection Extensions support removal
> >         https://www.intel.com/content/www/us/en/support/articles/000059823/processors.html
> >
> > Fixes: https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1978064
> >        https://gitlab.com/libvirt/libvirt/-/issues/304
>
> In this issue I've linked the appropriate qemu commit, but according to
> the commit message it seems that the MPX feature was dropped just in
> certain machine types.
>
> This will most likely mean that libvirt will not be able to delete it
> out of the definition, because we need to be able to preserve
> compatibility and VM ABI.

Right. Also the feature is only removed from 10nm CPUs, while 14nm CPUs
of the same generation still support it.

So what is the actual issue you're trying to fix here? In other words,
what steps did you do and what error or incorrect behavior did you see?

Jirka