Re: [PATCH 13/19] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

On Tue, Nov 5, 2024 at 11:07 PM Philippe Mathieu-Daudé <philmd(a)linaro.org&gt; wrote: Reviewed-by: Alistair Francis <alistair.francis(a)wdc.com&gt; Alistair > --- > target/microblaze/translate.c | 36 +++++++++++++++++------------------ > 1 file changed, 18 insertions(+), 18 deletions(-) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 4beaf69e76a..4c25b1e4383 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -779,13 +779,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) > static bool trans_lhu(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); > } > > static bool trans_lhur(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); > } > > static bool trans_lhuea(DisasContext *dc, arg_typea *arg) > @@ -797,26 +797,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) > return true; > #else > TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); > #endif > } > > static bool trans_lhui(DisasContext *dc, arg_typeb *arg) > { > TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); > - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); > } > > static bool trans_lw(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); > } > > static bool trans_lwr(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); > } > > static bool trans_lwea(DisasContext *dc, arg_typea *arg) > @@ -828,14 +828,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) > return true; > #else > TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); > - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); > #endif > } > > static bool trans_lwi(DisasContext *dc, arg_typeb *arg) > { > TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); > - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); > + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); > } > > static bool trans_lwx(DisasContext *dc, arg_typea *arg) > @@ -845,7 +845,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) > /* lwx does not throw unaligned access errors, so force alignment */ > tcg_gen_andi_tl(addr, addr, ~3); > > - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); > + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); > tcg_gen_mov_tl(cpu_res_addr, addr); > > if (arg->rd) { > @@ -929,13 +929,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) > static bool trans_sh(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); > } > > static bool trans_shr(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); > } > > static bool trans_shea(DisasContext *dc, arg_typea *arg) > @@ -947,26 +947,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) > return true; > #else > TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); > #endif > } > > static bool trans_shi(DisasContext *dc, arg_typeb *arg) > { > TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); > - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); > } > > static bool trans_sw(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); > } > > static bool trans_swr(DisasContext *dc, arg_typea *arg) > { > TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); > } > > static bool trans_swea(DisasContext *dc, arg_typea *arg) > @@ -978,14 +978,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) > return true; > #else > TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); > - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); > #endif > } > > static bool trans_swi(DisasContext *dc, arg_typeb *arg) > { > TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); > - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); > + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); > } > > static bool trans_swx(DisasContext *dc, arg_typea *arg) > @@ -1014,7 +1014,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) > > tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, > reg_for_write(dc, arg->rd), > - dc->mem_index, MO_TEUL); > + dc->mem_index, MO_TE | MO_UL); > > tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); > > -- > 2.45.2 > >