[libvirt] [PATCH 4/7] perf: add cache_l1dwm perf event support

This patch adds support and documentation for a generalized hardware cache event named cache_l1dwm perf event for measuring write misses on level 1 data cache Signed-off-by: Nitesh Konkar <nitkon12(a)linux.vnet.ibm.com&gt; --- docs/formatdomain.html.in | 7 +++++++ docs/news.xml | 4 ++-- docs/schemas/domaincommon.rng | 1 + include/libvirt/libvirt-domain.h | 11 +++++++++++ src/libvirt-domain.c | 3 +++ src/qemu/qemu_driver.c | 1 + src/remote/remote_protocol.x | 2 +- src/util/virperf.c | 8 +++++++- src/util/virperf.h | 1 + tests/genericxml2xmlindata/generic-perf.xml | 1 + tools/virsh.pod | 7 +++++-- 11 files changed, 40 insertions(+), 6 deletions(-) diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in index 4c24ead..d5c2aad 100644 --- a/docs/formatdomain.html.in +++ b/docs/formatdomain.html.in @@ -1940,6 +1940,7 @@ &lt;event name='cache_l1dra' enabled='no'/&gt; &lt;event name='cache_l1drm' enabled='no'/&gt; &lt;event name='cache_l1dwa' enabled='no'/&gt; + &lt;event name='cache_l1dwm' enabled='no'/&gt; &lt;/perf&gt; ... </pre> @@ -2036,6 +2037,12 @@ applications running on the platform</td> <td><code>perf.cache_l1dwa</code></td> </tr> + <tr> + <td><code>cache_l1dwm</code></td> + <td>the count of total write misses for level 1 data cache by + applications running on the platform</td> + <td><code>perf.cache_l1dwm</code></td> + </tr> </table> <h3><a name="elementsDevices">Devices</a></h3> diff --git a/docs/news.xml b/docs/news.xml index 129cbc9..eb2e815 100644 --- a/docs/news.xml +++ b/docs/news.xml @@ -107,8 +107,8 @@ Add support to get the count of branch instructions executed, branch misses, bus cycles, stalled frontend cpu cycles, stalled backend cpu cycles, ref cpu cycles, - cache l1dra, cache l1drm and cache l1dwa by applications - running on the platform. + cache l1dra, cache l1drm, cache l1dwa and cache l1dwm by + applications running on the platform. </description> </change> <change> diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng index 9ad5937..91ad636 100644 --- a/docs/schemas/domaincommon.rng +++ b/docs/schemas/domaincommon.rng @@ -436,6 +436,7 @@ <value>cache_l1dra</value> <value>cache_l1drm</value> <value>cache_l1dwa</value> + <value>cache_l1dwm</value> </choice> </attribute> <attribute name="enabled"> diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h index b02eb49..0d8d731 100644 --- a/include/libvirt/libvirt-domain.h +++ b/include/libvirt/libvirt-domain.h @@ -2221,6 +2221,17 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats); */ # define VIR_PERF_PARAM_CACHE_L1DWA "cache_l1dwa" +/* + * VIR_PERF_PARAM_CACHE_L1DWM: + * + *Macro for typed parameter name that represents cache_l1dwm + *perf event which can be used to measure the count of total + *write misses for level 1 data cache by applications running + *on the platform. It corresponds to the "perf.cache_l1dwm" + *field in the *Stats APIs. + */ +# define VIR_PERF_PARAM_CACHE_L1DWM "cache_l1dwm" + int virDomainGetPerfEvents(virDomainPtr dom, virTypedParameterPtr *params, int *nparams, diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c index 92e8bf1..3a5a776 100644 --- a/src/libvirt-domain.c +++ b/src/libvirt-domain.c @@ -11259,6 +11259,9 @@ virConnectGetDomainCapabilities(virConnectPtr conn, * "perf.cache_l1dwa" - The count of total write accesses for level 1 data * cache as unsigned long long. It is produced by * cache_l1dwa perf event. + * "perf.cache_l1dwm" - The count of total write misses for level 1 data + * cache as unsigned long long. It is produced by + * cache_l1dwm perf event. * * Note that entire stats groups or individual stat fields may be missing from * the output in case they are not supported by the given hypervisor, are not diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c index c2f55d3..205d2d2 100644 --- a/src/qemu/qemu_driver.c +++ b/src/qemu/qemu_driver.c @@ -9880,6 +9880,7 @@ qemuDomainSetPerfEvents(virDomainPtr dom, VIR_PERF_PARAM_CACHE_L1DRA, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DRM, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DWA, VIR_TYPED_PARAM_BOOLEAN, + VIR_PERF_PARAM_CACHE_L1DWM, VIR_TYPED_PARAM_BOOLEAN, NULL) < 0) return -1; diff --git a/src/remote/remote_protocol.x b/src/remote/remote_protocol.x index 6445685..3da6868 100644 --- a/src/remote/remote_protocol.x +++ b/src/remote/remote_protocol.x @@ -101,7 +101,7 @@ const REMOTE_DOMAIN_SCHEDULER_PARAMETERS_MAX = 16; const REMOTE_DOMAIN_BLKIO_PARAMETERS_MAX = 16; /* Upper limit on list of memory parameters. */ -const REMOTE_DOMAIN_MEMORY_PARAMETERS_MAX = 16; +const REMOTE_DOMAIN_MEMORY_PARAMETERS_MAX = 32; /* Upper limit on list of blockio tuning parameters. */ const REMOTE_DOMAIN_BLOCK_IO_TUNE_PARAMETERS_MAX = 32; diff --git a/src/util/virperf.c b/src/util/virperf.c index c4cea33..384a3e1 100644 --- a/src/util/virperf.c +++ b/src/util/virperf.c @@ -44,7 +44,8 @@ VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST, "branch_instructions", "branch_misses", "bus_cycles", "stalled_cycles_frontend", "stalled_cycles_backend", "ref_cpu_cycles", - "cache_l1dra", "cache_l1drm", "cache_l1dwa"); + "cache_l1dra", "cache_l1drm", "cache_l1dwa", + "cache_l1dwm"); struct virPerfEvent { int type; @@ -128,6 +129,11 @@ static struct virPerfEventAttr attrs[] = { .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)}, + {.type = VIR_PERF_EVENT_CACHE_L1DWM, + .attrType = PERF_TYPE_HW_CACHE, + .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | + (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | + (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)}, }; typedef struct virPerfEventAttr *virPerfEventAttrPtr; diff --git a/src/util/virperf.h b/src/util/virperf.h index 5671ec7..13967d8 100644 --- a/src/util/virperf.h +++ b/src/util/virperf.h @@ -50,6 +50,7 @@ typedef enum { VIR_PERF_EVENT_CACHE_L1DRA, /* Count of read accesses for level 1 data cache */ VIR_PERF_EVENT_CACHE_L1DRM, /* Count of read misses for level 1 data cache */ VIR_PERF_EVENT_CACHE_L1DWA, /* Count of write accesses for level 1 data cache */ + VIR_PERF_EVENT_CACHE_L1DWM, /* Count of write misses for level 1 data cache */ VIR_PERF_EVENT_LAST } virPerfEventType; diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml index e9d29a1..4351fb2 100644 --- a/tests/genericxml2xmlindata/generic-perf.xml +++ b/tests/genericxml2xmlindata/generic-perf.xml @@ -29,6 +29,7 @@ <event name='cache_l1dra' enabled='yes'/> <event name='cache_l1drm' enabled='yes'/> <event name='cache_l1dwa' enabled='yes'/> + <event name='cache_l1dwm' enabled='yes'/> </perf> <devices> </devices> diff --git a/tools/virsh.pod b/tools/virsh.pod index c06c96b..de7856b 100644 --- a/tools/virsh.pod +++ b/tools/virsh.pod @@ -947,8 +947,9 @@ I<--perf> returns the statistics of all enabled perf events: "perf.stalled_cycles_backend" - the count of stalled backend cpu cycles, "perf.ref_cpu_cycles" - the count of ref cpu cycles, "perf.cache_l1dra" - the count of read accesses for level 1 data cache, -"perf.cache_l1drm" - the count of read misses for level 1 data cache -"perf.cache_l1dwa" - the count of write accesses for level 1 data cache +"perf.cache_l1drm" - the count of read misses for level 1 data cache, +"perf.cache_l1dwa" - the count of write accesses for level 1 data cache, +"perf.cache_l1dwm" - the count of write misses for level 1 data cache See the B<perf> command for more details about each event. @@ -2319,6 +2320,8 @@ B<Valid perf event names> data cache by applications running on the platform. cache_l1dwa - Provides the count of total write accesses for level 1 data cache by applications running on the platform. + cache_l1dwm - Provides the count of total write misses for level 1 + data cache by applications running on the platform. B<Note>: The statistics can be retrieved using the B<domstats> command using the I<--perf> flag. -- 1.9.3