[PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang <jiangyifei(a)huawei.com&gt; Signed-off-by: Yipeng Yin <yinyipeng1(a)huawei.com&gt; --- target/riscv/kvm.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 687dd4b621..0d924be33f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,18 @@ #include "qemu/log.h" #include "hw/loader.h" +static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx) +{ + __u64 id = KVM_REG_RISCV | type | idx; + + if (riscv_cpu_is_32bit(env)) { + id |= KVM_REG_SIZE_U32; + } else { + id |= KVM_REG_SIZE_U64; + } + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret = 0; + target_ulong isa; + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + __u64 id; + + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa)); + ret = kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + env->misa = isa | RVXLEN; + + return ret; } int kvm_arch_msi_data_to_gsi(uint32_t data) -- 2.19.1