[libvirt] [PATCH 3/7] perf: add cache_l1dwa perf event support

This patch adds support and documentation for a generalized hardware cache event named cache_l1dwa perf event for measuring write accesses on level 1 data cache Signed-off-by: Nitesh Konkar <nitkon12(a)linux.vnet.ibm.com&gt; --- docs/formatdomain.html.in | 7 +++++++ docs/news.xml | 4 ++-- docs/schemas/domaincommon.rng | 1 + include/libvirt/libvirt-domain.h | 11 +++++++++++ src/libvirt-domain.c | 3 +++ src/qemu/qemu_driver.c | 1 + src/util/virperf.c | 7 ++++++- src/util/virperf.h | 1 + tests/genericxml2xmlindata/generic-perf.xml | 1 + tools/virsh.pod | 3 +++ 10 files changed, 36 insertions(+), 3 deletions(-) diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in index 9db6d38..4c24ead 100644 --- a/docs/formatdomain.html.in +++ b/docs/formatdomain.html.in @@ -1939,6 +1939,7 @@ &lt;event name='ref_cpu_cycles' enabled='no'/&gt; &lt;event name='cache_l1dra' enabled='no'/&gt; &lt;event name='cache_l1drm' enabled='no'/&gt; + &lt;event name='cache_l1dwa' enabled='no'/&gt; &lt;/perf&gt; ... </pre> @@ -2029,6 +2030,12 @@ applications running on the platform</td> <td><code>perf.cache_l1drm</code></td> </tr> + <tr> + <td><code>cache_l1dwa</code></td> + <td>the count of total write accesses for level 1 data cache by + applications running on the platform</td> + <td><code>perf.cache_l1dwa</code></td> + </tr> </table> <h3><a name="elementsDevices">Devices</a></h3> diff --git a/docs/news.xml b/docs/news.xml index fe83ce4..129cbc9 100644 --- a/docs/news.xml +++ b/docs/news.xml @@ -107,8 +107,8 @@ Add support to get the count of branch instructions executed, branch misses, bus cycles, stalled frontend cpu cycles, stalled backend cpu cycles, ref cpu cycles, - cache l1dra and cache l1drm by applications running on - the platform. + cache l1dra, cache l1drm and cache l1dwa by applications + running on the platform. </description> </change> <change> diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng index 6a7c83c..9ad5937 100644 --- a/docs/schemas/domaincommon.rng +++ b/docs/schemas/domaincommon.rng @@ -435,6 +435,7 @@ <value>ref_cpu_cycles</value> <value>cache_l1dra</value> <value>cache_l1drm</value> + <value>cache_l1dwa</value> </choice> </attribute> <attribute name="enabled"> diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h index abf0e14..b02eb49 100644 --- a/include/libvirt/libvirt-domain.h +++ b/include/libvirt/libvirt-domain.h @@ -2210,6 +2210,17 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats); */ # define VIR_PERF_PARAM_CACHE_L1DRM "cache_l1drm" +/* + * VIR_PERF_PARAM_CACHE_L1DWA: + * + * Macro for typed parameter name that represents cache_l1dwa + * perf event which can be used to measure the count of total + * write accesses for level 1 data cache by applications running + * on the platform. It corresponds to the "perf.cache_l1dwa" + * field in the *Stats APIs. + */ +# define VIR_PERF_PARAM_CACHE_L1DWA "cache_l1dwa" + int virDomainGetPerfEvents(virDomainPtr dom, virTypedParameterPtr *params, int *nparams, diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c index 7183905..92e8bf1 100644 --- a/src/libvirt-domain.c +++ b/src/libvirt-domain.c @@ -11256,6 +11256,9 @@ virConnectGetDomainCapabilities(virConnectPtr conn, * "perf.cache_l1drm" - The count of total read misses for level 1 data * cache as unsigned long long. It is produced by * cache_l1drm perf event. + * "perf.cache_l1dwa" - The count of total write accesses for level 1 data + * cache as unsigned long long. It is produced by + * cache_l1dwa perf event. * * Note that entire stats groups or individual stat fields may be missing from * the output in case they are not supported by the given hypervisor, are not diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c index da50f95..c2f55d3 100644 --- a/src/qemu/qemu_driver.c +++ b/src/qemu/qemu_driver.c @@ -9879,6 +9879,7 @@ qemuDomainSetPerfEvents(virDomainPtr dom, VIR_PERF_PARAM_REF_CPU_CYCLES, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DRA, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DRM, VIR_TYPED_PARAM_BOOLEAN, + VIR_PERF_PARAM_CACHE_L1DWA, VIR_TYPED_PARAM_BOOLEAN, NULL) < 0) return -1; diff --git a/src/util/virperf.c b/src/util/virperf.c index 4b9fc9a..c4cea33 100644 --- a/src/util/virperf.c +++ b/src/util/virperf.c @@ -44,7 +44,7 @@ VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST, "branch_instructions", "branch_misses", "bus_cycles", "stalled_cycles_frontend", "stalled_cycles_backend", "ref_cpu_cycles", - "cache_l1dra", "cache_l1drm"); + "cache_l1dra", "cache_l1drm", "cache_l1dwa"); struct virPerfEvent { int type; @@ -123,6 +123,11 @@ static struct virPerfEventAttr attrs[] = { .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)}, + {.type = VIR_PERF_EVENT_CACHE_L1DWA, + .attrType = PERF_TYPE_HW_CACHE, + .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | + (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | + (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)}, }; typedef struct virPerfEventAttr *virPerfEventAttrPtr; diff --git a/src/util/virperf.h b/src/util/virperf.h index 37058b0..5671ec7 100644 --- a/src/util/virperf.h +++ b/src/util/virperf.h @@ -49,6 +49,7 @@ typedef enum { VIR_PERF_EVENT_REF_CPU_CYCLES, /* Count of ref cpu cycles */ VIR_PERF_EVENT_CACHE_L1DRA, /* Count of read accesses for level 1 data cache */ VIR_PERF_EVENT_CACHE_L1DRM, /* Count of read misses for level 1 data cache */ + VIR_PERF_EVENT_CACHE_L1DWA, /* Count of write accesses for level 1 data cache */ VIR_PERF_EVENT_LAST } virPerfEventType; diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml index bb8a085..e9d29a1 100644 --- a/tests/genericxml2xmlindata/generic-perf.xml +++ b/tests/genericxml2xmlindata/generic-perf.xml @@ -28,6 +28,7 @@ <event name='ref_cpu_cycles' enabled='yes'/> <event name='cache_l1dra' enabled='yes'/> <event name='cache_l1drm' enabled='yes'/> + <event name='cache_l1dwa' enabled='yes'/> </perf> <devices> </devices> diff --git a/tools/virsh.pod b/tools/virsh.pod index c1bdbdd..c06c96b 100644 --- a/tools/virsh.pod +++ b/tools/virsh.pod @@ -948,6 +948,7 @@ I<--perf> returns the statistics of all enabled perf events: "perf.ref_cpu_cycles" - the count of ref cpu cycles, "perf.cache_l1dra" - the count of read accesses for level 1 data cache, "perf.cache_l1drm" - the count of read misses for level 1 data cache +"perf.cache_l1dwa" - the count of write accesses for level 1 data cache See the B<perf> command for more details about each event. @@ -2316,6 +2317,8 @@ B<Valid perf event names> data cache by applications running on the platform. cache_l1drm - Provides the count of total read misses for level 1 data cache by applications running on the platform. + cache_l1dwa - Provides the count of total write accesses for level 1 + data cache by applications running on the platform. B<Note>: The statistics can be retrieved using the B<domstats> command using the I<--perf> flag. -- 1.9.3