Re: [libvirt] [V3] RFC for support cache tune in libvirt

> > > <cache> > <bank type="l3" size="56320" units="KiB" cpus="0,2,3,6,7,8"/> > <bank type="l3" size="56320" units="KiB" cpus="3,4,5,9,10,11"/> > yes, I like this too, it could tell the the resource sharing logic by cpus. Another thinking is that if kernel enable CDP, it will split l3 cache to code / data type <cache> <bank type="l3code" size="28160" units="KiB" cpus="0,2,3,6,7,8"/> <bank type="l3data" size="28160" units="KiB" cpus="3,4,5,9,10,11"/> So these information should not only from /sys/devices/system/cpu/cpu0/cache/index3/size , also depend on if linux resctrl under /sys/fs/resctrl/ > <bank type="l2" size="256" units="KiB" cpus="0"/> > I think on your system you don't enable SMT, so if on a system which enabled SMT. we will have: <bank type="l2" size="256" units="KiB" cpus="0, 44"/> <bank type="l2" size="256" units="KiB" cpus="1"/> > <bank type="l2" size="256" units="KiB" cpus="2"/> > <bank type="l2" size="256" units="KiB" cpus="3"/> > <bank type="l2" size="256" units="KiB" cpus="4"/> > <bank type="l2" size="256" units="KiB" cpus="5"/> > <bank type="l2" size="256" units="KiB" cpus="6"/> > <bank type="l2" size="256" units="KiB" cpus="7"/> > <bank type="l2" size="256" units="KiB" cpus="8"/> > <bank type="l2" size="256" units="KiB" cpus="9"/> > <bank type="l2" size="256" units="KiB" cpus="10"/> > <bank type="l2" size="256" units="KiB" cpus="11"/> > <bank type="l1i" size="256" units="KiB" cpus="0"/> > <bank type="l1i" size="256" units="KiB" cpus="1"/> > <bank type="l1i" size="256" units="KiB" cpus="2"/> > <bank type="l1i" size="256" units="KiB" cpus="3"/> > <bank type="l1i" size="256" units="KiB" cpus="4"/> > <bank type="l1i" size="256" units="KiB" cpus="5"/> > <bank type="l1i" size="256" units="KiB" cpus="6"/> > <bank type="l1i" size="256" units="KiB" cpus="7"/> > <bank type="l1i" size="256" units="KiB" cpus="8"/> > <bank type="l1i" size="256" units="KiB" cpus="9"/> > <bank type="l1i" size="256" units="KiB" cpus="10"/> > <bank type="l1i" size="256" units="KiB" cpus="11"/> > <bank type="l1d" size="256" units="KiB" cpus="0"/> > <bank type="l1d" size="256" units="KiB" cpus="1"/> > <bank type="l1d" size="256" units="KiB" cpus="2"/> > <bank type="l1d" size="256" units="KiB" cpus="3"/> > <bank type="l1d" size="256" units="KiB" cpus="4"/> > <bank type="l1d" size="256" units="KiB" cpus="5"/> > <bank type="l1d" size="256" units="KiB" cpus="6"/> > <bank type="l1d" size="256" units="KiB" cpus="7"/> > <bank type="l1d" size="256" units="KiB" cpus="8"/> > <bank type="l1d" size="256" units="KiB" cpus="9"/> > <bank type="l1d" size="256" units="KiB" cpus="10"/> > <bank type="l1d" size="256" units="KiB" cpus="11"/> > </cache> > > hmm... l2 and l1 cache are per core, I am not sure if we really need to tune the l2 and l1 cache at all, that's too low level....... Per my understanding, if we expose this kinds of capabilities, we should support to manage it, just wonder if we are too early to expose it since low level (linux kernel) have not support it yet.