[libvirt] [PATCH 5/7] perf: add cache_l1dpa perf event support

This patch adds support and documentation for a generalized hardware cache event named cache_l1dpa perf event for measuring prefetch accesses on level 1 data cache Signed-off-by: Nitesh Konkar <nitkon12(a)linux.vnet.ibm.com&gt; --- docs/formatdomain.html.in | 7 +++++++ docs/news.xml | 4 ++-- docs/schemas/domaincommon.rng | 1 + include/libvirt/libvirt-domain.h | 11 +++++++++++ src/libvirt-domain.c | 3 +++ src/qemu/qemu_driver.c | 1 + src/util/virperf.c | 7 ++++++- src/util/virperf.h | 1 + tests/genericxml2xmlindata/generic-perf.xml | 1 + tools/virsh.pod | 5 ++++- 10 files changed, 37 insertions(+), 4 deletions(-) diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in index d5c2aad..245120d 100644 --- a/docs/formatdomain.html.in +++ b/docs/formatdomain.html.in @@ -1941,6 +1941,7 @@ &lt;event name='cache_l1drm' enabled='no'/&gt; &lt;event name='cache_l1dwa' enabled='no'/&gt; &lt;event name='cache_l1dwm' enabled='no'/&gt; + &lt;event name='cache_l1dpa' enabled='no'/&gt; &lt;/perf&gt; ... </pre> @@ -2043,6 +2044,12 @@ applications running on the platform</td> <td><code>perf.cache_l1dwm</code></td> </tr> + <tr> + <td><code>cache_l1dpa</code></td> + <td>the count of total prefetch accesses for level 1 data + cache by applications running on the platform</td> + <td><code>perf.cache_l1dpa</code></td> + </tr> </table> <h3><a name="elementsDevices">Devices</a></h3> diff --git a/docs/news.xml b/docs/news.xml index eb2e815..1f362e2 100644 --- a/docs/news.xml +++ b/docs/news.xml @@ -107,8 +107,8 @@ Add support to get the count of branch instructions executed, branch misses, bus cycles, stalled frontend cpu cycles, stalled backend cpu cycles, ref cpu cycles, - cache l1dra, cache l1drm, cache l1dwa and cache l1dwm by - applications running on the platform. + cache l1dra, cache l1drm, cache l1dwa, cache l1dwm, + cache l1dpa by applications running on the platform. </description> </change> <change> diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng index 91ad636..83a205a 100644 --- a/docs/schemas/domaincommon.rng +++ b/docs/schemas/domaincommon.rng @@ -437,6 +437,7 @@ <value>cache_l1drm</value> <value>cache_l1dwa</value> <value>cache_l1dwm</value> + <value>cache_l1dpa</value> </choice> </attribute> <attribute name="enabled"> diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h index 0d8d731..9db4969 100644 --- a/include/libvirt/libvirt-domain.h +++ b/include/libvirt/libvirt-domain.h @@ -2232,6 +2232,17 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats); */ # define VIR_PERF_PARAM_CACHE_L1DWM "cache_l1dwm" +/* + * VIR_PERF_PARAM_CACHE_L1DPA: + * + *Macro for typed parameter name that represents cache_l1dpa + *perf event which can be used to measure the count of total + *prefetch accesses for level 1 data cache by applications + *running on the platform. It corresponds to the + *"perf.cache_l1dpa" field in the *Stats APIs. + */ +# define VIR_PERF_PARAM_CACHE_L1DPA "cache_l1dpa" + int virDomainGetPerfEvents(virDomainPtr dom, virTypedParameterPtr *params, int *nparams, diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c index 3a5a776..089d3f5 100644 --- a/src/libvirt-domain.c +++ b/src/libvirt-domain.c @@ -11262,6 +11262,9 @@ virConnectGetDomainCapabilities(virConnectPtr conn, * "perf.cache_l1dwm" - The count of total write misses for level 1 data * cache as unsigned long long. It is produced by * cache_l1dwm perf event. + * "perf.cache_l1dpa" - The count of total prefetch accesses for level 1 + * data cache as unsigned long long. It is produced by + * cache_l1dpa perf event. * * Note that entire stats groups or individual stat fields may be missing from * the output in case they are not supported by the given hypervisor, are not diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c index 205d2d2..8acb706 100644 --- a/src/qemu/qemu_driver.c +++ b/src/qemu/qemu_driver.c @@ -9881,6 +9881,7 @@ qemuDomainSetPerfEvents(virDomainPtr dom, VIR_PERF_PARAM_CACHE_L1DRM, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DWA, VIR_TYPED_PARAM_BOOLEAN, VIR_PERF_PARAM_CACHE_L1DWM, VIR_TYPED_PARAM_BOOLEAN, + VIR_PERF_PARAM_CACHE_L1DPA, VIR_TYPED_PARAM_BOOLEAN, NULL) < 0) return -1; diff --git a/src/util/virperf.c b/src/util/virperf.c index 384a3e1..df2a91a 100644 --- a/src/util/virperf.c +++ b/src/util/virperf.c @@ -45,7 +45,7 @@ VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST, "bus_cycles", "stalled_cycles_frontend", "stalled_cycles_backend", "ref_cpu_cycles", "cache_l1dra", "cache_l1drm", "cache_l1dwa", - "cache_l1dwm"); + "cache_l1dwm", "cache_l1dpa"); struct virPerfEvent { int type; @@ -134,6 +134,11 @@ static struct virPerfEventAttr attrs[] = { .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)}, + {.type = VIR_PERF_EVENT_CACHE_L1DPA, + .attrType = PERF_TYPE_HW_CACHE, + .attrConfig = (PERF_COUNT_HW_CACHE_L1D) | + (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | + (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)}, }; typedef struct virPerfEventAttr *virPerfEventAttrPtr; diff --git a/src/util/virperf.h b/src/util/virperf.h index 13967d8..78c8557 100644 --- a/src/util/virperf.h +++ b/src/util/virperf.h @@ -51,6 +51,7 @@ typedef enum { VIR_PERF_EVENT_CACHE_L1DRM, /* Count of read misses for level 1 data cache */ VIR_PERF_EVENT_CACHE_L1DWA, /* Count of write accesses for level 1 data cache */ VIR_PERF_EVENT_CACHE_L1DWM, /* Count of write misses for level 1 data cache */ + VIR_PERF_EVENT_CACHE_L1DPA, /* Count of prefetch accesses for level 1 data cache */ VIR_PERF_EVENT_LAST } virPerfEventType; diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml index 4351fb2..a575f89 100644 --- a/tests/genericxml2xmlindata/generic-perf.xml +++ b/tests/genericxml2xmlindata/generic-perf.xml @@ -30,6 +30,7 @@ <event name='cache_l1drm' enabled='yes'/> <event name='cache_l1dwa' enabled='yes'/> <event name='cache_l1dwm' enabled='yes'/> + <event name='cache_l1dpa' enabled='yes'/> </perf> <devices> </devices> diff --git a/tools/virsh.pod b/tools/virsh.pod index de7856b..c599aa5 100644 --- a/tools/virsh.pod +++ b/tools/virsh.pod @@ -949,7 +949,8 @@ I<--perf> returns the statistics of all enabled perf events: "perf.cache_l1dra" - the count of read accesses for level 1 data cache, "perf.cache_l1drm" - the count of read misses for level 1 data cache, "perf.cache_l1dwa" - the count of write accesses for level 1 data cache, -"perf.cache_l1dwm" - the count of write misses for level 1 data cache +"perf.cache_l1dwm" - the count of write misses for level 1 data cache, +"perf.cache_l1dpa" - the count of prefetch accesses for level 1 data cache See the B<perf> command for more details about each event. @@ -2322,6 +2323,8 @@ B<Valid perf event names> data cache by applications running on the platform. cache_l1dwm - Provides the count of total write misses for level 1 data cache by applications running on the platform. + cache_l1dpa - Provides the count of total prefetch accesses for + level 1 data cache by applications running on the platform. B<Note>: The statistics can be retrieved using the B<domstats> command using the I<--perf> flag. -- 1.9.3